CN114038791A - Preparation method of STI structure - Google Patents

Abstract

The application discloses a preparation method of an STI structure, which comprises the following steps: forming an O3 type oxide layer on the hard mask layer, wherein the hard mask layer is formed on a first oxide layer formed on the substrate; forming a trench in the O3 type oxide layer, the hard mask layer and the substrate; forming a second oxide layer, wherein the second oxide layer covers the surface of the groove; forming a third oxide layer, wherein the third oxide layer fills the groove; and planarizing by a CMP process to expose the hard mask layer outside the trench. The method comprises forming O on the hard mask layer during the preparation of STI structure₃Type oxide layer due to the presence of O₃The type oxidation layer is used as a buffer layer, and can reduce the grinding rate of a subsequent CMP process, thereby improving the appearance after the CMP process, reducing the dish-shaped defect and further improving the reliability and yield of products.

Description

Preparation method of STI structure

Technical Field

The application relates to the technical field of semiconductor manufacturing, in particular to a preparation method of a Shallow Trench Isolation (STI) structure.

Background

STI structures are widely used in semiconductor manufacturing (especially in the process of 40/28 nm and below) as an insulating structure between Active Areas (AA) of semiconductor devices.

In the related art, the method for manufacturing the STI structure includes: sequentially forming a liner oxide layer and a hard mask layer on a substrate; forming a trench in a substrate by a photolithography process; depositing an oxide layer to fill the trench with the oxide layer; the oxide layer outside the trench is removed by planarization through a Chemical Mechanical Polishing (CMP) process.

However, after planarization by the CMP process, there is a high probability of forming "dishing defect" (CMP), thereby affecting the topography of the device and reducing the reliability and yield of the product.

Disclosure of Invention

The application provides a preparation method of an STI structure, which can solve the problem that the reliability and yield of products are low because dishing defects are easily generated after CMP planarization in the preparation method of the STI structure provided in the related technology.

In one aspect, an embodiment of the present application provides a method for manufacturing an STI structure, including:

forming an O3 type oxide layer on a hard mask layer, the hard mask layer being formed on a first oxide layer formed on a substrate;

forming a trench in the O3 type oxide layer, the hard mask layer and the substrate;

forming a second oxide layer, wherein the second oxide layer covers the surface of the groove;

forming a third oxide layer, wherein the third oxide layer fills the groove;

and planarizing by a CMP process to expose the hard mask layer outside the groove.

Optionally, the hard mask layer comprises a silicon nitride layer.

Optionally, the hard mask layer has a thickness of 300 to 800 angstroms.

Optionally, the forming an O3 type oxide layer on the hard mask layer includes:

and depositing the O3 type oxide layer on the hard mask layer by a CVD (chemical vapor deposition) process, wherein the introduced reaction gas comprises ozone in the deposition process.

Optionally, during the deposition process, the flow rate of ozone is 15000SCCM to 35000 SCCM.

Optionally, the thickness of the O3 type oxide layer is 10 to 100 angstroms.

Optionally, the forming the second oxide layer includes:

the second oxide layer is formed by an ISSG process.

Optionally, the forming a third oxide layer includes:

depositing silicon dioxide by a HARP CVD process to form the third oxide layer.

The technical scheme at least comprises the following advantages:

by forming O on the hard mask layer during the fabrication of STI structure₃Type oxide layer due to the presence of O₃The type oxidation layer is used as a buffer layer, and can reduce the grinding rate of a subsequent CMP process, thereby improving the appearance after the CMP process, reducing the dish-shaped defect and further improving the reliability and yield of products.

Drawings

In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a flow chart of a method for fabricating an STI structure provided in an exemplary embodiment of the present application;

fig. 2 to 6 are schematic views illustrating the formation of an STI structure according to an exemplary embodiment of the present application.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.

Referring to fig. 1, a flow chart of a method for fabricating an STI structure according to an exemplary embodiment of the present application is shown, where the method is applicable to a semiconductor process with a process node of 28 nm or less, and the method includes:

step 101, forming O on the hard mask layer₃The hard mask layer is formed on the first oxide layer, and the first oxide layer is formed on the substrate.

Referring to FIG. 2, the formation of O on the hard mask layer is shown₃The cross-sectional view of the type oxide layer. As shown in fig. 2, a first oxide layer 220 is formed on a substrate 210, and a hard mask layer 230 is formed on the first oxide layer 220. Wherein the first oxide layer 220 may comprise silicon dioxide (SiO)₂) A layer that may form a first oxide layer 220 on the substrate 210 through a thermal oxidation process; the hard mask layer 230 may include a silicon nitride (SiN) layer, the hard mask layer 230 may be formed by depositing silicon nitride on the first oxide layer 220 through a Chemical Vapor Deposition (CVD) process, and the thickness of the hard mask layer 230 may be 300 angstroms

To 800 angstroms (e.g., it may be 550 angstroms).

Illustratively, O may be deposited on the hard mask layer 230 by a CVD process₃A patterned oxide layer 240, wherein the reaction gas introduced during the deposition process comprises ozone (O)₃) O is a radical of₃The thickness of the type oxide layer 240 is 10 to 100 angstroms (e.g., it may be 50 angstroms).

In the embodiment of the application, the formed O can be formed by setting the appropriate deposition parameters₃The type oxide layer 240 has a better buffer effect, for example: during deposition, the flow rate of ozone is 15000 standard milliliter per minute (SCCM) to 35000SCCM (e.g., which may be 27000SCCM), the gas pressure is 300 Torr to 900 Torr (e.g., which may be 600 Torr), and the temperature of deposition is 200 degrees celsius (° c) to 600 degrees celsius (e.g., which may be 400 degrees celsius).

Step 102, at O₃A trench is formed in the type oxide layer, the hard mask layer and the substrate.

Referring to fig. 3, a cross-sectional schematic view of forming a trench is shown. Illustratively, as shown in FIG. 3, step 102 includes, but is not limited to: by a photolithographic process at O₃The type oxide layer 240 is covered with a photoresist to expose a target region (the target region is a region corresponding to the removal trench 300), and etching is performed to a predetermined depth in the substrate 210 of the target region to form the removal trench 300.

Step 103, forming a second oxide layer, wherein the second oxide layer covers the surface of the trench.

Referring to fig. 4, a schematic cross-sectional view of forming a second oxide layer is shown. Illustratively, as shown in fig. 4, the second oxide layer 251 may be generated on the surface of the trench 300 and over the substrate 210 by an in-situ steam generation (ISSG) process.

And step 104, forming a third oxide layer, wherein the third oxide layer fills the groove.

Referring to fig. 5, a schematic cross-sectional view of forming a third oxide layer is shown. Illustratively, as shown in fig. 5, the third oxide layer 252 may be formed by depositing silicon dioxide by a High Aspect Ratio (HARP) CVD process, and the third oxide layer 252 fills the trench 300.

In step 105, planarization is performed by Chemical Mechanical Polishing (CMP) process to expose the hard mask layer outside the trench.

Referring to fig. 6, a schematic cross-sectional view after planarization is shown. Illustratively, as shown in FIG. 6, due to the presence of O₃The type oxide layer 240 serves as a buffer layer, which reduces the polishing rate of the CMP process, and after planarization by the CMP process, no dishing defect occurs in a region (as shown by a dotted line in fig. 6) where dishing defects are likely to occur, and the topography is very flat.

In summary, in the embodiment of the present application, during the process of fabricating the STI structure, O is formed on the hard mask layer₃Type oxide layer due to the presence of O₃The type oxidation layer is used as a buffer layer, and can reduce the grinding rate of a subsequent CMP process, thereby improving the appearance after the CMP process, reducing the dish-shaped defect and further improving the reliability and yield of products.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims (8)

1. A method for fabricating an STI structure, comprising:

forming O on the hard mask layer₃The hard mask layer is formed on a first oxidation layer, and the first oxidation layer is formed on the substrate;

at the O₃Forming a trench in the type oxide layer, the hard mask layer and the substrate;

forming a second oxide layer, wherein the second oxide layer covers the surface of the groove;

forming a third oxide layer, wherein the third oxide layer fills the groove;

and planarizing by a CMP process to expose the hard mask layer outside the groove.

2. The method of claim 1, wherein the hard mask layer comprises a silicon nitride layer.

3. The method of claim 2, wherein the hard mask layer has a thickness of 300 to 800 angstroms.

4. The method of claim 2, wherein forming O on the hard mask layer₃A type oxide layer comprising:

depositing the O on the hard mask layer by a CVD process₃And the reaction gas introduced in the deposition process comprises ozone.

5. The method of claim 4, wherein the flow of ozone during the deposition process is 15000 to 35000 SCCM.

6. The method of claim 1, wherein said O is₃The thickness of the type oxide layer is 10 to 100 angstroms.

7. The method of any of claims 1 to 6, wherein the forming a second oxide layer comprises:

the second oxide layer is formed by an ISSG process.

8. The method of claim 7, wherein the forming a third oxide layer comprises:

depositing silicon dioxide by a HARP CVD process to form the third oxide layer.

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