JP2001250817A - Method of dry etching and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of dry etching by which a high selection rate can be obtained and a method of manufacturing a semiconductor device by which the manufacturing yield or performance of a semiconductor device can be improved by using the method of dry etching. SOLUTION: In this method of dry etching, CH2F2 is used as an etching gas at the time of dry etching. When the etching gas is composed of a plurality of gases, the occupying ratio of the CH2F2 in the mixed gas is adjusted to >=20% and, when a C-containing gas is mixed in the mixed gas, the occupying ratio of the CH2F2 and C-containing gas in the mixed gas is adjusted to >=20% and that of the CH2F2 in the mixed gas is adjusted to >=5%. Consequently, etching takes place in the bottom section of a contact hole, but does not take place on a resist 31, because a resulted product 32 of reaction accumulates on the resist 31. Therefore, the contact hole can be formed without damaging the masking property of the resist 21.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dry etching method capable of etching with a high selectivity and a method of manufacturing a semiconductor device, and more particularly to a dry etching technique used in manufacturing a semiconductor device with advanced miniaturization. Things.

[0002]

2. Description of the Related Art In recent years, miniaturization of semiconductor devices has been remarkable. The lithography technology and the etching technology are the key technologies for this miniaturization, and various researches on the exposure light source and the mask material in the lithography, the gas used in the etching, and the like are being advanced.

[0003] About ten years ago, an isotropic wet etching method using a solution and an isotropic dry etching method using a gas were found about ten years ago. Then, as the miniaturization of semiconductor devices progresses, reactive ion etching (RI
E: Reactive Ion Etching) method has begun to be introduced. This R
The introduction of the IE method has made it possible to realize today's ultra-high density semiconductor memory devices. Thus, while the etching technology has changed with the miniaturization of semiconductor devices,
The fundamental processing technology for semiconductor devices, in which a base material is selectively etched using a resist patterned by lithography as a mask, has not changed.

A conventional method for etching a semiconductor device will be described with reference to FIGS. 31 (a) and 31 (b). FIG.
(A) and (b) show a case where a contact hole or the like having a high aspect ratio is formed in an interlayer insulating film by an RIE method, and are cross-sectional views of a semiconductor device during and after formation of a contact hole, respectively. .

In order to etch a semiconductor device,
As shown in FIG. 31 (a), first, an interlayer insulating film of SiO_Twofilm
Resist 101 patterned into a desired pattern on 100
To form Then, using this resist 101 as a mask
Etching by RIE to form contact holes
To achieve. Conventionally, SiO_TwoCF gas for etching_Four, C_TwoF
₆F system and CHF_Three, CHF_ThreeTo H_TwoH-F gas mixed with
It has been. As shown in FIG.
In the initial stage, the resist 101 functions as a mask.

However, due to the recent trend toward thinner resists due to the miniaturization of semiconductor devices and the tendency to increase the aspect ratio of the contact holes, the resist cannot withstand etching until the contact holes are completely opened. FIG. 31B shows this case, and the resist 101 is entirely etched during the formation of the contact hole. As described above, since the etching mask is lost during the etching, the surface of the SiO ₂ film 100 other than the contact hole forming portion is also etched.

As described above, as the miniaturization of a semiconductor device progresses, the resist serving as a mask becomes thinner. Therefore, while the region to be etched is being etched by the RIE method, the etching of the peripheral resist also progresses, and the function as a mask is not achieved. This phenomenon is particularly noticeable when forming a contact hole or trench having a high aspect ratio, and causes a reduction in manufacturing yield and a deterioration in performance of a semiconductor device. Therefore, a technique for avoiding the influence of the failure of the mask property of the resist is indispensable.

[0008]

As described above, in the conventional dry etching method, the maskability of the resist is broken particularly when etching with a high aspect ratio is performed due to the thinning of the resist accompanying the miniaturization of the semiconductor device. There was a problem.

Further, there has been a problem that the failure of the mask property of the resist in the etching causes a reduction in the manufacturing yield of the semiconductor device and a deterioration in the performance of the semiconductor device.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a dry etching method capable of obtaining a high selectivity.

Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving the manufacturing yield and the performance of the semiconductor device by using a dry etching method capable of obtaining a high selectivity.

[0012]

In order to achieve the above object, a first dry etching method according to the present invention comprises a step of forming a concave portion having an aspect ratio of at least 0.5 in an etching region of an object to be etched; using an etching gas containing ₂ F _2, comprising the step of etching of the recess, the etching gas used in the step of etching of said recess, said etching gas contains at least one composition of carbon If the gas to part of only CH ₂ F _2, the ratio of the CH ₂ F ₂ occupied in the etching gas is 20% or more, in addition to the CH ₂ F _2, and at least a part of the composition of carbon When a gas is contained in the etching gas, the ratio of the gas having at least a part of the composition of the carbon and the CH ₂ F _{2 in} the etching gas to the etching gas is 20% or more and occupied in the etching gas. The ratio of the CH ₂ F ₂ is at least 5%.

Furthermore the second dry etching process of the present invention comprises steps of forming a mask material for etching on the etching object, the steps of an aspect ratio on the mask material to form at least 0.5 recess, CH ₂ using an etching gas containing F _2, comprising the step of etching of the recess, the etching gas used in the step of etching of said recess, said etching gas contains,
For the gas to at least a part of the composition of carbon only CH ₂ F _2, the ratio of the CH ₂ F ₂ occupied in the etching gas 20%
As described above, in addition to CH ₂ F ₂ , when a gas containing at least a part of the composition of carbon is contained in the etching gas,
Ratio of the CH ₂ F ₂ gas and the ratio of the CH ₂ F ₂ to at least part of the composition of the carbon occupying in the etching gas is occupied in and the etching gas is 20% or more is 5% or more It is characterized by:

Further, in a third dry etching method according to the present invention, a step of forming a mask material for etching on an object to be etched, and forming a recess having an aspect ratio of at least 0.5 in the mask material and the object to be etched. A step of etching the concave portion using an etching gas containing CH ₂ F ₂ , wherein the etching gas used in the step of etching the concave portion contains carbon contained in the etching gas. If at least a portion to the gas composition is only CH ₂ F _2, the ratio of the CH ₂ F ₂ occupied in the etching gas is 20% or more, in addition to the CH ₂ F _2, at least the composition of carbon When the etching gas contains a gas to be used as a part of the gas, the gas containing at least a part of the composition of the carbon occupying the etching gas and the CH ₂ F
₂ is 20% or more, and the ratio of the CH ₂ F _{2 in} the etching gas is 5% or more.

Further, in the method of manufacturing a semiconductor device according to the present invention, a step of forming a first mask material on a semiconductor substrate; a step of forming a second mask material on the first mask material; Patterning a material to form a concave portion having an aspect ratio of at least 0.5, and etching the first mask material in a region corresponding to the concave portion using an etching gas containing CH ₂ F ₂ ; Forming a trench by etching the semiconductor substrate in a region corresponding to the concave portion, wherein the etching gas used in the step of etching the first mask material has a composition of carbon contained in the etching gas. for the gas to at least partially only CH ₂ F _2, the ratio of the CH ₂ F ₂ occupied in the etching gas is 20% or more, in addition to the CH ₂ F _2, at least the composition of carbon When containing gas to parts in the etching gas, gas and the ratio of the CH ₂ F ₂ to at least part of the composition of the carbon occupying in the etching gas is 20% or more and in the etching gas Occupy the CH ₂
It is characterized in that the proportion of F ₂ is at least 5%.

According to the first to third dry etching methods and the method for manufacturing a semiconductor device, for example, CH ₂ F ₂ is used as an etching gas for RIE. As a result, etching is performed only on the region to be etched, and the reaction product by RIE is deposited on the mask that is not to be etched without being etched. Therefore, a sufficiently large or substantially infinite etching selectivity can be obtained even when the aspect ratio is extremely large or the thickness of the mask material is extremely small.

In order to obtain the above effects, a mixed gas with another gas may be used, but in that case, the proportion of CH ₂ F _{2 in} the mixed gas must be 20% or more. . Further, when a gas containing C is added to the mixed gas, the C is deposited as a reaction product, so that the ratio of the gas containing CH ₂ F ₂ and the gas containing C in the mixed gas is reduced.
It must be at least 20% and the proportion of CH ₂ F _{2 to} the whole should be at least 5%. By performing RIE under these conditions, dry etching with a substantially infinite selection ratio can be performed. As a result, the consumption of the mask material in the manufacturing process of the semiconductor device can be reduced, and the accuracy of the etching process can be improved, so that the manufacturing yield and performance of the semiconductor device can be improved.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. For this explanation,
Common parts are denoted by common reference symbols.

FIG. 1 illustrates a dry etching method according to the first embodiment of the present invention.
FIG. 2 is a cross-sectional configuration diagram of a dry etching apparatus, particularly a magnetron RIE apparatus.

As shown, the magnetron RIE device 10
Has a vacuum chamber 11 as an etching chamber, in which a mounting table 13 (high-frequency electrode) for mounting an object to be processed 12 such as a semiconductor wafer, and a vacuum chamber 11 provided opposite to the mounting table 13. And a ground electrode 14 which is grounded. Further, outside the vacuum chamber 11, a high frequency power supply 16 for applying high frequency power to the mounting table 13 via the blocking capacitor 15; a gas introduction pipe 17 for introducing an etching gas into the vacuum chamber 11; The vacuum chamber 11 includes a gas discharge pipe 18 for discharging gas, and a magnet 19 that is provided to surround the vacuum chamber 11 and forms a magnetic field in the vacuum chamber 11. The magnet 19 is, for example, an electromagnet coil.

Next, the magnetron RI constructed as described above
FIG. 2A shows an etching method using the E apparatus 10.
This will be described with reference to FIG. FIGS. 2A and 2B are cross-sectional views of a semiconductor device showing a state in which a contact hole is formed in an interlayer insulating film. FIG. It shows the situation.

First, an SiO ₂ film 30 as an interlayer insulating film is formed on the surface of a semiconductor wafer, and a resist 31 is formed on the SiO ₂ film 30.
Is applied, exposed and developed to pattern the resist 31 into a desired pattern. Then, the semiconductor wafer is placed on the mounting table 13 in the etching chamber 11 as the processing object 12.

Thereafter, after the inside of the vacuum chamber 11 is evacuated by a vacuum pump (not shown), an etching gas is introduced into the vacuum chamber 11 through a gas introduction pipe 17. Then, high frequency power is applied to the mounting table 13 by the high frequency power supply 16. When high-frequency power is applied, high-density plasma is generated in the vacuum chamber 11 under the influence of the magnet 19, and ions and electrons are generated. They are affected by the high-frequency power, and when the high-frequency power is positive, the electrons go to the high-frequency electrode 13 and the blocking capacitor 15 is negatively charged. Conversely, when the high-frequency power is negative, the electrons go to the ground electrode 14, and the electrons disappear due to the ground. At this time, the ions also act together with the electrons, but the ions move slower than the electrons, and the ions cannot collide with the high-frequency electrode and the ground electrode. Therefore, the inside of the plasma is settled in a positively charged state due to a shortage of electrons. As a result, an electric field is generated between the high-frequency electrode 13 (blocking capacitor 15) and the plasma. Therefore, ions having a positive charge collide with the high-frequency electrode 13 negatively charged by electrons with anisotropy. The workpiece 12 is etched by the collision of the ions.

[0024] The etching gas during the etching, the CF _4, C ₂ F ₆ or the like F-based or CHF _3, CHF _3, which first widely used as an etching gas for SiO ₂ were mixed H ₂ H-
Use F type gas. Then, the SiO ₂ film 30 is etched using the resist 31 as a mask by the RIE method using the above gas as an etching gas. By this etching,
As shown in FIG. 2A, a contact hole having an aspect ratio of about 0.5 is formed. With such an aspect ratio, there is no problem in thinning the resist.

Next, the etching gas is switched to CH ₂ F ₂ to perform etching by the RIE method. Then, as shown in FIG. 2B, etching proceeds at the bottom of the contact hole formed first, but a reaction product 32 by RIE is deposited above the resist 31, and a phenomenon that etching does not proceed occurs. Thus, the contact hole can be formed without breaking the mask property of the resist 31.

Next, a dry etching method according to a second embodiment of the present invention will be described with reference to FIGS. FIGS. 3A and 3B show a case where a contact hole is formed by performing dry etching using the dry etching apparatus shown in FIG. 1 as in the first embodiment. FIG. FIG. 2B is a cross-sectional view of the semiconductor device after the formation of the contact hole during the formation.

As shown in FIG. 3A, first, an RIE method using an F-based gas such as CF ₄ or C ₂ F ₆ or an HF-based gas in which H ₂ is mixed with CHF ₃ or CHF ₃ is used as an etching gas. The SiO ₂ film 30 is etched. After forming a contact hole having an aspect ratio of about 0.5 by this etching, the resist is entirely removed.

After that, the etching gas is switched to CH ₂ F ₂ to perform etching by the RIE method. Then, as shown in FIG. 3B, the etching proceeds at the bottom of the contact hole, but the reaction product 32 by RIE is deposited on the surface of the SiO ₂ film 30, and the etching does not proceed. That is, although the surface and the bottom of the contact hole are made of the same material, the etching proceeds at the bottom of the contact hole with a selectivity relative to the surface.

Next, a dry etching method according to a third embodiment of the present invention will be described with reference to FIGS. FIGS. 4A and 4B show a case where a contact hole having a step inside is formed by performing dry etching using the dry etching apparatus shown in FIG. 1 similarly to the first embodiment. FIG. 3A is a cross-sectional view of the semiconductor device during the formation of the contact hole, and FIG. 3B is a cross-sectional view of the semiconductor device after the formation of the contact hole.

As shown in FIG. 4A, a gate electrode 41 is provided on a semiconductor substrate 40, a SiN film 42 is provided on the gate electrode 41 and the semiconductor substrate 40, and a SiO ₂ film is provided on the SiN film 42.
It is assumed that the film 43 is provided. In order to form a contact hole reaching the semiconductor substrate 40 between the adjacent gate electrodes 41, first, the SiO ₂ film 43 between the adjacent gate electrodes 41 is removed by etching. At this time, the SiN film 42 functions as an etching stopper.

In the next step, the SiN film 42 between the gate electrodes 41 is removed. At this time, etching is performed by the RIE method using CH ₂ F ₂ as an etching gas. Then, as shown in FIG. 4B, only the SiN film 42 between the gate electrodes 41 is etched,
_On the surface of the iO ₂ film 43 and on the SiN film 42 on the gate electrode 41, a reaction product 44 by RIE is deposited, and etching does not proceed.

As described in the dry etching method according to the first to third embodiments, CH gas is used as the etching gas.
When etching is performed by RIE using ₂ F _2, etching proceeds only in a region located at the bottom of the step, the progress of the etching is prevented by the reaction product is deposited in other areas.

This phenomenon is caused by gas reaction during RIE. C conventionally used as an etching gas
F type gas such as F ₄ , C ₂ F _{6 and the} like, and HF type gas obtained by mixing CHF ₃ and CHF ₃ with H ₂ are brought into a plasma state in the vacuum chamber 11 by magnetron discharge generated by high frequency power. Ions and radicals are generated in the plasma. The contribution of the ions to the lifetime and etching is CF ₃ ⁺ > CF ₂ ⁺ > CF ⁺ > C. On the other hand, the contribution ratio of radicals to etching is CF ₃ ^* >
CF ₂ ^* > CF ^* > C, and the lower the etching contribution ratio, the easier it is to deposit as a reaction product.

In the conventional F system such as CF ₄ and C ₂ F ₆ , the gas is hardly decomposed in the plasma, and mainly has a high contribution to etching.
Active species such as CF ₄ ⁺ and CF ₃ ⁺ , CF ₄ ^* and CF ₃ ^* are generated, and CF (Fluoro-Carbon) and C (Carbo) have low contribution to etching.
Unsaturated species such as n) are not easily generated. This is HF such as CHF ₃
Similarly, in the system, since unsaturated species are hardly generated, reaction products such as CF and C are hardly deposited.

On the other hand, when CH ₂ F ₂ is used, relatively unsaturated species are easily generated. This unsaturated species becomes a precursor and deposits as a reaction product, and functions to suppress etching. At the same time, active species that function as etchants are also generated. Since CF ⁺ and C, which are unsaturated species, have a short life, they collide with the surface of the object to be etched and are deposited as reaction products. On the other hand, active species CF ₃ ⁺ and CF ₂ ⁺ have a long life, and can reach deep portions of the object to be etched. Therefore, only the bottom of the trench or the contact hole is etched. Of course, active species contributing to etching are also present on the surface of the object to be etched, but the overwhelming number of unsaturated species are present on the surface. Beats. As a result, a reaction product due to unsaturated species is deposited on the surface and etching does not proceed, and etching with active species is performed only at the bottom of the trench. Of course, it is possible to control the generation ratio of the active species and the unsaturated species with high accuracy by the etching conditions.

FIG. 5 is a graph showing the etching rates on the bottom surface of the contact hole and the surface of the SiO ₂ film when the contact hole is formed in the SiO ₂ film by the RIE method using each etching gas. In the figure, square marks indicate the etching rate at the center of the semiconductor wafer, triangle marks indicate the etching rate at a position 30 mm from the edge of the semiconductor wafer, and circles indicate the etching rate at a position 5 mm from the edge. The etching conditions when using each gas are all the same.

As shown in the figure, CF ₄ , C
In the case of using HF ₃ and C ₄ F ₈ , it can be seen that although the etching rate is different, the etching proceeds at both the bottom of the contact hole and the surface of the SiO ₂ film. CH ₂ F ₂
Is used, the etching rate in the contact hole is slightly reduced, and the etching rate on the surface of the SiO ₂ film is approximately minus 100 ° / min. In other words, the etching does not proceed on the surface of the SiO ₂ film, but the deposition proceeds in reverse. At this point, it can be said that the etching selectivity is substantially infinite.

As the RIE apparatus, a magnetron RIE apparatus has been described as an example, but of course, an ECR (Electron Cyclotron Resonance) etching apparatus that generates high-density plasma by a magnetic field and a microwave using electron cyclotron resonance, , A helicon wave etching device that generates high-density plasma by the interaction of helicon waves and electrons, and an inductively coupled plasma etching device that accelerates electrons by an induction electric field generated by a high-frequency induction magnetic field and thereby generates plasma. good.

Next, a first embodiment of a method of manufacturing a semiconductor device using this dry etching method will be described with reference to a DRAM.
(Dynamic Random Access Memory) A method for manufacturing a trench capacitor will be described as an example with reference to FIGS. 6 to 12 are sectional views sequentially showing the steps of manufacturing the trench capacitor.

First, as shown in FIG. 6, SiO _{2 is formed} on a semiconductor substrate 50 such as a silicon substrate by a hydrogen combustion oxidation method.
A film 51 is formed, and a SiN film 52 and a SiO ₂ film 53 are formed on the SiO ₂ film 51.
Is formed by a CVD (Chemical Vapor Deposition) method.

Next, as shown in FIG. 7, an anti-reflective coating (ARC) 54 is formed on the SiO ₂ film 53 using an organic material. And resist 55 on this ARC54
Is applied, and the resist 55 is patterned by PEP (Photo Engraving Process) so as to have an opening in an area where a capacitor is to be formed.

Next, as shown in FIG. 8, the ARC 54 and the SiO ₂ film 53 at the portions where the trench capacitors are to be formed are removed by RIE using the resist 55 as a mask. At this time, the etching gas RIE were mixed with H ₂ in F-based or CHF _3, CHF ₃ normal CF _4, etc. C ₂ F ₆ which is used to etch the SiO ₂ H-
Use F type gas. The reason that the SiN film 52 is not removed all at once is that the resist 55 has become thinner due to the progress in miniaturization of the semiconductor device due to the higher storage capacity of the DRAM.
This is because if the O ₂ film 53 and the SiN film 52 are simultaneously etched, the mask properties of the resist 55 may be broken during the etching.

Thereafter, as shown in FIG.
4 Ashed by ashing and removed.
To prevent the peeling of 55 and ARC54,
Perform ching. As an etchant for wet etching
For example, H_TwoSO_Four, H_TwoO_TwoAnd H _TwoA mixture of O is used.

Then, as shown in FIG. 10, using the SiO ₂ film 53 as a mask, the SiN film 52 and the SiO ₂ film 51 are etched and removed by the RIE method using the magnetron RIE apparatus shown in FIG.

[0045] In this step, F system has been conventionally used for etching the SiO ₂ by the RIE method or CHF _3, the CHF ₃ H
₂ instead of the mixed gas or SiN to and CF ₄ are conventionally used to etch CHF _3, ArO ₂ such gases, for example, a CH ₂ F ₂ as the etching gas. However, the etching conditions are the same as before, and the gas flow rate is 10 to
100sccm, gas pressure is 10 ~ 100mTorr, high frequency power is 400 ~
2000 W and the substrate temperature are set in the range of about -30 to 60 ° C., respectively. By performing RIE using CH ₂ F ₂ as an etching gas, the SiO ₂ film 53 serving as a mask is not removed at all, and the exposed SiN film 52 and the exposed SiO ₂ film 51 are sequentially etched. Conversely, a reaction product 56 generated during RIE is deposited on the SiO ₂ film 53. The reaction product 56 is, for example, C or CF. That is, when RIE is performed using CH ₂ F ₂ as an etching gas, a reaction product is deposited on the mask, and a phenomenon occurs in which only the opening of the mask, that is, the region to be etched, is etched. Is substantially infinite.

Subsequently, as shown in FIG. 11, the reaction product 56 deposited on the SiO ₂ film 53 is removed by ashing and wet etching.

Next, as shown in FIG. 12, the semiconductor substrate 50 is etched by RIE using the SiO ₂ film 53 as a mask to form a trench 57 for a cell capacitor.

CH ₂ F ₂ may be used as an etching gas when the semiconductor substrate 50 is etched by RIE to form a trench. However, from the viewpoint of an etching rate and controllability, a conventional Si etching gas is used. C used for
Some of F of F ₄ , SF ₆ and CF ₄ are Cl (Chlorine) or Br (B
It is desirable to use the gas replaced by romine).

Thereafter, the SiO _{2 is formed} by wet etching or the like.
The film 53 is removed. Then, as is well known, an insulating film containing impurities is formed inside the trench 57, and the impurities contained in the insulating film are solid-phase diffused into the semiconductor substrate 50 by performing a heat treatment. Then, an impurity diffusion layer serving as a plate electrode is formed. Subsequently, after removing the insulating film, a capacitor insulating film is formed on the inner peripheral surface of the trench 50. As the material of the capacitor insulating film, for example, an SiO ₂ film, an ONO film (three-layer structure of SiO ₂ film, SiN film and SiO ₂ film), and an ON film (two-layer structure of SiO ₂ film and SiN film) are used. Then, the trench 57 is filled with, for example, a polycrystalline silicon film or the like serving as a storage node electrode to complete a cell capacitor.

Normally, the aspect ratio of a trench for a cell capacitor is very large, and in a DRAM having a storage capacity of 256 Mbit class, the aspect ratio is about 20. It is expected that 1Gbit class DRAM will exceed 20 from the viewpoint of securing the capacity of the cell capacitor.

In order to form a trench having such a high aspect ratio, the consumption of the mask material during the etching is considerably large, and the etching of the mask material due to the breakdown of the resist when patterning the mask material itself is taken into consideration. It is necessary to increase the thickness of the mask material.

However, according to the method of manufacturing a semiconductor device described in this embodiment, when forming a mask material, etching is performed by RIE using CH ₂ F ₂ as an etching gas. Then, a phenomenon occurs in which the etching proceeds only in the region to be etched, and the surface of the mask material is not etched. As a result, the thickness of the mask material can be reduced to the minimum required for forming the trench of the cell capacitor.

When CH ₂ F ₂ is also used for RIE for forming a trench of a cell capacitor, the etching rate is reduced, but a thick mask material is not required and there is no fear of the mask material being broken. Cell capacitor having a high density can be formed.

After forming the above-mentioned trench type cell capacitor, an element isolation region is formed in the memory cell array region and the peripheral circuit region of the semiconductor substrate 50 by STI (Shallow Trench Isch).
olation) technology. STI technology is a technology that forms a shallow trench in a semiconductor substrate and forms an element isolation region by filling the trench with an insulator.
The trench used for this element isolation region can also be formed in exactly the same procedure as when forming the trench 57 of the cell capacitor described above.

Next, a method of manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to SAC (Self Align Control).
t) An example of a method of manufacturing a DRAM contact plug using technology will be described with reference to FIGS.

First, as shown in FIG. 13, a Si substrate is formed on a semiconductor substrate 60 on which a cell capacitor and an element isolation region are formed.
A gate insulating film 61 of an O ₂ film is formed by a dry oxygen oxidation method or the like. A polycrystalline silicon film 62 is formed on the gate insulating film 61.
It is formed by a CVD method or the like, and a CVD
The SiO ₂ film 63 is formed by a method or an oxidation method. And SiO ₂
A W (Tungsten) film is formed on the film 63, and silicidation by heat treatment is performed to form a WSi film 64. The SiO ₂ film 63 has a very small thickness, and is formed in order to prevent W from coming out of the WSi film 64. Furthermore, a SiN film is formed on the WSi film 64.
65 are formed. Then, the polycrystalline silicon film 62, Si
A gate electrode is formed by patterning the O ₂ film 63, the WSi film 64, and the SiN film 65 into a desired pattern by lithography and etching. Next, an impurity is introduced into the semiconductor substrate 60 by an ion implantation technique to form an impurity diffusion layer 66 to be a source / drain region. The source electrode of the cell transistor formed in the memory cell region is formed so as to be connected to the storage node electrode of the cell capacitor described above. At this time, impurities are simultaneously introduced into the gate electrode. Subsequently, the impurities introduced by the heat treatment are activated to form the DRAM cell transistor and the MOS transistor in the peripheral circuit region.

Thereafter, an SiN film 67 and a BPSG (Boron P
(Hosphorous Silicate Glass)
It is formed by the VD method or the like, and the CMP (Chemical Mechanical Polishin
g) Flatten by a method or the like.

Then, in order to form a contact hole for making contact with the impurity diffusion layer 66,
ARC69 is formed, and a resist 70 is applied on ARC69. This resist 70 is patterned into a contact hole formation pattern by PEP.

Next, as shown in FIG. 14, using the patterned resist 70 as a mask, the ARC 69 and the interlayer insulating film 68 are etched by RIE to form a contact hole 71 reaching the SiN film 67. The etching gas used for RIE may be a commonly used F-based gas such as CF ₄ , C ₂ F ₆ , CHF ₃ , CHF ₃
It is a HF-based gas mixed with H ₂ in. In this step, the SiN
High-selectivity etching is performed by the SAC technique using the film 67 as a stopper.

Then, as shown in FIG. 15, the resist 70 and the ARC6 are etched by ashing and wet etching for removing organic substances.
Remove 9 and.

Next, in order to make contact with the impurity diffusion layer 66, the bottom of the contact hole 71 is formed between the gate electrodes.
The SiN film 67 and the gate insulating film 61 are etched by RIE. At this time, for example, CH ₂ F ₂ , CF
₄ and a mixed gas of Ar is used. And their mixing ratio is 10 sccm, 30 sccm, 160 sccm respectively, and chamber 2
The pressure in 1 is 50 mTorr, and the high frequency power is 300 W. By using the above mixed gas, as shown in FIG. 16, only the SiN film 67 and the gate insulating film 61 at the bottom of the contact hole 71 are etched, and the SiN film on the interlayer insulating film 68 and the gate electrode in the contact hole 71 is etched. A reaction product 72 is deposited on 67. Therefore, the contact hole 71 reaching the impurity diffusion layer 66 can be formed only by performing etching by changing the etching gas by the normal RIE method.

Then, as shown in FIG. 17, the deposited reaction product 72 is removed by ashing and wet etching.

After that, as shown in FIG. 18, the contact hole 71 is filled with, for example, polycrystalline silicon or the like.
The contact plug 73 is formed by planarization by CMP. The contact plug 73 is made of, for example, Ti (Titaniu
m) It may be formed by a multilayer structure of a film and a W film.

According to the above-described manufacturing method, the etching of the SiN film 67 and the gate insulating film 61 between the adjacent gate electrodes is performed by using a mixed gas containing CH ₂ F ₂ as an etching gas.
It is done by IE method. By using the above etching gas, only the SiN film 67 and the gate insulating film 61 between the gate electrodes are selectively etched. Therefore, it is not necessary to mask a region other than between the gate electrodes with a mask material, so that the manufacturing process of the DRAM can be simplified, the manufacturing cost can be reduced, and the yield can be improved.

In this embodiment, the side surface of the SiN film 67 is made more vertical and the bottom of the contact hole 71 is
In order to uniformly etch the SiN film 67, a gas containing CF (CF ₄ ) and an Ar (Argon) for a dilution effect are mixed with CH ₂ F ₂
And used as an etching gas. Of course, CH ₂ F
A single gas of _two gases may be used.

Next, a method of manufacturing a semiconductor device according to the third embodiment of the present invention will be described with reference to FIGS. 19 to 23, taking a method of manufacturing a DRAM contact plug as an example. 19 to 23 are sectional views sequentially showing the steps of manufacturing the contact plug.

First, as shown in FIG. 19, a MOS transistor is formed in the peripheral circuit region by the manufacturing process described in the second embodiment. Then, an interlayer insulating film 68 covering the MOS transistor is formed by a BPSG film, and further, TEOS (Tetraethylorthosilicate; Si (OC
An SiO ₂ film 74 is formed by a CVD method using ₂ H ₅ ) ₄ )). Then, an impurity diffusion layer between adjacent gate electrodes
A contact hole reaching 66 is formed, and the contact hole is buried with a metal or the like to form a contact plug 73. The level at which the SiO ₂ film 74 is provided is a level at which a bit line is formed in the memory cell region, and the contact plug 73 in the peripheral circuit region may be formed using a wiring layer of the bit line. Further, an interlayer insulating film 75 is formed on the SiO ₂ film 74 and the contact plug 73.

Subsequently, an ARC 76 is formed on the interlayer insulating film 75 in order to form a contact hole for making contact with the contact plug 73 in the interlayer insulating film 75 in the peripheral circuit region.
Then, a resist 77 is formed. And this resist 77
An opening is provided at a position corresponding to the contact plug 73 by patterning using PEP.

Next, as shown in FIG. 20, the interlayer insulating film 75 is etched by the RIE method using the resist 77 as a mask. At this time, an RIE etching gas such as CF-based and CH-F6 such as CF ₄ and C ₂ F _{6 which} are generally used for etching SiO ₂ is used.
An HF-based gas in which H ₂ is mixed with F ₃ and CHF ₃ is used.

However, since the interlayer insulating film at this level has a large thickness, if an attempt is made to open a contact hole by the RIE method using a normal gas, the resist 77 and the ARC 76 are etched during the RIE as shown in FIG. And the mask may break down.

Therefore, when the mask is broken or is about to be broken, the etching gas is switched to CH ₂ F ₂ to perform etching. By using the above gas, as shown in FIG. 21, only the interlayer insulating film 75 is etched,
Reaction products 79 such as C and CF are deposited on the resist 77.
Of course, in the etching by RIE for forming the contact hole 78, CH ₂ F ₂ may be used as an etching gas all the time, but from the viewpoint of the etching rate, conventionally used F-based or CHF ₃ , to CHF ₃ to perform the RIE in two steps between the gas and the CH ₂ F ₂ in HF based mixed with H ₂ be the most efficient.

Then, as shown in FIG. 22, the reaction products 79 deposited on the resist 55, the ARC 76, and the resist 77 are removed by ashing and wet etching.

Subsequently, the entire surface is formed by sputtering or the like.
A TiN film and a W film are formed, the contact holes 78 formed in the previous process are buried, and planarization is performed by CMP to form a contact plug 80 as shown in FIG.

According to the above manufacturing method, CH ₂ F ₂ is used as an RIE etching gas for forming a contact hole in the interlayer insulating film 75. By using this gas as an etching gas, etching proceeds only in the region to be etched, and the surface of the mask material is not etched. Therefore, the thickness of the mask material can be reduced to the minimum necessary.

FIGS. 24 and 25 are cross-sectional views for explaining a modification of the present embodiment, and sequentially show the steps of manufacturing a DRAM contact plug.

That is, as shown in FIG. 24, when forming a contact hole in the interlayer insulating film 75 by RIE, first, CH ₂ F ₂ is used as an etching gas. in this case,
The resist 77 is formed at the same time when the contact hole 78 is formed.
Reaction products 79 are deposited on the top.

Then, as shown in FIG. 25, the reaction product 79
Is deposited to a certain thickness, the etching gas is switched to a conventional F-based gas, CHF ₃ , or an HF-based gas in which H ₂ is mixed with CHF ₃ . Then, a contact hole 78 is finally formed using the reaction product 79 as a mask.

According to such a manufacturing method, the same effect as in the above embodiment can be obtained.

According to the dry etching method and the semiconductor device manufacturing method described in the first to third embodiments, CH ₂ F ₂ is used as an etching gas in the etching by the RIE method when forming a trench or a contact hole. Used. By using this gas, etching is performed only on the region to be etched, and the reaction product of RIE is deposited on the mask that is not to be etched without being etched. Therefore, a sufficiently large or substantially infinite etching selectivity can be obtained even when the aspect ratio is extremely large or the thickness of the mask material is extremely small.

Further, as described in the above embodiment, the etching gas introduced at the time of etching is not limited to a single gas of CH ₂ F ₂ alone, but may be a mixed gas with another gas. As a gas added to CH ₂ F ₂ , for example, CO is preferable.
Of the elements contained in these gases, C (Carbon), of course, acts in the direction of depositing as a reaction product. Conversely, O (Oxyge
In the case of n), since C as an unsaturated species is removed by oxidization, it works in the direction of promoting the etching. Therefore, the effect of CH ₂ F ₂ can be further enhanced by adding CO. In addition to CO, for example, CF ₄ and C ₄ F ₈
If a mixed gas with a gas containing C is used, the effect of accelerating the deposition of the reaction product can be naturally obtained. In addition, a gas such as O ₂ or N ₂ (Nitrogen) may be added. However, since these gases react with the reaction products and contribute to the direction of removing the reaction products, it is not preferable to add a large amount of these gases. Further, Ar or He (Helium) may be added for the purpose of obtaining a dilution effect of the entire gas.

As described above, as the etching gas, not only a single gas of CH ₂ F ₂ but also a mixed gas with other gas may be used, but the ratio of CH ₂ F _{2 in} the mixed gas may be used. Is 2
Must be at least 0%. In the mixed gas,
When a gas containing C is added, the C is deposited as a reaction product, so that CH ₂ F ₂ and C
The proportion of the gas containing gas must be 20% or more and the proportion of the gas to CH ₂ F _{2 as} a whole must be 5% or more.

First, the condition that the proportion of the gas containing CH ₂ F ₂ and C is 20% or more will be described with reference to FIGS. 26 (a) to 26 (c). FIGS. 26 (a) to 26 (c)
FIG. 3 is a cross-sectional view of a semiconductor device when RIE is performed using a mixed gas of CH ₂ F ₂ / CF ₄ / Ar as an etching gas. The pressure in the chamber was set to 40 mTorr, and the high frequency power was set to 1000 W.

First, the case where the gas flow rates of CH ₂ F ₂ and CF ₄ are fixed at 10 sccm and 30 sccm, respectively, and the gas flow rate of Ar is changed will be described.

FIG. 26A shows a case where the Ar gas flow rate is set to 50 sccm. Under these gas flow conditions, the total gas flow is 90 sccm, and the ratio of CH ₂ F ₂ and CF ₄ is
44%. In this case, a reaction product is deposited on the surface at the same time as the etching of the bottom of the contact hole progresses, so that etching with a substantially infinite selectivity becomes possible.

FIG. 26B shows the case where the Ar gas flow rate is 150 sccm. In this case, the ratio of CH ₂ F ₂ and CF ₄ to the whole is 21%, and although the amount of the reaction product is smaller than the condition of FIG. It is.

FIG. 26C shows the case where the Ar gas flow rate is 250 sccm. Under these conditions, the ratio of CH ₂ F ₂ and CF ₄ to the whole is only 14%. As a result, it can be seen that the etching progresses not only at the bottom of the contact hole but also at the surface of the semiconductor device, making it impossible to perform selective etching.

Next, the gas flow rates of CF ₄ and Ar were set to 30 seconds, respectively.
The case where the gas flow rate of CH ₂ F ₂ is changed while fixing to ccm and 160 sccm will be described.

When the gas flow rate of CH ₂ F ₂ is set to 20 sccm,
H ₂ F ₂ and CF ₄ account for 24% of the total, and FIG.
The result shown in (a) is obtained. That is, etching having an infinite selection ratio is possible.

When the gas flow rate of CH ₂ F ₂ is reduced to 10 sccm, the ratio of CH ₂ F ₂ and CF ₄ to the whole becomes 20%, and the result shown in FIG. 26B is obtained. Even under these conditions, etching with an infinite selection ratio is possible.

When the gas flow rate of CH ₂ F ₂ is further reduced and set to 5 sccm, the ratio of CH ₂ F ₂ and CF ₄ to the whole becomes 18%, and as shown in FIG. Etching is not possible.

Next, the gas flow rates of CH ₂ F ₂ and Ar were set to 1 respectively.
A case where the gas flow rate of CF ₄ is changed while fixing to 0 sccm and 160 sccm will be described.

As shown in FIG. 26A, CF_FourGas flow
If the amount is set to 50sccm, CH_TwoF_TwoAnd CF _FourAnd occupy the whole
The ratio is 27%, etching with infinite selectivity
Is possible.

As shown in FIG. 26B, when the gas flow rate of CF ₄ is reduced to 30 sccm, the ratio of CH ₂ F ₂ and CF ₄ to the whole becomes 20%. Is possible.

As shown in FIG. 26 (c), when the gas flow rate of CF ₄ is further reduced and set to 10 sccm, the ratio of CH ₂ F ₂ and CF ₄ to the whole becomes 11%, and selective etching becomes impossible. It is impossible.

As described above, when a gas containing C as a part of the composition is added to the etching gas,
And the ratio of CH ₂ F ₂ is ₂ % of the total etching gas.
It must be 0% or more. FIG. 27 is a graph of this state. FIG. 27 shows a gas containing C and CH ₂ F _2.
It shows the deposition rate of the reaction product with respect to the ratio of the gas to the total. As shown, gas containing C and C
It can be seen that the reaction products start to be deposited from the vicinity where the ratio of the H ₂ F ₂ gas to the whole exceeds 20%, and the deposition rate of the reaction products increases as the ratio increases. Of course, the deposition rate of the reaction product depends on the applied power of the high-frequency power and the pressure in the chamber. However, the two values have a relationship roughly as shown in the graph of FIG.

When a gas containing C is added to the etching gas, the ratio of CH ₂ F ₂ is 5% of the total etching gas.
Must account for at least%. In this regard, FIG.
This will be described with reference to (a) to (c). FIGS. 28A to 28C are cross-sectional views of a semiconductor device when RIE is performed using a mixed gas composed of CH ₂ F ₂ / CF _4, and the gas flow rate of CF ₄ is kept constant at 100 sccm. Shows the case where the gas flow rate of CH ₂ F ₂ is changed. The pressure in the chamber was set to 40 mTorr, and the high frequency power was set to 500 W.

FIG. 28 (a) shows a gas flow rate of CH ₂ F ₂ of 10 sccm.
The case where it is set to is shown. Under these gas flow conditions, the total gas flow is 110 sccm, in which CH ₂ F ₂
Accounts for 9%. In this case, a reaction product is deposited on the surface at the same time as the etching of the bottom of the contact hole progresses, so that etching with a substantially infinite selectivity becomes possible.

FIG. 28 (b) shows a case where the gas flow rate of CH ₂ F ₂ is set to 5 sccm, and the ratio occupied by CH ₂ F ₂ is 5%. In this case, although the deposition amount of the reaction product is greatly reduced, etching with a substantially infinite selectivity is still possible.

FIG. 28C shows the case where the gas flow rate of CH ₂ F ₂ is set to 3 sccm, and the ratio of CH ₂ F ₂ is 3%. Under this condition, etching proceeds not only at the bottom of the contact hole but also at the surface of the semiconductor device, making selective etching impossible.

As described above, the reaction product depends on the gas composition.
Can control the deposition rate and etching rate of the material,
Of course, the applied high frequency power and
Radicals and ions generated in the plasma
Adjust the reaction product deposition rate and etching rate
Can also be controlled. In this regard, FIG.
This will be described with reference to (a) to (c). FIG. 29 (a) through
(C) is CH_TwoF _Two/ CF_FourUsing a mixed gas consisting of
FIG. 2 shows a cross-sectional view of a semiconductor device when RIE is performed.
You. Note that CH_TwoF_TwoAnd CF_FourThe gas flow rates of each were 40 sccm,
It is set to 50sccm.

FIG. 29A shows a case where the high frequency power is set to 500 W or the pressure in the chamber is set to 80 mTorr. Under these conditions, a reaction product is deposited on the surface at the same time as the etching of the bottom of the contact hole proceeds, and etching with a substantially infinite selectivity becomes possible.

FIG. 29B shows a case where the high frequency power is set to 1000 W or the pressure in the chamber is set to 40 mTorr. In this case, although the amount of the reaction product is smaller than the condition of FIG. 29A, etching with an infinite selection ratio is still possible.

FIG. 29C shows the case where the high frequency power is set to 1500 W or the pressure in the chamber is set to 20 mTorr. Under these conditions, it can be seen that the etching proceeds not only at the bottom of the contact hole but also at the surface of the semiconductor device, making selective etching impossible.

FIG. 30 is a graph of the above results. As shown in the figure, it can be seen that the deposition rate of the reaction product is inversely proportional to the high frequency power and changes in proportion to the pressure in the chamber. If the high-frequency power is increased, the ion energy is also increased, so that the reaction product has an ion assist effect or the like. This reduces the deposition rate of reaction products. Conversely, if the pressure in the chamber is set high, the ion energy decreases, and the deposition rate of the reaction product increases.

As described above, according to the present invention, CH ₂ F ₂
By performing RIE using at least a part of the etching gas, etching having a substantially infinite selectivity can be performed. However, the condition is that the entire etching gas contains 20% or more of CH ₂ F ₂ , and when a gas containing C is added, the mixed gas of the gas and CH ₂ F ₂ is 20%. It is necessary that the content of CH ₂ F ₂ be at least 5%.

Further, in the above embodiment, the description has been given by taking CH ₂ F ₂ as an example of the etching gas, but the composition of the etching gas satisfies the condition of x / y ≧ 0.6 in CnHxFy (n is an arbitrary integer). If so, almost the same tendency can be obtained. That is, the same effect can be obtained by using a gas such as CH ₃ F or C ₃ H ₅ F ₃ . However, as the composition ratio of H (Hydrogen) increases, the deposition rate of reaction products tends to increase and the etching rate tends to decrease. Therefore, it is necessary to perform etching by selecting an appropriate gas depending on the situation. Also, if the amount of reaction products deposited is too large, RI
The inside of the vacuum chamber of the E apparatus may be contaminated. Therefore, it is more preferable to set the etching rate and the deposition rate of the reaction product to be the same in the region not to be etched, so that the reaction product is not deposited and the etching does not proceed. However, it is not necessary to make the etching rate and the deposition rate of the reaction product the same in the region that should not be etched, and the surface is etched thin by balancing the etching rate and the deposition rate of the reaction product as much as possible. Alternatively, the reaction product may be deposited thinly.

[0107] Materials to be etched include SiO ₂ and SiN.
However, the present invention is not limited to these materials, but can be applied to Si, organic, and inorganic SiO ₂ . Organic SiO ₂ is a material that is starting to attract attention as a material that can achieve a low dielectric constant film, and can be said to be a material suitable for forming an interlayer insulating film.

Further, the present invention is widely applicable not only to the DRAM described in the first to third embodiments, but also to other semiconductor devices.

The present invention is not limited to the above-described embodiment, and can be variously modified at the stage of implementation without departing from the scope of the invention. Further, the embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some components are deleted from all the components shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved and the effects described in the column of the effect of the invention can be solved. Is obtained, a configuration from which this configuration requirement is deleted can be extracted as an invention.

[0110]

As described above, according to the present invention, a dry etching method capable of obtaining a high selectivity can be provided.

Further, according to the present invention, it is possible to provide a method of manufacturing a semiconductor device capable of improving the manufacturing yield and the performance of the semiconductor device by using a dry etching method capable of obtaining a high selectivity.

[Brief description of the drawings]

FIG. 1 is a sectional configuration diagram of a magnetron RIE apparatus for performing a dry etching method according to an embodiment of the present invention.

FIGS. 2A and 2B show a dry etching method according to the first embodiment of the present invention, wherein FIG. 2A is a sectional view of the semiconductor device during the formation of a trench, and FIG.

FIGS. 3A and 3B show a dry etching method according to a second embodiment of the present invention, wherein FIG. 3A is a sectional view of a semiconductor device during formation of a trench, and FIG.

4A and 4B show a dry etching method according to a third embodiment of the present invention, in which FIG. 4A is a sectional view of a semiconductor device during the formation of a contact hole, and FIG.

FIG. 5 is a graph showing an etching rate by each gas in the dry etching method according to the first to third embodiments of the present invention.

FIG. 6 is a sectional view of a first manufacturing step of the trench capacitor of the DRAM according to the first embodiment of the present invention;

FIG. 7 is a sectional view of a second manufacturing step of the trench capacitor of the DRAM according to the first embodiment of the present invention;

FIG. 8 is a sectional view of a third manufacturing step of the trench capacitor of the DRAM according to the first embodiment of the present invention;

FIG. 9 is a sectional view of a fourth manufacturing step of the trench capacitor of the DRAM according to the first embodiment of the present invention;

FIG. 10 is a sectional view of a fifth step of manufacturing the trench capacitor of the DRAM according to the first embodiment of the present invention;

FIG. 11 is a sectional view of a sixth manufacturing step of the trench capacitor of the DRAM according to the first embodiment of the present invention;

FIG. 12 is a sectional view of a seventh step of manufacturing the trench capacitor of the DRAM according to the first embodiment of the present invention;

FIG. 13 is a sectional view of a first step of manufacturing a contact plug of the DRAM according to the second embodiment of the present invention;

FIG. 14 is a sectional view of a second step of manufacturing the contact plug of the DRAM according to the second embodiment of the present invention;

FIG. 15 is a sectional view of a third step of manufacturing the contact plug of the DRAM according to the second embodiment of the present invention;

FIG. 16 is a sectional view of a fourth manufacturing step of the contact plug of the DRAM according to the second embodiment of the present invention;

FIG. 17 is a sectional view of a fifth step of manufacturing the contact plug of the DRAM according to the second embodiment of the present invention;

FIG. 18 is a sectional view of a sixth manufacturing step of the contact plug of the DRAM according to the second embodiment of the present invention;

FIG. 19 is a sectional view of a first step of manufacturing a contact plug of the DRAM according to the third embodiment of the present invention;

FIG. 20 is a sectional view of a second manufacturing step of the contact plug of the DRAM according to the third embodiment of the present invention;

FIG. 21 is a sectional view showing a third manufacturing step of the contact plug of the DRAM according to the third embodiment of the present invention;

FIG. 22 is a sectional view of a fourth step of manufacturing the contact plug of the DRAM according to the third embodiment of the present invention;

FIG. 23 is a sectional view of a fifth step of manufacturing the contact plug of the DRAM according to the third embodiment of the present invention;

FIG. 24 is a diagram showing a DR according to a modification of the third embodiment of the present invention.
Sectional drawing of the 1st manufacturing process of the contact plug of AM.

FIG. 25 is a diagram showing a DR according to a modification of the third embodiment of the present invention.
Sectional drawing of the 2nd manufacturing process of the contact plug of AM.

FIG. 26 is a view for explaining the influence of the composition of the etching gas in the embodiment of the present invention.
FIGS. 7A to 7C are cross-sectional views of a semiconductor device obtained when dry etching is performed while the flow ratio of CH ₂ F ₂ is sequentially reduced.

FIG. 27 is a graph showing a change in a deposition rate of a reaction product with respect to a ratio of a mixed gas of a gas containing carbon and CH ₂ F ₂ in an etching gas.

FIG. 28 is a view for explaining the influence of the composition of the etching gas in the embodiment of the present invention.
FIGS. 7A to 7C are cross-sectional views of a semiconductor device obtained when dry etching is performed while the flow ratio of CH ₂ F ₂ is sequentially reduced.

FIG. 29 is a view for explaining the influence of the composition of the etching gas in the embodiment of the present invention.
FIGS. 3A to 3C are cross-sectional views of a semiconductor device obtained when dry etching is performed by sequentially increasing high-frequency power or sequentially reducing the pressure in a vacuum chamber.

FIG. 30 is a graph showing a change in a deposition rate of a reaction product with respect to a high-frequency power and a pressure in a vacuum chamber.

31A and 31B show a conventional dry etching method. FIG. 31A shows a state in which a contact hole is being formed, and FIG.
The figure is a cross-sectional view of the semiconductor device after formation.

[Explanation of symbols]

10 magnetron RIE equipment 11 vacuum chamber 12 workpiece 13 high-frequency electrode 14 ground electrode 15 blocking capacitor 16 high-frequency power supply 17 gas introduction pipe 18 gas exhaust pipe 19 magnet 30, 53, 63, 65 , 74, 100 ... SiO ₂ films 31, 55, 70, 77, 101 ... resists 32, 44, 56, 72, 79 ... reaction products 40, 50, 60 ... semiconductor substrates 41, 61 ... gate electrodes 42, 52, 67 ... SiN film 43,68,75 ... interlayer insulating film 51 ... gate insulating film 54,69,76 ... ARC 57 ... trench 62 ... polycrystalline silicon film 64 ... WSi film 71,78 ... contact hole 73,80 ... contact plug

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 5F004 AA04 AA05 BA04 BA13 BA14 BB07 BB13 BB14 CA02 DA01 DA02 DA15 DA16 DA24 DB01 DB03 DB07 EA02 EA10 EB01 5F032 AA35 AA66 CA17 DA23 5F083 AD15 JA35 JA39 MA02 MA06 MA15 NA03

Claims (11)

[Claims] 1. An etching method according to claim 1, wherein the etching area of the object to be etched is
Forming a recess with a pect ratio of at least 0.5; CH_TwoF_TwoUsing an etching gas containing
Performing a step of performing etching.
The etching gas contains at least carbon having a composition contained in the etching gas.
Part of the gas is CH_TwoF _TwoOnly if the etching gas
The occupied CH_TwoF_TwoIs more than 20%, CH_TwoF_TwoGas containing carbon as at least a part of the composition
Is contained in the etching gas,
Gas containing at least part of its composition in carbon
And the CH_TwoF_TwoIs more than 20% and etching gas
The occupied CH _TwoF_TwoIs characterized by being at least 5%
Dry etching method. 2. An etching mass on an object to be etched.
Forming a mask material; and forming a recess having an aspect ratio of at least 0.5 in the mask material.
Forming process and CH_TwoF_TwoUsing an etching gas containing
Performing a step of performing etching.
The etching gas contains at least carbon having a composition contained in the etching gas.
Part of the gas is CH_TwoF _TwoOnly if the etching gas
The occupied CH_TwoF_TwoIs more than 20%, CH_TwoF_TwoGas containing carbon as at least a part of the composition
Is contained in the etching gas,
Gas containing at least part of its composition in carbon
And the CH_TwoF_TwoIs more than 20% and etching gas
The occupied CH _TwoF_TwoIs characterized by being at least 5%
Dry etching method. 3. An etching mass on an object to be etched.
Forming a mask material, and the mask material and the object to be etched have an aspect ratio.
Forming a recess of at least 0.5; CH_TwoF_TwoUsing an etching gas containing
Performing a step of performing etching.
The etching gas contains at least carbon having a composition contained in the etching gas.
Part of the gas is CH_TwoF _TwoOnly if the etching gas
The occupied CH_TwoF_TwoIs more than 20%, CH_TwoF_TwoGas containing carbon as at least a part of the composition
Is contained in the etching gas,
Gas containing at least part of its composition in carbon
And the CH_TwoF_TwoIs more than 20% and etching gas
The occupied CH _TwoF_TwoIs characterized by being at least 5%
Dry etching method. 4. The object to be etched is organic SiO ₂ , inorganic
4. The dry etching method according to claim 1, wherein the material is at least one material selected from the group consisting of SiO ₂ , SiN, and Si. 5. The etching gas further contains a gas containing carbon and oxygen as at least a part of a composition, the carbon promotes a deposition rate of a reaction product generated at the time of etching, and the oxygen etches the gas. 5. The dry etching method according to claim 1, wherein the rate is increased. 6. A first mask material is formed on a semiconductor substrate.
Forming a second mask material on the first mask material; and patterning the second mask material to obtain an aspect ratio.
Forming a recess of at least 0.5; CH_TwoF_TwoCorresponds to the recess using an etching gas containing
Etching the first mask material in a region to be etched, and etching the semiconductor substrate in a region corresponding to the concave portion
Forming a trench by etching the first mask material.
The etching gas contains at least carbon which is contained in the etching gas.
Part of the gas is CH_TwoF _TwoOnly if the etching gas
The occupied CH_TwoF_TwoIs more than 20%, CH_TwoF_TwoGas containing carbon as at least a part of the composition
Is contained in the etching gas,
Gas containing at least part of its composition in carbon
And the CH_TwoF_TwoIs more than 20% and etching gas
The occupied CH _TwoF_TwoIs characterized by being at least 5%
Semiconductor device manufacturing method. 7. The semiconductor substrate is etched to form a trench.
In at least some of the steps of forming_TwoF_Two
Etching is performed using an etching gas containing: the etching gas contains:
Gas containing carbon as at least part of the composition is CH_TwoF_TwoOnly
In the case, the CH occupied in the etching gas_TwoF_Two20%
That's it, CH_TwoF_TwoGas containing carbon as at least a part of the composition
Is contained in the etching gas,
Gas containing at least part of its composition in carbon
And the CH_TwoF_TwoIs more than 20% and etching gas
The occupied CH _TwoF_TwoIs characterized by being at least 5%
The method of manufacturing a semiconductor device according to claim 6. 8. A gate insulating film is formed on a semiconductor substrate
Forming a gate electrode on the gate insulating film; forming an insulating film on the gate insulating film and the gate electrode
Forming an interlayer insulating film on the insulating film; and using the insulating film as a stopper to form the adjacent gate.
Forming a contact hole between the electrodes to reach the insulating film
Process and CH_TwoF_TwoThe gate electrode using an etching gas containing
Etching the insulating film between the gate electrodes, and etching the insulating film between the gate electrodes.
The etching gas used in the above, the carbon contained in the etching gas at least in the composition
Part of the gas is CH_TwoF _TwoOnly if the etching gas
The occupied CH_TwoF_TwoIs more than 20%, CH_TwoF_TwoGas containing carbon as at least a part of the composition
Is contained in the etching gas,
Gas containing at least part of its composition in carbon
And the CH_TwoF_TwoIs more than 20% and etching gas
The occupied CH _TwoF_TwoIs characterized by being at least 5%
Semiconductor device manufacturing method. 9. The insulating film between the gate electrodes is etched.
After the step of_TwoF_TwoUsing an etching gas containing
Etching the gate insulating film between the gate electrodes
Further comprising the step of: wherein the etching gas contains
Gas containing carbon as at least part of the composition is CH_TwoF_TwoOnly
In the case, the CH occupied in the etching gas_TwoF_Two20%
That's it, CH_TwoF_TwoGas containing carbon as at least a part of the composition
Is contained in the etching gas,
Gas containing at least part of its composition in carbon
And the CH_TwoF_TwoIs more than 20% and etching gas
The occupied CH _TwoF_TwoIs characterized by being at least 5%
The method for manufacturing a semiconductor device according to claim 8. 10. An interlayer insulating film is formed on a semiconductor substrate.
Forming a mask material on the interlayer insulating film; and patterning the mask material into a desired pattern.
Etching the interlayer insulating film using the mask material as a mask
Forming a contact hole by etching the interlayer insulating film.
In at least some of the steps of forming_TwoF_TwoIncluding d
Etching using a etching gas, the CH_TwoF_TwoEtching using an etching gas containing
The etching gas at the time of performing is at least carbon having a composition contained in the etching gas.
Part of the gas is CH_TwoF _TwoOnly if the etching gas
The occupied CH_TwoF_TwoIs more than 20%, CH_TwoF_TwoGas containing carbon as at least a part of the composition
Is contained in the etching gas,
Gas containing at least part of its composition in carbon
And the CH_TwoF_TwoIs more than 20% and etching gas
The occupied CH _TwoF_TwoIs characterized by being at least 5%
Semiconductor device manufacturing method. 11. The etching gas further contains a gas containing carbon and oxygen as at least a part of a composition, the carbon promotes a deposition rate of a reaction product generated at the time of etching, and the carbon etches a gas. The method for manufacturing a semiconductor device according to claim 6, wherein the rate is increased.