KR101155093B1 - Semiconductor memory device - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided to increase the area of a drive capacitor by forming a drive transistor and the drive capacitor on different layers. CONSTITUTION: A memory cell array(MCA) comprises a plurality of memory cells(MCEL) formed on a first layer of a first region. The memory cell comprises a memory element(ME) and a switch element(SE). The memory cell is connected to a single bit line among a plurality of bit lines(BL1-BLm) and a single word line among a plurality of word lines(WL1-WLn). A drive circuit unit(DRU) drives the memory cell array. The drive circuit unit comprises a plurality of drive capacitors and a plurality of drive transistors formed on a second region.

Description

Technical Field [0001] The present invention relates to a semiconductor memory device,

The present invention relates to a semiconductor memory device.

The semiconductor memory device includes a memory cell array including a plurality of memory cells capable of storing data, and a driving circuit unit for driving the memory cell array. The memory cell array and the driving circuit unit may be integrated on a single substrate.

An object of the present invention is to provide a semiconductor memory device capable of improving the degree of integration.

In accordance with another aspect of the present invention, a semiconductor memory device includes a memory cell array including a plurality of memory cells formed in a first layer of a first region, and a driving circuit unit for driving the memory cell array. The driving circuit unit includes a plurality of driving transistors and a plurality of driving capacitors formed in a second region, wherein the plurality of driving transistors are formed in a second layer, and a first driving capacitor of the plurality of driving capacitors It is formed in the first layer.

The first driving capacitor or part of the first driving capacitor may be formed to overlap the first driving transistor of the plurality of driving transistors.

The first driving capacitor may include a first capacitor and a second capacitor connected in parallel.

Each of the plurality of driving capacitors includes a first terminal and a second terminal, and the first layer of the second region includes a connection space in which the first terminal and the second terminal are not formed. A plurality of contacts electrically connected to the plurality of driving transistors may be formed in the space.

The first terminal of the first capacitor and the first terminal of the second capacitor may be electrically connected through a bridge signal line formed in the second layer.

The first terminal of the first capacitor is connected to a first bit line layer formed on the first layer, and the first terminal of the second capacitor is connected to a second bit line layer formed on the first layer. A branch bit line may be connected between the first bit line layer and the second bit line layer.

The second terminal of the first capacitor is connected to a first word line layer formed on the first layer, and the second terminal of the second capacitor is connected to a second word line layer formed on the first layer. A branch word line may be formed between the first word line layer and the second word line layer.

Each of the first capacitor and the second capacitor may include a plurality of capacitors, and the plurality of capacitors may be connected in parallel.

The first terminal of the first driving capacitor may include a semiconductor electrode layer and a driving active layer connected to the bit line layer, and the semiconductor electrode layer and the driving active layer may be formed by doping with impurities of the same type.

A first voltage may be applied to the first terminal of the first driving capacitor, a second voltage may be applied to a second terminal of the second driving capacitor, and the first voltage may be higher than the second voltage. .

The second driving transistor, which is one of the plurality of driving transistors, may be a third capacitor having a gate conductor as a first terminal and two electrically connected sources / drains as a second terminal.

The third capacitor may be connected in parallel to the first driving capacitor.

The memory cell array may include a bit line, a word line, and a resistance change material formed between the bit line and the word line.

The first driving capacitor may include a bit line layer, a word line layer, and a driving capacitor dielectric layer formed between the bit line layer and the word line layer.

The first driving capacitor may further include a resistance shift material.

The first driving capacitor may further include a lower layer and an upper layer formed by doping with impurities of the same type.

According to an embodiment of the present invention, a semiconductor memory device capable of improving the degree of integration may be provided.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.
1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention.
2 is a diagram illustrating an example of a driving transistor and a driving capacitor that may be included in the driving circuit unit of FIG. 1.
3 is a layout diagram illustrating a portion of a semiconductor memory device according to an embodiment of the present invention.
4 is a cross-sectional view taken along the line X1-X1 of FIG.
5 is a cross-sectional view taken along the line X2-X2 of FIG. 3.
6 is a cross-sectional view taken along the line Y1-Y1 of FIG.
FIG. 7 is a cross-sectional view taken along the line Y2-Y2 of FIG. 3. FIG.
8 to 13 are diagrams illustrating a method of forming a second layer of a semiconductor memory device according to an embodiment of the present invention.
14 to 23 are views illustrating a method of forming a first layer on a second layer of a semiconductor memory device according to an embodiment of the present invention.
24 is a layout diagram illustrating a portion of a semiconductor memory device according to another embodiment of the present invention.
FIG. 25 is a cross-sectional view taken along the line X1-X1 of FIG. 24.
26 is a layout diagram illustrating a portion of a semiconductor memory device according to another embodiment of the present invention.
FIG. 27 is a cross-sectional view taken along the line X1-X1 of FIG. 26.
FIG. 28 is a cross-sectional view taken along the line X2-X2 of FIG. 26.
29 is a layout for describing a method of manufacturing the semiconductor memory device of FIG. 26.
30 is a block diagram of a semiconductor memory device according to another embodiment of the present invention.
31 is a layout diagram illustrating a portion of a semiconductor memory device according to another embodiment of the present invention.
32 is a cross-sectional view taken along the line X1-X1 of FIG. 31.
33 is a cross-sectional view taken along the line X2-X2 of FIG. 31.
34 is a cross-sectional view taken along the line Y1-Y1 of FIG. 31;
35 is a cross-sectional view taken along the line Y2-Y2 of FIG. 31.
36 is a block diagram of a semiconductor memory device according to still another embodiment of the present invention.
37 is a layout diagram illustrating a portion of a semiconductor memory device according to still another embodiment of the present invention.
38 is a cross-sectional view taken along the line X1-X1 of FIG. 37.
FIG. 39 is a cross-sectional view taken along the line X2-X2 of FIG. 37.
40 is a cross-sectional view taken along the line Y1-Y1 of FIG. 37.
FIG. 41 is a cross-sectional view taken along the line Y2-Y2 of FIG. 37; FIG.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The embodiments of the present invention are described in order to more fully explain the present invention to those skilled in the art, and the following embodiments may be modified into various other forms, It is not limited to the embodiment. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art.

In the following description, when a layer is described as being on top of another layer, it may be directly on top of another layer, and a third layer may be interposed therebetween. In the drawings, the thickness and size of each layer are exaggerated for convenience and clarity of description, and the same reference numerals refer to the same elements in the drawings. As used herein, the term "and / or" includes any and all combinations of one or more of the listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. Also, as used herein, "comprise" and / or "comprising" specifies the presence of the mentioned shapes, numbers, steps, actions, members, elements and / or groups of these. It is not intended to exclude the presence or the addition of one or more other shapes, numbers, acts, members, elements and / or groups.

Although the terms first, second, etc. are used herein to describe various members, parts, regions, layers, and / or parts, these members, parts, regions, layers, and / or parts are defined by these terms. It is obvious that not. These terms are only used to distinguish one member, part, region, layer or portion from another region, layer or portion. Thus, the first member, part, region, layer or portion, which will be discussed below, may refer to the second member, component, region, layer or portion without departing from the teachings of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings schematically showing embodiments of the present invention. In the figures, for example, variations in the shape shown may be expected, depending on manufacturing techniques and / or tolerances. Accordingly, embodiments of the present invention should not be construed as limited to any particular shape of the regions illustrated herein, including, for example, variations in shape resulting from manufacturing. In addition, in the accompanying drawings, like reference numerals refer to like components.

1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor memory device SMD includes a memory cell array MCA and a driving circuit unit DRU.

The memory cell array MCA may include a plurality of memory cells MCEL arranged in a matrix form. Each memory cell MCEL is connected to one word line of the plurality of word lines WL1 to WLn and one bit line of the plurality of bit lines BL1 to BLm.

Each memory cell MCEL may include a memory device ME and a switch device SE. As shown in FIG. 1, when the memory device ME is a capacitor, the memory cell MCEL may be a DRAM memory cell. 1 is only an example, and the memory cell MCEL includes a phase-change RAM (PRAM), a resistive RAM (RRAM), a nano floating gate memory (NFGM), a polymer RAM (PoRAM), a magnetic RAM (MRAM), and a FeRAM. (Ferroelectric RAM) or flash memory cells.

The gate terminal of the switch element SE is connected to one of the plurality of word lines WL1 to WLn, the drain terminal is connected to one of the plurality of bit lines BL1 to BLm, and the source terminal is a memory element ME. It can be connected with.

The driving circuit unit DRU drives the memory cell array MCA. The driving circuit unit DRU may write data to the memory cell MCEL or read data stored in the memory cell MCEL. The driving circuit unit DRU may include a plurality of driving transistors and a plurality of driving capacitors.

The driving circuit unit DRU writes data into a decoder capable of selecting a specific memory cell among the plurality of memory cells MCEL, a sense amplifier capable of reading data stored in the memory cell MCEL, and a memory cell MCEL. Write drivers, voltage generators, and the like. Since the implementation of the driving circuit unit (DRU) will be apparent to those skilled in the art, a detailed description thereof will be omitted.

2 is a diagram illustrating an example of a driving transistor and a driving capacitor that may be included in the driving circuit unit of FIG. 1.

Referring to FIG. 2, the driving circuit unit includes a plurality of driving transistors DTR1 and DTR2 and a first driving capacitor DCP1. 2 shows two driving transistors DTR1 and DTR2 and one driving capacitor DCP1. However, FIG. 2 is only an example and does not limit the number of driving transistors or the number of driving capacitors included in the driving circuit unit (DRU of FIG. 1).

The first driving capacitor DCP1 may include a first capacitor C1 and a second capacitor C2 connected in parallel. The first terminal of the first driving capacitor DCP1 may be connected to the source terminal of the first driving transistor DTR1, and the second terminal of the first driving capacitor DCP1 may receive a ground voltage VSS.

The gate terminal of the first driving transistor DTR1 can receive the first gate voltage VG1, the drain terminal can receive the first drain voltage VD1, and the source terminal can receive the first driving capacitor DCP1. It can be connected with.

The second driving transistor DTR2 may not be connected to the first driving transistor DTR1 and the first driving capacitor DCP1. Each terminal of the second driving transistor DTR2 may receive a corresponding voltage VG2, VS2, and VD2.

3 is a layout diagram illustrating a portion of a semiconductor memory device according to an exemplary embodiment of the present invention, FIG. 4 is a cross-sectional view taken along the line X1-X1 of FIG. 3, and FIG. 5 is a line X2-X2 of FIG. 3. 6 is a cross-sectional view taken along the cut line Y1-Y1 of FIG. 3, and FIG. 7 is a cross-sectional view taken along the line Y2-Y2 of FIG. 3.

3 to 7 illustrate one embodiment of the memory cell array MCA and the driving circuit unit DRU of FIG. 1, in particular, the plurality of driving transistors DTR1 and DTR2 of FIG. 2 included in the driving circuit unit DRU, One embodiment of the driving capacitor DCP1 is implemented.

3 to 7, the semiconductor memory device includes a first region RG1 and a second region RG2 in plan view, and vertically includes a first layer LA1 and a second layer LA2. .

The first region RG1 is a region where the memory cell array MCA is formed, and the second region RG2 is a region except the first region RG1. In the second region RG2, a driving circuit unit (DRU of FIG. 1) is mainly formed.

The memory cell array MCA is formed in the first layer LA1 of the first region RG1. A plurality of driving transistors DTR1 and DTR2 are formed in the second layer LA2 of the second region RG2. The driving transistor DTR3 may be formed in the second layer LA2 of the first region RG1. That is, the plurality of driving transistors DTR1 to DTR3 are planarly formed in both the first region RG1 in which the memory cell arrays MCA are formed and in the second region RG2 in which the memory cell arrays MCA are not formed. Can be. The plurality of driving transistors DTR1 to DTR3 are formed in the second layer LA2 in which the memory cell array MCA is not formed vertically.

The first driving capacitor DCP1 is formed in the first layer LA1 of the second region RG2. The first driving capacitor DCP1 may include a first capacitor C1 and a second capacitor C2.

The first driving capacitor DCP1 is formed in the second region RG2 which is different from the first region RG1 in which the memory cell array MCA is formed, but is the same as the layer in which the memory cell array MCA is formed. It is formed in the first layer LA1.

A semiconductor is formed by separating a first layer LA1 in which the first driving capacitor DCP1 included in the driving circuit unit (DRU of FIG. 1) is formed, and a second layer LA2 in which the plurality of driving transistors DTR1 to DTR3 are formed. The planar area of the memory device can be reduced, and the degree of integration of the semiconductor memory device can be improved. In addition, by forming the driving transistor and the driving capacitor in different layers, the area of the driving capacitor can be increased, so that the capacity of the driving capacitor can be increased. That is, the area of the driving capacitor can be increased without increasing the overall planar area of the semiconductor memory device due to the formation of the driving capacitor.

The first driving capacitor DCP1 or a part of the first driving capacitor DCP1 (eg, the first capacitor C1) may be formed to overlap the first driving transistor DTR1. The first capacitor C1 formed in the first layer LA1 may overlap the first driving transistor DTR1 formed in the second layer LA2. The second capacitor C2 may overlap the second driving transistor DTR2.

The first layer LA1 of the second region RG2 may include a connection space CS. The connection space CS is a space in which a plurality of driving capacitors (including the first driving capacitor DCP1) are not formed in the first layer LA1 of the second region RG2. The connection space CS may include a plurality of fourth contacts 350 electrically connected to the plurality of driving transistors DTR1 and DTR2.

For example, the gate conductor 130 of the first driving transistor DTR1 receives the first gate voltage VG1 through the fourth contact 350, and the source / drain of the first driving transistor DTR1. 107 may receive the first drain voltage VD1 through the fourth contact 350.

The first capacitor C1 and the second capacitor C2 included in the first driving capacitor DCP1 may be connected in parallel. The first terminal T1a of the first capacitor C1 and the first terminal T2a of the second capacitor C2 are electrically connected, and the second terminal T1b and the second capacitor of the first capacitor C1 are electrically connected. The second terminal T2b of C2 may be electrically connected.

The first and second capacitors C1 and C2 may be connected in parallel to implement the first driving capacitor DCP1 in various ways.

For example, as illustrated in FIGS. 3 to 7, the first terminal T1a of the first capacitor C1 and the first terminal T2a of the second capacitor C2 are formed in the second layer LA2. It may be electrically connected through the bridge signal line 160B. The second terminal T1b of the first capacitor C1 and the second terminal T2b of the second capacitor C2 may be electrically connected to each other by receiving a ground voltage VSS through the third contact 340. have.

The first terminals T1a and T2a of the first and second capacitors C1 and C2 may be electrically connected to the first driving transistor DTR1. The second terminals T1b and T2b of the first and second capacitors C1 and C2 may receive a ground voltage VSS. Therefore, the voltage applied to the first terminals T1a and T2a of the first and second capacitors C1 and C2 is greater than the voltage applied to the second terminals T1b and T2b of the first and second capacitors C1 and C2. Can be high.

Next, a method of manufacturing the semiconductor memory device of FIGS. 2 to 7 will be described with reference to FIGS. 8 to 23.

8 to 13 are diagrams illustrating a method of forming a second layer of a semiconductor memory device according to an embodiment of the present invention. 9, 11, and 13 are cross-sectional views taken along line X1-X1 of FIGS. 8, 10, and 12, respectively.

First, referring to FIGS. 8 and 9, a shallow trench isolation (STI) 110 is formed on the first substrate 100. For example, the first substrate 100 may be made of silicon, glass, quartz, or the like. The STI 110 may be made of a dielectric material such as silicon oxide, such as boro-phosphor silicate glass (BPSG), undoped silicate glass (USG), spin on glass (SOG), and tetraethylorthosilicate (TEOS). Since the method for forming the STI 110 is apparent to those skilled in the art, a detailed description thereof will be omitted.

P-type wells 101 and n-type wells 102 are formed in the first substrate 100 through an ion implantation process. Next, the gate dielectric 120, the gate conductor 130, and the gate hard mask 131 on the p-type wells 101 and the n-type wells 102 through deposition and photolithography processes. And a gate spacer 132.

For example, the gate conductor 130 may be made of metal nitride such as copper, aluminum, gold, titanium nitride, tungsten nitride, tantalum nitride, titanium aluminum nitride, doped polysilicon, or a composite film thereof. have. The gate hard mask 131 and the gate space 132 may be made of a silicon nitride film, a silicon oxide film, or a composite film thereof.

An ion implantation process forms an n-type LDD (Lightly Doped Drain) 105 in the p-type well region 101, and forms a p-type LDD 106 in the n-type well region 102. An n-type source / drain 107 is formed in the p-type well region 101, and a p-type source / drain 108 is formed in the n-type well region 102.

For example, n-type well 102, n-type LDD 105 and n-type source / drain 107 are formed by ion implantation of impurities such as Phosphorus or Arsenic, respectively. can do. The p-type well 101, the p-type LDD 106, and the p-type source / drain 108 may be formed by ion implantation of boron or a combination of boron and fluorine. Since the ion implantation process technology is apparent to those skilled in the art, detailed description thereof will be omitted.

As a result, a plurality of driving transistors DTR1 to DTR3 including the gate conductor 130 and the source / drain 107 or 108 are formed.

Most of the plurality of driving transistors of the driving circuit unit (DRU of FIG. 1) are formed in the second region RG2 like the first and second driving transistors DTR1 and DTR2. However, some transistors included in the driving circuit unit (DRU of FIG. 1), such as the third driving transistor DTR3 of the first region RG1, may be formed in the first region RG1.

Next, referring to FIGS. 10 and 11, the first interlayer insulating layer 140 is formed on the first substrate 100 on which the plurality of driving transistors DTR1 to DTR3 are formed through a deposition process. The first interlayer insulating layer 140 may be formed by depositing a sufficiently thick dielectric film such as silicon oxide, such as BPSG, USG, SOG, and TEOS, and then planarization through chemical mechanical polishing (CMP). For example, the dielectric film may be formed through a known deposition method such as chemical vapor deposition (CVD), spin coating, atomic layer deposition (ALD), or the like.

A plurality of contact holes are formed in the first interlayer insulating layer 140 through a photolithography process. Each contact hole exposes the gate conductor 130 or the source / drain 107 or 108 of the plurality of driving transistors DTR1 to DTR3.

A plurality of first contacts 150 are formed by plugging a conductive material into each contact hole. For example, the conductive material plugged into each contact hole may be a metal such as copper, aluminum, gold, tungsten or titanium, a metal nitride such as titanium nitride, tungsten nitride, cobalt nitride, tantalum nitride, or titanium aluminum nitride, or doped polysilicon. Or combinations thereof.

A plurality of first signal lines 160 and a plurality of first hard masks 161 are formed through a deposition and photolithography process. Each first signal line 160 is formed to contact the first contact 150. Hereinafter, a signal line connected to one source / drain 107 of the first driving transistor DTR1 through the first contact 150 among the plurality of first signal lines 160 is referred to as a bridge signal line 160B.

For example, the first signal line 160 may be formed of metals such as copper, aluminum, gold, tungsten, titanium, metal nitrides such as titanium nitride, tungsten nitride, cobalt nitride, tantalum nitride, titanium aluminum nitride, doped polysilicon, or the like. It may be a combination material of. The first hard mask 161 may be a silicon nitride film.

Next, referring to FIGS. 12 and 13, a second interlayer insulating layer 170 is formed on the first interlayer insulating layer 140, the first signal line 160, and the first hard mask 161 through a deposition process. The second interlayer insulating film 170 may be formed by depositing a dielectric film such as silicon oxide, such as BPSG, USG, SOG, and TEOS, sufficiently thickly, and then performing planarization through chemical mechanical polishing (CMP).

After forming a plurality of contact holes exposing the bridge signal line 160B in the second interlayer insulating layer 170 through a photolithography process, the second contact 180 is formed by plugging a conductive material into each contact hole.

The plugged conductive material of the second contact 180 may be a conductive material, and is not particularly limited. For example, the plugged conductive material of the second contact 180 may be a metal such as copper, aluminum, gold, metal nitride such as titanium nitride, tungsten nitride, tantalum nitride, titanium aluminum nitride, doped polysilicon, or a combination thereof. It may be a substance.

Hereinafter, the first substrate 100 to the second interlayer insulating layer 170 are referred to as a second layer LA2 of the semiconductor memory device.

14 to 23 are views illustrating a method of forming a first layer on a second layer of a semiconductor memory device according to an embodiment of the present invention. FIG. 15 is a cross-sectional view taken along the line X1-X1 of FIG. 14, FIG. 17 is a cross-sectional view taken along the line X1-X1 of FIG. 16, and FIG. 18 is a cross-sectional view taken along the line Y1-Y1 of FIG. 16. 19 is a cross-sectional view taken along the line Y2-Y2 of FIG. 16, and FIG. 21 is a cross-sectional view taken along the line X1-X1 of FIG. 20, and FIG. 22 is a cross-sectional view taken along the line Y1-Y1 of FIG. 20. 23 is a cross-sectional view taken along the line Y2-Y2 of FIG. 20.

First, referring to FIGS. 14 and 15, the bit line material layer 190 and the lower source / drain material layer 200 are formed on the second interlayer insulating layer 170 through a deposition process. In the first region RG1, the cell active layer material layer 211 is formed on the lower source / drain material layer 200, and in the second region RG2, the cell active layer material layer 2 is formed on the lower source / drain material layer 200. 213).

The bit line material film 190 may be a conductive material, and is not particularly limited. For example, the bit line material film 190 may be metal nitride such as copper, aluminum, gold, titanium nitride, tungsten nitride, tantalum nitride, titanium aluminum nitride, or the like, doped polysilicon, or a combination thereof. .

The lower source / drain material layer 200 may be made of a semiconductor material such as doped polysilicon, active silicon implanted with ions, or a composite film thereof.

The cell active layer material layer 211 and the driving active layer material layer 213 are formed in the first region RG1 after forming a second substrate (not shown) on the lower source / drain material layer 200. Cell channel doping may be performed on the substrate (not shown), and ion implantation of the same type as the lower source / drain material layer 200 may be performed on the second substrate (not shown) included in the second region RG2. Can be. If the lower source / drain material layer 200 is doped with n-type impurities, the impurities of the driving active layer material layer 213 are also n-type impurities. For example, the lower source / drain material layer 200 may be doped with n-type impurities such as phosphorus, the cell active layer material layer 211 may be doped with p-type material such as boron, and the driving active layer material film ( 213 may be doped with n-type impurities such as phosphorus. The driving active layer material layer 213 is formed by doping with impurities of the same type as the lower source / drain material layer 200 will be described later.

In this case, the second substrate (not shown) is a silicon single crystal film, and may be formed using a method such as a smartcut.

16 to 19, a bit line 193 is formed in the first region RG1 on the second interlayer insulating layer 170 from the bit line material layer 190 of FIG. 15, and the second region RG2. The first bit line layer 191 and the second bit line layer 192 are formed thereon. Hereinafter, the bit line 193 and the bit line layers 191 and 192 are referred to as bit line conductors.

The bit line conductors 191 to 193 may be formed in the following manner. A second substrate hard mask (not shown) made of a material such as a silicon nitride film is formed on the cell active layer material film 211 of FIG. 15 and the driving active layer material film 213 of FIG. 15 through a deposition process. A second substrate hard mask (not shown), a cell active layer material film (211 of FIG. 15), a lower source / drain material film (200 of FIG. 15), and a bit line material film in the first region RG1 through a photolithography process. By etching (190 in FIG. 15), a bit line 193 may be formed. At the same time, in the second region RG2, a second substrate hard mask (not shown), a driving active layer material film (213 of FIG. 15), a lower source / drain material film (200 of FIG. 15), and a bitline material film (FIG. 15). By etching 190, first and second bit line layers 191 and 192 of the second region RG2 may be formed.

After the formation of the bit line conductors 191 to 193, a first dielectric film (not shown) such as USG, SOG, and BPSG is sufficiently thickly deposited on the second interlayer insulating film 170 and the second substrate hard mask (not shown). After that, planarization is performed through CMP using a second substrate hard mask (not shown) as a blocking film. The second substrate hard mask (not shown), the cell active layer material film (211 of FIG. 15) and the lower source / drain material film (200 of FIG. 15) of the first region RG1 may be etched through a photolithography process. A plurality of pillars including a lower source / drain electrode layer 202 and a cell active layer 212 are formed on the bit line 193 of the first region RG1. At the same time, the second substrate hard mask (not shown) of the second region RG2, the driving active layer material layer (213 of FIG. 15), and the lower source / drain material layer (200 of FIG. 15) are etched to form the second region ( A plurality of pillars including the lower electrode layer 203 and the driving active layer 214 are formed on the first and second bit line layers 191 and 192 of the RG2. In this case, the first dielectric layer (not shown) may be etched to form a third interlayer insulating layer 231.

Next, after depositing a sufficiently thick second dielectric film (not shown), such as USG, SOG, and BPSG, on the third interlayer insulating film 231 and the plurality of pillars, CMP using a second substrate hard mask (not shown) as a blocking film. Planarization is carried out through the process. Next, a second dielectric layer (not shown) may be selectively etched through a selective etching process to form a fourth interlayer insulating layer 241 disposed below the top surface of the cell active layer 212 and the top surface of the driving active layer 214.

After forming the fourth interlayer insulating layer 241, the second gate dielectric layer 250 is formed on the side of the pillar through an oxidation process and a deposition process. By depositing a next wordline material film (not shown) and selectively etching the wordline material film (not shown), the wordline material film (not shown) is formed on top of the cell active layer 212 and on top of the driving active layer 214. Place it below the face. Next, the word line 260 of the first region RG1 and the first and second word line layers 261 and 262 of the second region RG2 are formed through a photolithography process. Hereinafter, the word line 260 and the word line layers 261 and 262 are referred to as word line conductors.

After the word line conductors 260 to 262 are formed, a third dielectric film such as USG, SOG, and BPSG on the fourth interlayer insulating layer 241, the word line conductors 260 to 262, and the second substrate hard mask (not shown). After depositing (not shown) thick enough, planarization is performed through CMP using a second substrate hard mask (not shown) as a blocking film. Next, the fifth interlayer insulating layer 270 is selectively removed by selectively removing the second substrate hard mask (not shown) and selectively etching the third dielectric layer (not shown) to the top of the cell active layer 212 and the driving active layer 214. Form.

20 to 23, through the ion implantation process, the upper source / drain electrode layer 280 is formed on the cell active layer 212 of the first region RG1, and at the same time, the driving active layer of the second region RG2 is formed. An upper electrode layer 281 is formed over the 214. As a result, the switch element SE of FIG. 1 of the memory cell (MCEL of FIG. 1) may be formed in the first region RG1, and the first driving capacitor DCP1 may be formed in the second region RG2. .

In the first region RG1, a cell active layer 212 doped with impurities of a different type from the upper and lower source / drain electrode layers 280 and 202 between the upper source / drain electrode layer 280 and the lower source / drain electrode layer 202. ) Is formed. Therefore, in the first region RG1, the upper source / drain electrode layer 280, the word line 260, and the lower source / drain electrode layer 202 form a three-terminal switch element SE.

In the second region RG2, a driving active layer 214 doped with impurities of the same type as the upper and lower electrode layers 281 and 203 is formed between the upper electrode layer 281 and the lower electrode layer 203. The upper electrode layer 281 and / or the lower electrode layer 203 may be referred to as a semiconductor electrode layer. For example, in the second region RG2, the semiconductor electrode layer (eg, the upper electrode layer 281 or the lower electrode layer 203) and the driving active layer 214 may both be doped with n-type impurities.

Therefore, the plurality of pillars including the lower electrode layer 203, the driving active layer 214, and the upper electrode layer 281 in the second region RG2 form the first terminals T1a and T2a of the capacitors C1 and C2, respectively. The first and second word line layers 261 and 262 form second terminals T1b and T1b of the capacitors C1 and C2, respectively. That is, the second terminals T1b and T1b of the capacitors C1 and C2 may include word line layers 261 and 262.

The plurality of pillars of the first capacitor C1 are all connected to the first bit line layer 191, and the first word line layer 261 is connected to one other except a portion where the pillars are formed. Therefore, the first capacitor C1 may be formed of a plurality of capacitors connected in parallel. The second capacitor C2 may also be formed of a plurality of capacitors connected in parallel.

Next, an etch stop layer 290 and a storage lower electrode 300 are formed on the fifth interlayer insulating layer 270.

The etch stop layer 290 and the storage lower electrode 300 may be formed in the following manner. First, an etch stop layer (not shown) and a mold material layer (not shown) are formed on the fifth interlayer insulating layer 270, and the etch stop layer (not shown) and the mold material layer (not shown) are formed through a photolithography process. Holes exposing the upper source / drain electrode layer 280 of the first region RG1 are formed. That is, holes are formed in the etch stop layer (not shown) to form the etch stop layer 290. Next, a conductive material is formed conformally in the holes to form a storage lower electrode material film (not shown), and the holes are filled through the sacrificial film on the storage lower electrode material film, and then each node is separated through node separation. The storage lower electrode 300 is formed. For example, the etch stop layer may be silicon nitride, and the mold material layer may be silicon oxide.

Referring to FIGS. 3 to 7 again, after forming the cell capacitor dielectric layer 310, after forming the storage upper electrode 320 on the cell capacitor dielectric layer 310 in the first region RG1, a sixth interlayer insulating layer is formed. 330 is formed.

In the first region RG1, the storage lower electrode 300 and the storage upper electrode 320 form a memory device (ME of FIG. 1). In the formation of the storage upper electrode 320, a plurality of memory cells (MCEL of FIG. 1) including a switch element (SE of FIG. 1) and a memory element (ME of FIG. 1) are respectively formed, thereby forming a memory cell array (MCA). ) Is formed.

The illustrated memory cell is a DRMA memory cell in which the memory element is a capacitor. However, this is only an example.

Next, a plurality of holes are formed by a photolithography process, and a plurality of third contacts 340 and a plurality of fourth contacts 350 are formed in the second region RG2 by plugging a conductive material into the plurality of holes. .

The first terminal T1a of the first capacitor C1 is connected to the first bit line layer 191, and the first terminal T2b of the second capacitor C1 is connected to the second bit line layer 192. It is. Alternatively, the first terminal T1a of the first capacitor C1 includes a first bit line layer 191, and the first terminal T2a of the second capacitor C1 has a second bit line layer 192. It may be interpreted to include. The first bit line layer 191 and the second bit line layer 192 are physically separated, and the first word line layer 261 and the second word line layer 262 are physically separated to form a connection space CS. Can be formed. The first terminals T1a and T2a and the second terminals T1b and T2b of the plurality of driving capacitors (eg, the first driving capacitor DCP1) may not be formed in the connection space CS.

The first terminals T1a and T2a of the first and second capacitors C1 and C2 are electrically connected to each other through the bridge signal line 160B formed in the second layer LA2.

The plurality of third contacts 340 may be electrically connected to the first and second word line layers 261 and 262, respectively, and may receive a ground voltage VSS. Therefore, the first driving capacitor DCP1 including the first and second capacitors C1 and C2 connected in parallel may be formed.

Since the first terminals T1a and T2a of the first driving capacitor DCP1 include the lower electrode layer 203, the upper electrode layer 281, and the driving active layer 214, one of the lower electrode layer 203 and the upper electrode layer 281. Even when a voltage is applied to only one semiconductor electrode layer, the first driving capacitor DCP1 may function as a capacitor.

Therefore, the areas of the first terminals T1a and T2a of the first driving capacitor DCP1 are increased, and the capacitance of the first driving capacitor DCP1 is increased. This can minimize voltage losses.

The plurality of fourth contacts 350 are formed in the connection space CS to be electrically connected to the plurality of driving transistors DTR1 and DTR2 of the second layer LA2.

As described above, according to the exemplary embodiment of the present invention, a semiconductor memory device and a method of manufacturing the same may be provided.

FIG. 24 is a layout diagram illustrating a portion of a semiconductor memory device according to another exemplary embodiment. FIG. 25 is a cross-sectional view taken along the line X1-X1 of FIG. 24. 24 and 25 are modified parts of FIGS. 3 and 4, and thus descriptions overlapping with those of FIGS. 3 and 4 will be omitted.

24 and 25, a branch bit line 190B may be formed between the first bit line layer 191 and the second bit line layer 192. The first bit line layer 191 and the second bit line layer 192 may be electrically connected through the branch bit line 190B.

In addition, a branch word line 260B may be formed between the first word line layer 261 and the second word layer 262. The first word line layer 261 and the second word line layer 262 may be electrically connected through the branch word line 260B.

The first capacitor C1 and the second capacitor C2 may be connected in parallel to each other to form one driving capacitor DCP1 through the branch bit line 190B and the branch word line 260B.

24 and 25, the bridge signal line 160B connecting the first capacitor C1 and the second capacitor C2 does not need to be formed as shown in FIGS. 3 and 4. The signal line 160C of FIGS. 23 and 24 may electrically connect the first capacitor C1 and the first driving transistor DTR1.

FIG. 26 is a layout diagram illustrating a portion of a semiconductor memory device according to another exemplary embodiment of the inventive concept. FIG. 27 is a cross-sectional view taken along the line X1-X1 of FIG. 26, and FIG. 28 illustrates the line X2-X2 of FIG. 26. 29 is a cross-sectional view taken along the cut line and FIG. 29 is a layout diagram for describing a method of manufacturing the semiconductor memory device of FIG. 26.

26 to 28 are modified parts of FIGS. 3 to 5, and FIG. 29 is a modified part of FIG. 12. Therefore, duplicated content is omitted.

26 to 29, the gate conductor 130 of the second driving transistor DTR2 is electrically connected to the first signal line 160 through the first contact 150 and the first signal line 160. The second bit line layer 192 is electrically connected to the first terminal T2a of the second capacitor C2 through the second bit line layer 192.

The two p-type sources / drains 108 of the second driving transistor DTR2 are electrically connected to the first signal line 160 through two first contacts 150. That is, the two p-type sources / drains 108 of the second driving transistor DTR2 are physically separated, but electrically connected. As a result, the second driving transistor DTR2 is in the form of a transistor, but the gate conductor 130 is used as the first terminal, and the two p-type sources / drains 108 electrically connected to each other are used as the second terminal. It becomes a capacitor.

The first signal line 160 connecting the two p-type sources / drains 108 may receive the ground voltage VSS through the fourth contact 350.

Therefore, the first and second capacitors C1 and C2 and the second driving transistor DTR2 serving as a capacitor may be connected in parallel.

In FIGS. 26 to 29, the second driving transistor DTR2 serving as a capacitor is formed in the n-type well 102 and is shown to include a p-type source / drain 108, but FIGS. 26 to 29. Is just an example. The second driving transistor DTR2 serving as a capacitor may be formed in the p-type well and include an n-type source / drain.

30 is a block diagram of a semiconductor memory device according to another embodiment of the present invention. Since FIG. 30 is a modification of the memory cell of FIG. 1, a description overlapping with FIG. 1 will be omitted.

Referring to FIG. 30, each memory cell MCEL includes a resistor device RE and a diode device DE. The memory cell MCEL of FIG. 30 may be a PRAM memory cell or an RRAM memory cell that stores information in the resistor device RE.

The cathode terminal of the diode device DE is connected to one of the plurality of word lines WL1 to WLn, and the anode terminal of the diode device DE is connected to one end of the resistor device RE. have. The other end of the resistor element RE is connected to one of the plurality of bit lines BL1 to BLm.

The driving circuit unit DRU may select a specific memory cell among the plurality of memory cells MCEL, write data into the resistance element RE of the specific memory cell MCEL, or store data in the resistance element RE. Can be read.

FIG. 31 is a layout diagram illustrating a portion of a semiconductor memory device according to another exemplary embodiment of the present invention. FIG. 32 is a cross-sectional view taken along the line X1-X1 of FIG. 31, and FIG. 33 illustrates the line X2-X2 of FIG. 31. 34 is a cross-sectional view taken along the cut line Y1-Y1 of FIG. 31, and FIG. 35 is a cross-sectional view taken along the line Y2-Y2 of FIG. 31.

31 to 35 illustrate one embodiment of the memory cell array MCA and the driving circuit unit DRU of FIG. 30. 31 to 35 are modified parts of FIGS. 3 to 7, and thus descriptions overlapping with those of FIGS. 3 to 7 will be omitted. The second layer LA2 in which the plurality of driving transistors DTR1 to DTR3 are formed is the same as in FIGS. 3 to 7.

31 to 35, a bit line 193 is formed in a first region RG1 on the second interlayer insulating layer 170, and a first bit line layer 191a and a second region RG2. The second bit line layer 192a is formed.

A plurality of pillars including a resistance element 302, a p-type layer 243, and an n-type layer 245 are formed on the bit line 193 of the first region RG1. For example, the resistance element 302 may be GST (Ge-Sb-Te). The resistance element 302 corresponds to the resistance element RE of FIG. 30. The p-type layer 243 and the n-type layer 245 correspond to the diode device DE of FIG. 30. That is, the pillar formed of the resistive element 302, the p-type layer 243, and the n-type layer 245 corresponds to the memory cell MCEL of FIG. 30.

A pillar formed of a resistance transition material 301, a lower n-type layer 244, and an upper n-type layer 246 is formed on each of the bit line layers 191a and 192a of the second region RG2.

The height of the pillar formed in the first region RG1 and the height of the pillar formed in the second region RG2 may be the same. However, the horizontal area of the pillar formed in the first region RG1 may be different from the horizontal area of the pillar formed in the second region RG2.

An interlayer dielectric film 248 is formed between the plurality of pillars of the first region RG1 and between the plurality of pillars of the second region RG2.

In the first region RG1, the p-type layer 243 and the n-type layer 245 are formed by doping different types of impurities to form a diode device (DE of FIG. 30). On the other hand, in the second region RG2, the lower n-type layer 244 and the upper n-type layer 246 are both formed by doping with impurities of the same type. That is, the lower n-type layer 244 and the upper n-type layer 246 may both be p-type layers.

The word line 260 is formed on the plurality of pillars including the resistance element 302, the p-type layer 243, and the n-type layer 245 of the first region RG1. The word line 260 is formed in contact with the n-type layer 245. In the first region RG1, a memory cell array MCA may be formed from the bit line 193 to the word line 260.

Word lines layers 261a and 262a are formed on the pillars including the resistance change material 301, the lower n-type layer 244, and the upper n-type layer 246 in the second region RG2. A driving capacitor dielectric layer 255 is formed between the pillars and the word line layers 261a and 262a. Thus, the upper n-type layer 246 is not in contact with the word line layers 261a and 262a.

As such, the driving capacitor dielectric layer 255 may be formed between the bit line layers 191a and 192a and the word line layers 261a and 262a in the second region RG2.

The pillar composed of the resistance transition material 301, the lower n-type layer 244, and the upper n-type layer 246 of the second region RG2 may have a first terminal T1a and T2a of the capacitors C1 and C2. The first and second word line layers 261a and 262a form second terminals T1b and T2b of the capacitors C1 and C2. That is, the second terminals T1b and T1b of the capacitors C1 and C2 may include word line layers 261 and 262.

The first terminal T1a of the first capacitor C1 is connected to the first bit line layer 191a, and the first terminal T2a of the second capacitor C2 is connected to the second bit line layer 192a. It is. The first bit line layer 191a and the second bit line layer 192a may be physically separated to form a connection space CS.

Alternatively, the first terminal T1a of the first capacitor C1 includes a first bit line layer 191, and the first terminal T2a of the second capacitor C1 has a second bit line layer 192. It may be interpreted to include.

The first terminals T1a and T2a of the first and second capacitors C1 and C2 are electrically connected to each other through the bridge signal line 160B formed in the second layer LA2.

The plurality of third contacts 340 may be electrically connected to the first and second word line layers 261 and 262, respectively, and may receive a ground voltage VSS. Therefore, the first driving capacitor DCP1 including the first and second capacitors C1 and C2 connected in parallel may be formed.

Structure of the memory cell array MCA formed in the first layer LA1 of the first region RG1 and structure of the first driving capacitor DCP1 formed in the first layer LA1 of the second region RG2. Except for, the structure is almost the same as that of FIGS. Therefore, duplicated content is omitted.

36 is a block diagram of a semiconductor memory device according to still another embodiment of the present invention. FIG. 36 is a modified form of the memory cell of FIG. 30, and thus descriptions overlapping with those of FIG. 30 will be omitted.

Referring to FIG. 36, each memory cell MCEL includes a resistor element RE. The memory cell MCEL of FIG. 36 may be a PRAM memory cell or an RRAM memory cell that stores information in the resistor device RE.

One end of the resistor element RE is connected to one of the plurality of word lines WL1 to WLn, and the other end of the resistor element RE is connected to one of the plurality of bit lines BL1 to BLm. The memory cell MCEL of FIG. 36 is a form in which the diode device DE is removed from the memory cell MCEL of FIG. 31.

 The state of the resistor element RE may be controlled by the magnitude of the current flowing through the resistor element RE and the amount of current, thereby controlling data stored in the resistor element RE. Accordingly, as shown in FIG. 36, the memory cell MCEL may be implemented without the diode device DE of FIG. 30.

FIG. 37 is a layout diagram illustrating a portion of a semiconductor memory device according to still another embodiment of the inventive concept, FIG. 38 is a cross-sectional view taken along line X1-X1 of FIG. 37, and FIG. 39 is a line X2-X2 of FIG. 37. 40 is a cross-sectional view taken along the cut line Y1-Y1 of FIG. 37, and FIG. 41 is a cross-sectional view taken along the line Y2-Y2 of FIG. 37.

37 to 41 illustrate one embodiment of the memory cell array MCA and the driving circuit unit DRU of FIG. 36. 37 to 41 are modified parts of FIGS. 31 to 35, and thus descriptions overlapping with those of FIGS. 31 to 35 will be omitted.

37 to 41, the memory cell array MCA is formed in the first layer LA1 of the first region RG1. The memory cell array MCA includes a bit line 193, a word line 260, and a resistor 302 formed between the bit line 193 and the word line 260. In FIGS. 31 to 35, the p-type layer 243 and the n-type layer 245 constituting the diode element are formed on the resistor element 302. In FIGS. 37 to 41, the p-type layer 243 is formed. And n-type layer 245 is not formed.

The first driving capacitor DCP1 is formed in the first layer LA1 of the second region RG2. The first driving capacitor DCP1 may include a first capacitor C1 and a second capacitor C2 connected in parallel.

The resistance change material 301 connected to the first and second bit line layers 191a and 192a of the second region RG2 forms the first terminals T1a and T2a of the capacitors C1 and C2. The first and second word line layers 261a and 262a form second terminals T1b and T2b of the capacitors C1 and C2.

31 to 35, the lower n-type layer 244 and the upper n-type layer 246 are included in the first terminals T1a and T1b of the capacitors C1 and C2 in addition to the resistance transition material 301. 37 through 41, the lower n-type layer 244 and the upper n-type layer 246 are not formed.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms are employed herein, they are used for purposes of describing the present invention only and are not used to limit the scope of the present invention. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

100: first substrate 110: STI
107: n-type source / drain 108: p-type source / drain
130: gate conductor 150: first contact
160: first signal line 160B: bridge signal line
170: second interlayer insulating film 180: second contact
191, 192, 193: Bitline Conductor
202: lower source / drain electrode layer 203: lower electrode layer
212: cell active layer region 214: driving active layer
260, 261, 262: wordline conductors
280: upper source / drain electrode layer 281: upper electrode layer
300: lower storage electrode 320: upper storage electrode
340: third contact 350: fourth contact

Claims (16)

A memory cell array including a plurality of memory cells formed in a first layer of a first region; And
A driving circuit unit for driving the memory cell array,
The driving circuit unit includes a plurality of driving transistors and a plurality of driving capacitors formed in a second region,
The plurality of driving transistors are formed in a second layer,
And a first driving capacitor of the plurality of driving capacitors is formed in the first layer. The semiconductor memory device of claim 1, wherein the first driving capacitor or a part of the first driving capacitor is formed to overlap the first driving transistor of the plurality of driving transistors. The semiconductor memory device of claim 2, wherein the first driving capacitor includes a first capacitor and a second capacitor connected in parallel. The method of claim 3, wherein each of the plurality of driving capacitors comprises a first terminal and a second terminal,
The first layer of the second region includes a connection space in which the first terminal and the second terminal are not formed.
And a plurality of contacts electrically connected to the plurality of driving transistors in the connection space. 4. The semiconductor memory device of claim 3, wherein the first terminal of the first capacitor and the first terminal of the second capacitor are electrically connected through a bridge signal line formed in the second layer. The method of claim 3, wherein the first terminal of the first capacitor is connected to a first bit line layer formed in the first layer, and the first terminal of the second capacitor is formed in the first layer. Is connected to the second bit line layer,
And a branch bit line is formed between the first bit line layer and the second bit line layer. The method of claim 3, wherein the second terminal of the first capacitor is connected to a first word line layer formed in the first layer, and the second terminal of the second capacitor is formed in the first layer. Is connected to the second word line layer,
And a branch word line is formed between the first word line layer and the second word line layer. The semiconductor device of claim 3, wherein each of the first capacitor and the second capacitor includes a plurality of capacitors, and the plurality of capacitors are connected in parallel. The method according to claim 1,
The first terminal of the first driving capacitor includes a semiconductor electrode layer and a driving active layer connected to the bit line layer,
And the semiconductor electrode layer and the driving active layer are both formed by doping with the same type of impurities. 10. The method of claim 9,
A first voltage is applied to the first terminal of the first driving capacitor, and a second voltage is applied to the second terminal of the second driving capacitor.
And the first voltage is higher than the second voltage. The second driving transistor, which is one of the plurality of driving transistors, is a third capacitor having a gate conductor as a first terminal and two electrically connected sources / drains as a second terminal. A semiconductor memory device. The semiconductor memory device of claim 11, wherein the third capacitor is connected in parallel with the first driving capacitor. The semiconductor memory device of claim 1, wherein the memory cell array comprises a bit line, a word line, and a resistance shift material formed between the bit line and the word line. The semiconductor memory device of claim 13, wherein the first driving capacitor includes a bit line layer, a word line layer, and a driving capacitor dielectric layer formed between the bit line layer and the word line layer. The semiconductor memory device of claim 14, wherein the first driving capacitor further comprises a resistance shift material. The semiconductor memory device of claim 15, wherein the first driving capacitor further comprises a lower layer and an upper layer formed by doping with impurities of the same type.

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