KR101171874B1 - Non-volatile memory device and method of fabricating the same - Google Patents

Abstract

PURPOSE: A non-volatile memory device and a manufacturing method thereof are provided to improve data retention power and durability and to obtain device reliability by controlling thermal interference between neighboring memory cells. CONSTITUTION: A plurality of memory cells(MC1,MC2) includes a nonvolatile storage element(SE). The plurality of memory cells is arranged in an array shape consisting of a plurality of rows and columns. A transistor(TR) is formed in an active area defined by an element isolation film(11). A memory film(ML) is electrically connected to source/drain regions(S/D) of the transistor through a contact pad(20C). Contact pads and via plugs(40V1,40V2) are electrically insulated by one or more insulating layers(20,30,40).

Description

Non-volatile memory device and method of manufacturing the same {Non-volatile memory device and method of fabricating the same}

The present invention relates to semiconductor device technology, and more particularly, to a nonvolatile memory device using a resistive memory film and a method of manufacturing the same.

In recent years, the demand for portable digital applications such as digital cameras, MP3 players, personal digital assistants (PDAs), and cellular phones is increasing, and the nonvolatile memory market is rapidly expanding. As a programmable nonvolatile memory, high density flash memory devices with low manufacturing cost per bit are widely used. However, flash memory requires relatively large capacitance transistors for hot carrier injection operations for programming, and because it requires a thick tunneling oxide that can withstand high internal voltages to ensure reliable data retention, its scaling Has a basic limitation. As a recent flash memory reaches the limit of scaling, it is a nonvolatile memory that can replace the phase change random access memory (PRAM) or the resistive random access memory (PRAM) using a resistive memory material having a variable resistance value. Resistance Random Access Memory (RRAM) is attracting attention.

Since the resistive memory material has a bi-stable resistive state in which the resistive state can be reversibly changed by an electrical pulse applied thereto, the resistive random access memory can operate without a transistor, thus There is an advantage that the scaling of the memory device is easy. In memory devices based on switches and resistive memory materials, the problem of scaling of switches is common in CMOS technology, and in the case of resistive memory materials, they can be designed under the constraint that they must be able to accommodate the supply voltage for programming. have.

Regarding the scaling of the resistive memory material, thermal cross talk between the resistive memory material of adjacent memory cells can be a potential problem. Node designs of 65 nm or less, and even 40 nm or less, must take into account the problem of data loss or malfunction that may occur due to the heat generated in the selected memory cell affecting the state of other adjacent memory cells. do.

SUMMARY OF THE INVENTION The present invention provides a nonvolatile memory capable of securing device reliability such as data retention and durability by suppressing thermal interference between adjacent memory cells in response to high integration of a nonvolatile memory device using a resistive memory film. It is to provide an element.

Another object of the present invention is to provide a method of manufacturing a nonvolatile memory device having the aforementioned advantages.

According to an aspect of the present invention, there is provided a nonvolatile memory device including a substrate and a plurality of memory cells formed on the substrate, wherein each of the plurality of memory cells is adjacent to another lower electrode. And a lower electrode, an upper electrode, and a resistive memory layer between the lower and upper electrodes.

In example embodiments, each of the plurality of memory cells may further include a transistor, and the lower electrode may be electrically connected to any one of a source / drain region of the transistor. In another embodiment, each of the plurality of memory cells further includes a diode, and the lower electrode may be electrically connected to one terminal of the diode.

The nonvolatile memory device may include: a plurality of first conductive lines formed on the substrate; And a plurality of second conductive lines crossing the first plurality of conductive lines to define intersection points. In this case, the plurality of memory cells may be disposed at the intersections, and one of the plurality of first and second conductive lines may be word lines, and the other may be bit lines. In addition, the plurality of memory cells may be arranged in an array of a plurality of rows and a plurality of columns, and the lower electrodes may be alternately different from a first height and a first height in the direction of the plurality of rows and the plurality of columns, respectively. It may have a second height.

The lower electrode may be formed in a hole in the first interlayer insulating layer whose thickness varies for each region where the plurality of memory cells are formed. In this case, an upper surface of the lower electrode may have the same height as an upper surface of the first interlayer insulating layer, and the resistive memory layer may be stacked on the first interlayer insulating layer. In another embodiment, the lower electrodes may be recessed to form grooves in the holes, and the resistive memory layer may be formed to partially or entirely fill the grooves.

The nonvolatile memory device may further include a spacer between at least some of the plurality of memory cells, between the sidewall of the groove and the resistive memory layer.

In an embodiment, the nonvolatile memory device may include: a second interlayer insulating layer formed on the first interlayer insulating layer to cover the upper electrode; And via plugs for electrically connecting the upper electrode and an external circuit through the second interlayer insulating layer, each of the via plugs being adjacent to each of the adjacent memory cells to compensate for a difference in height of the lower electrode of the lower surface. May have different heights.

The nonvolatile memory device may be a phase change random access memory (PRAM) or a resistive random access memory (RRAM).

According to another aspect of the present invention, there is provided a method of manufacturing a nonvolatile memory device, the lower part having a different height from other adjacent lower electrodes in the holes of the first interlayer insulating layer formed on the substrate. Forming an electrode; And forming a resistive memory layer and an upper electrode sequentially stacked on the lower electrode.

The forming of the lower electrode may include forming the first interlayer insulating layer on the substrate; Locally recessing the first interlayer insulating layer such that thicknesses of the adjacent memory cell regions are different from each other; Forming the holes in the locally recessed first interlayer insulating film; Forming a lower electrode material layer to fill the holes on the first interlayer insulating film; And a planarization step of removing the lower electrode material layer until the surface of the first interlayer insulating film is exposed.

In some embodiments, grooves may be defined in the holes by over-etching the lower electrode material layer to recess down the surface of the first interlayer insulating film. In this case, some or all of the resistive memory layer may be filled in the groove.

The forming of the sequentially stacked resistive memory film and the upper electrode may include forming a resistive memory material layer on a first interlayer insulating film; Forming an upper electrode material layer on the resistive memory material layer; And simultaneously patterning the resistive memory material layer and the upper electrode material layer.

In some embodiments, prior to the patterning, forming an etch stop material layer on the upper electrode material layer; Forming an etch stop layer on the upper electrode material layer by the patterning; Forming a second interlayer insulating layer on the first interlayer insulating layer to cover the etch stop layer; Planarizing the second interlayer insulating film; Forming via holes in the planarized second interlayer insulating layer exposing the etch stop layer; Removing the etch stop layer exposed through the via holes; And forming via plugs for connection with an external circuit in the via holes.

According to a nonvolatile memory device according to an embodiment of the present invention, each of a plurality of memory cells has a lower electrode having a different height from that of other adjacent lower electrodes, so that the substrate of the resistive memory layer stacked on the lower electrode. The distance between the adjacent resistive memory films is increased by the position difference in the vertical direction. Accordingly, even if the degree of integration is increased to increase the capacity of the nonvolatile memory device, data loss or malfunction that may be caused by heat transfer between adjacent resistive memory films may be reduced or suppressed.

In addition, according to the manufacturing method of the nonvolatile memory device according to the embodiment of the present invention, there is an advantage that it is possible to easily provide a lower electrode having a height deviation only by controlling the thickness of the interlayer insulating film.

1 is a cross-sectional view illustrating a plurality of memory cells of a nonvolatile memory device according to an embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram of the nonvolatile memory device shown in FIG. 1.
3A and 3B are cross-sectional views illustrating a plurality of memory cells of a nonvolatile memory device according to other embodiments of the present invention.
4A through 4L are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with embodiments of the present invention.
5 is a block diagram schematically illustrating a nonvolatile memory device according to an embodiment of the present invention.
6 is a schematic diagram illustrating a memory card according to an embodiment of the present invention.
7 is a block diagram illustrating an electronic system according to an exemplary embodiment of the present disclosure.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The embodiments of the present invention are described in order to more fully explain the present invention to those skilled in the art, and the following embodiments may be modified into various other forms, It is not limited to the embodiment. Rather, these embodiments are provided so that this disclosure will be more faithful and complete, and will fully convey the scope of the invention to those skilled in the art.

In the drawings like reference numerals refer to like elements. In addition, as used herein, the term "and / or" includes any and all combinations of one or more of the listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the scope of the invention. In addition, although described in the singular in this specification, a plural form may be included unless the singular is clearly indicated in the context. Also, as used herein, the terms "comprise" and / or "comprising" specify the shapes, numbers, steps, actions, members, elements and / or presence of these groups mentioned. It does not exclude the presence or addition of other shapes, numbers, operations, members, elements and / or groups.

In the following, embodiments of the present invention will be described with reference to the drawings schematically showing ideal embodiments of the present invention. In these figures, for example, the size and shape of the members may be exaggerated for convenience and clarity of description, and in actual implementation, variations of the illustrated shape may be expected. Accordingly, embodiments of the present invention should not be construed as limited to the specific shapes of the regions shown herein. Also, reference numerals of members in the drawings refer to the same members throughout the drawings.

As used herein, the term "substrate" refers to a semiconductor layer formed on a base structure, such as silicon, silicon-on-insulator (SOI) or silicon-on-sapphire (SOS), or other base structure other than semiconductor, doped or undoped Semiconductor layer and modified semiconductor layer. Further, the terms base structure and semiconductor are not limited to silicon-based materials, but collectively refer to group III-V semiconductor materials such as carbon, polymer, or silicon-germanium, germanium, and gallium-arsenic compound materials.

In addition, in the present specification, the term "resistive memory material" or "resistive memory film" means that the electrical resistance value is reversibly changed by an electrical signal, and the electrical resistance is not applied even when no external energy is applied to implement a nonvolatile memory operation. It refers to a variable resistive material whose value can remain the same. In addition, in the present specification, the nonvolatile memory device is a concept including a phase change memory or a resistive memory to which the variable resistive material is applied.

1 is a cross-sectional view illustrating a plurality of memory cells MC of a nonvolatile memory device 100 according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of the nonvolatile memory device 100 shown in FIG. 1. to be.

Referring to FIG. 1, the nonvolatile memory device 100 includes a plurality of memory cells MC1 and MC2. These plurality of memory cells MC1 and MC2 include a nonvolatile storage element SE having a resistive memory layer ML. Referring to FIG. 2 together with FIG. 1, similar to a direct random access memory (DRAM), in the nonvolatile memory device 100, the memory film ML may be coupled to a transistor TR that is a switching device. .

The transistor TR may be formed in an active region defined by a field isolation region 11, such as a shallow trench isolation (STI) in the substrate 10. The transistor TR has source / drain regions S / D spaced apart from each other by a gate G and a gate G formed of a gate insulating layer Gox and a gate electrode GE formed on the active region. It may be a field effect transistor (FET). The memory layer ML is electrically connected to a source / drain region S / D (also referred to as a source region) of the transistor TR through a contact pad 20C and another source / drain region of the transistor TR. (S / D; may be referred to as a drain region) may be grounded (GND).

In the field effect transistor, the shape of the channel (e.g., planar, trench type, etc.) or the shape and impurity concentration of the impurity region S / D is equal to the short channel effect and leakage current due to the increase in the degree of integration. It may be appropriately selected for improving the characteristics. In addition, the switching element may be implemented by two or more coupled transistors capable of a non destructive read mode, or may replace the field effect transistor to access a nonvolatile memory element (SE). It may be a nano switching device using a grapheme or a nano phenomenon.

As shown in FIG. 2, the plurality of memory cells MC1 and MC2 including the nonvolatile memory element SE may be arranged in an array of a plurality of rows and a plurality of columns, and each memory The gate G of the transistor TR is electrically coupled to the word lines W / Ln-1, W / Ln .. W / L for addressing the cell MC, and the nonvolatile memory element SE One terminal of) may be electrically coupled to the bit lines B / Ln-1, B / Ln .. B / L through the via plugs 40V1 and 40V2.

The conductive members formed on the substrate 10, that is, the transistor TR, the nonvolatile memory element SE and the wirings GND, B / L, and W / L and contact pads for connection therebetween ( 20c and via plugs 40V1 and 40V2 may be electrically insulated by one or more insulating layers 20, 30 and 40.

1 and 2, the plurality of memory cells MC has a 1T / 1R structure having a transistor TR and a nonvolatile memory element SE, but this is exemplary, and the present invention is thus an example. It is not limited. For example, other cross bar array structures (or also referred to as 0T / 1R structures) that can operate without switching elements, or other known structures in which diodes have been applied as a switching element in place of or in combination with the transistor, are also seen. It can be included in the invention.

The nonvolatile memory element SE may include a lower electrode BE, an upper electrode TE, and a resistive memory layer ML therebetween. By the resistive memory layer ML, the nonvolatile memory element SE implements the nonvolatile operating characteristics required by the memory device.

The resistive memory layer ML may be reversibly switched from an amorphous state to a crystalline state or vice versa, and thus may be a phase change material having different resistance values. The phase change material may be, for example, a chalcogenide compound. The chalcogenide-based compound may include, for example, any one of GeSbTe-based materials, for example, GeSb ₂ Te ₃ , Ge ₂ Sb ₂ Te ₅ , GeSb ₂ Te ₄ , or a combination thereof. This is exemplary and the present invention is not limited thereto. In addition, as the phase change material, GeTeAs, GeSnTe, SeSnTe, GaSeTe, GeTeSnAu, SeSb2, InSe, GeTe, BiSeSb, PdTeGeSn, InSeTiCo, InSbTe, In ₃ SbTe _2, GeTeSb _2, GeTe ₃ Sb, GeSbTePd, a AgInSbTe. In addition, the above-mentioned materials may be further doped with an impurity element, for example, a nonmetallic element such as B, C, N, P.

The aforementioned phase change material generally has high resistance in an amorphous state and low resistance in a crystalline state. The phase change required in the embodiments is not limited to the transition between the fully crystalline state and the completely amorphous state, but between two different states such that a difference can be detected within the entire spectrum of the fully crystalline state and the completely amorphous state. It also includes conversion. In addition, the phase change may occur throughout the resistive memory layer ML or may occur over a part of the resistive memory layer ML.

In another embodiment, the resistive memory film ML may be a perovskite oxide or a transition metal oxide. In the perovskite-based oxide and the transition metal oxide, the switching characteristic of the resistance value according to the electrical pulse also appears. For these switching characteristics, various mechanisms relating to conductive filaments, interfacial effects and trap charges have been proposed to account for resistance changes. To date, these mechanisms are not clear. However, these materials are commonly applied as nonvolatile resistive memory films because they have a factor with some kind of hysterisis that affects the current by electrons in microstructures suitable for nonvolatile memory applications.

There teugye perovskite oxide showing such properties, for example, a SrTiO ₃ or SrZrO _3. In addition, the transition metal oxide film may include, for example, TiO ₂ , NiO, Ta ₂ O ₅ , HfO ₂ , Al ₂ O ₃ , ZrO ₂ , GaO, GdO, MnO, PrCaMnO, Nb ₂ O _5, and ZnO. Can be. In another embodiment, the above materials may be further doped with an impurity element, for example, a nonmetallic element such as B, C, N, P.

The materials described above with respect to the resistive memory film ML are exemplary, and the present invention is not limited thereto. In order to implement an excellent nonvolatile memory device, a material having a high ratio of a resistance value in a low resistance state to a resistance value in a high resistance state and a small driving voltage, and thus having low power consumption, may be a resistive memory layer ML according to example embodiments. ) May be selected.

The electrodes TE and BE for the resistive memory layer ML described above are platinum (Pt), ruthenium (Ru), iridium (Ir), silver (Ag), aluminum (Al), titanium (Ti) and tantalum, respectively. (Ta), tungsten (W), silicon (Si), copper (Cu), nickel (Ni), cobalt (Co), molybdenum (Mo), conductive nitrides thereof (for example, TiN, MoN, etc.) , Conductive oxygen nitride (for example, TiON, etc.) or a combination thereof (for example, TiSiN, TiAlON, etc.), these are merely exemplary and the present invention is not limited thereto. The lower electrode BE and the upper electrode TE may be a suitable material that functions as a barrier layer that prevents a reaction between the contact pads 20C and the via plugs 40V1 and 40V2 and the resistive memory layer ML. .

In connection with the operation of the nonvolatile memory device 100, a programming operation may be performed by switching the resistance states of the resistive memory film ML described above, and bit values "0" and "1" in each resistance state. This can be assigned as recording information. For example, information can be processed by assigning a low resistance state (also commonly referred to as a set state) to a bit value "1", and assigning a high resistance state (also called a reset state) to a bit value "0". However, this is exemplary and one skilled in the art will understand that it is also within the present invention to assign the bit values "1" and "0" in reverse.

When the resistive memory film ML is the above-described phase change material, the lower electrode BE acts as a heater to perform a programming operation. Specifically, when a program current flows through the lower electrode BE, joule heat is generated at an interface between the resistive memory layer ML and the lower electrode BE, and the joule heat causes the resistive memory film ML to be set to a set state. You can switch to the reset state.

On the other hand, when the resistive memory film ML is a perovskite compound or a transition metal compound, a suitable voltage signal is applied between the upper electrode TE and the lower electrode BE, so that the resistive memory film ML is applied. It can induce a reset state and a set state. Specifically, the resistive memory film ML, which has undergone a suitable forming process, becomes a reset state having a high resistance when a reset voltage is applied, and then a voltage higher than the reset voltage, that is, a set voltage, is again applied to the memory film ML in the reset state. Applying can set the low resistance set state. In relation to this characteristic, the resistive memory layer ML may have unipolarity having a set voltage and a reset voltage independent of polarity, or bipolarity having a difference in the set voltage and a reset voltage depending on polarity. Included in the Examples.

As such, when a programming or erase operation occurs in one selected memory cell, the resistance state of the resistive memory film of another memory cell adjacent thereto may be affected. When the resistive memory films ML are a phase change material, the resistive memory film in an adjacent reset state may be converted into a set state by a heat transferred from a programming operation of a selected memory cell so that an unwanted erase operation may be performed. This problem is frequently found in PRAM using phase change materials.

The inventors have observed that even when the resistive memory films ML are perovskite-based compounds or transition metal oxides, the resistance state of adjacent memory cells not selected by this thermal interference can be changed. In this case, thermal interference may cause the set state of an unselected adjacent resistive memory film to be changed to a reset state and vice versa, so that crosstalk appears more complicated than the above-described phase change material.

This thermal interference problem between adjacent memory cells is a significant limitation in manufacturing a nonvolatile memory device using a resistive memory film. The following features relate to suppressing or reducing this thermal interference problem. Referring again to FIG. 1, the positions of the resistive memory film ML of the nonvolatile memory element SE formed on the substrate 10 may be aligned with each other in a direction perpendicular to the substrate 10 for each adjacent memory cells MC. different.

When the memory cells MC are provided in an array structure as illustrated in FIG. 2, the heights of the lower electrodes BE are alternately arranged in a plurality of rows and a plurality of columns, respectively, to form a first height, for example, the height of FIG. 1. It may have a second height different from H1 and the first height, for example a height H2 greater than the height H1. As such, the heights of the lower electrodes BE may be altered with two different values, but the present invention is not limited thereto. For example, the lower electrodes BE may be arranged to have three or more different heights in adjacent memory cells.

Referring to FIG. 1, in the semiconductor memory device 100, the actual distance D of the resistive memory layer ML may be defined by Equation 1 below.

[Formula 1]

D = (L ² + ΔH ² ) ^1/2

Here, L is a horizontal distance between adjacent resistive memory films ML, and ΔH is a difference in height of the lower electrode BE in contact with the resistive memory film ML, that is, H ₁ -H ₂ .

The positional difference in the vertical direction of the resistive memory layer ML with respect to the main surface of the substrate 10 is equal to the height difference ΔH of the lower electrode BE. Accordingly, as the height difference ΔH of the lower electrode BE increases, the position difference in the vertical direction of the resistive memory layer ML increases, and thus the actual distance D between adjacent resistive memory layers ML is increased. ) Can be increased by a relationship such as equation (1).

For example, if the lower electrodes BE are designed to have a constant height difference ΔH, which is equal to the horizontal distance D between the adjacent resistive memory layers ML, the adjacent resistive memory layers ML may be formed. The actual distance D therebetween may be increased by at least 40% compared to the distance when the height difference is zero (in this case, equal to the horizontal distance D).

Conversely, when the degree of integration is doubled to increase the capacity of the nonvolatile memory device 100, the horizontal distance L between adjacent resistive memory films ML may be reduced to 1/2. In this case, however, as in the embodiment, if the lower electrodes BE are designed to have a height difference ΔH equivalent to the size of the reduced horizontal distance L, between adjacent resistive memory films ML The actual distance D is reduced by only 30%. As such, the heat transfer path between the resistive memory films ML adjacent to the lower electrodes BE by the height difference ΔH may be reduced even if the degree of integration is increased.

In addition, considering that the contact interface between the lower electrode BE and the resistive memory layer ML is a direct heat source, even if the contact interface and the programming region of the resistive memory layer ML are in direct contact with each other, the adjacent memory cells MC may be adjacent to each other. The heat sources may be different from each other in a direction perpendicular to the substrate 10, and thus a heat transfer path between adjacent resistive memory layers ML may be substantially increased. As a result, according to the embodiment of the present invention, thermal interference which appears during programming of adjacent resistive memory films ML can be suppressed or reduced.

As shown in the illustrated embodiment, when the lower electrodes BE are electrically separated by the first interlayer insulating layer 30, the first interlayer insulating layer 30 according to the height difference ΔH of the lower electrodes BE. The thickness of may vary for each adjacent memory cell region. 1 illustrates a first interlayer insulating film 30 having a step 30st having a size of ΔH between adjacent memory cells MC1 and MC2.

A second interlayer insulating layer 40 may be further formed on the first interlayer insulating layer 30 to cover the nonvolatile memory element SE including the upper electrode. An upper wiring, for example, a bit line B / L, may be further formed on the second interlayer insulating layer 40 to connect to an external circuit. In this case, the upper wiring B / L and the upper electrode TE of the nonvolatile memory element SE may be electrically connected by via plugs 40V1 and 40V2 passing through the second interlayer insulating layer 40. .

If necessary, the via plugs 40V1 and 40V2 may have different heights for each of the memory cells MC1 and MC2 in order to eliminate low flatness according to the step 30st of the first interlayer insulating layer 30. have. In FIG. 1, in order to compensate for the small height of the lower electrode BE of the memory cell MC1, the via plug 40V1 of the memory cell MC1 is connected to the via plug 40V2 of another adjacent memory cell CM2. It can be designed to have a height greater than the height. Features related to this will be described later in more detail with reference to FIGS. 4J to 4L.

3A and 3B are cross-sectional views illustrating a plurality of memory cells MC1 and MC2 of nonvolatile memory devices 200A and 200B according to other embodiments of the inventive concept. Description of components having the same reference numerals as those of FIGS. 1 and 2 among the illustrated components may refer to the foregoing disclosure unless otherwise indicated, and will be omitted below. .

3A and 3B, unlike the 1T / 1R structure illustrated in FIGS. 1 and 2, the nonvolatile memory devices 200A and 200B may have first wirings intersecting with each other, eg, word lines. It has a crossbar structure having a nonvolatile memory element SE at the intersection defined by (W / L) and the second wiring, for example, bit lines B / L. The first wire and the second wire may be defined as bit lines and word lines, as opposed to the above, and the cross bar structure may be referred to as a cross point structure.

Embodiments of the present invention are not limited by the names, and the first wiring W / L may be a separate conductive metal pattern formed on the substrate, as shown, and an impurity region of the substrate 10. It may be a conductive layer formed by. Since the cross bar structure does not require a transistor, the design of each of the memory cells MC1 and MC2 has an advantage of possible up to 4F ² .

In some embodiments, a diode DI may be disposed between the first wiring W / L and the nonvolatile memory element SE to prevent crosstalk between adjacent memory cells MC1 and MC2. . Alternatively, although not shown, a diode DI may be disposed on the second wiring B / L and the nonvolatile memory element SE. The diode DI may be manufactured through a known epitaxial deposition process and / or an impurity implantation process.

In order to solve the problem of thermal interference due to scaling, even in a cross bar structure, the height of the lower electrode BE is different for each of the adjacent memory cells MC1 and MC2. As a result, a vertical deviation between the resistive memory films ML of the adjacent memory cells MC1 and MC2 may occur so that the actual distance between them may be increased more than the horizontal distance L. FIG.

In some embodiments, together with the features described above, it may be possible to limit the area in which the resistive memory film ML is programmed to be stabilized in the set state and / or the reset state, respectively. This aspect can be equally applied to the 1T / 1R structure shown in FIG. 1. To this end, as shown in FIGS. 3A and 3B, the lower electrode BE is recessed from the surface of the first interlayer insulating layer 30 by a depth d, and thus, is formed in the groove of the first interlayer insulating layer 30 formed thereby. The resistive memory layer ML may be filled.

In the element 200A of FIG. 3A, only a part of the resistive memory film ML contacts the lower electrode BE while filling the groove, and in the element 200B of FIG. 3B, the entirety of the resistive memory film ML is not shown. Fill the grooves. In order to obtain such a structure, the resistive memory layer ML may be formed by a chemical vapor deposition or an atomic layer deposition process, which is a deposition process having excellent step coverage.

Alternatively, as shown in FIG. 3A, a spacer 30sp may be further formed on the sidewall of the groove of the first interlayer insulating film 30. The spacer 30sp may be obtained through an etch back process after depositing a suitable layer of spacer material. The spacer material layer may be an electrical insulator and / or an insulator. In this case, the spacer 30sp may serve as a heat insulating structure for the portion of the resistive memory film ML to be programmed.

In addition, the spacer 30sp may serve to limit the programmed region of the resistive memory film ML to a threshold value of or less than a photolithography process. In particular, in the case where the resistive memory film ML is a phase change material, the spacer 30sp is driven by reducing the contact area between the resistive memory film ML and the lower electrode BE to improve the effective current density of the program current. The devices can be miniaturized and thus the degree of integration can be further improved.

In some embodiments, the spacer 30sp may be alternately applied to each of the adjacent memory cells MC1 and MC2 to compensate for the resistance value according to the height difference of the lower electrode BE. For example, the lower electrode BE of the memory cell MC1 may have a smaller resistance value than the lower electrode BE of another adjacent memory cell MC2. In this case, in order to increase the resistance value of the memory cell MC1 having a relatively low resistance value, the spacer 30sp is formed only in the memory cell MC1 and the spacer 30sp is formed in the other memory cell MC2. As a result, the resistance unevenness due to the height deviation of the lower electrode BE may be solved.

In some embodiments, in order to make the resistance of the lower electrodes BE of the memory cells MC1 and MC2 uniform with or in place of the spacer 30sp described above, The widths W1 and W2, or the cross-sectional areas thereby, may be designed differently. For example, the width W1 of the lower electrode BE having the small height of the memory cell MC1 is designed to be smaller than the width W2 of the lower electrode BE having the large height of the memory cell MC2. The resistance value of the lower electrode BE of all the memory cells MC1 and MC2 may be uniform. In some embodiments, the cross-sectional area difference between adjacent lower electrodes BE may be proportional to their height difference so as to have a constant resistance value.

3A illustrates that the upper structure including the second interlayer insulating layer 40 and the upper wiring BL has a low flatness due to the height difference between the lower electrodes BE. If necessary, as illustrated in FIG. 3B, via plugs 40V1 and 40V2 having different heights may be applied to planarize the upper structure. The formation method thereof will be described later.

Hereinafter, methods of manufacturing a nonvolatile memory device having the above-described features and advantages are disclosed. 4A through 4L are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with embodiments of the present invention.

Referring to FIG. 4A, before forming the lower electrode BE having a different height, first, an isolation region 11 is formed in the substrate 10 to define an active region. A lower structure may be formed in the active region including switching elements such as MOS field effect transistors (TR), contact pads 20C for connecting to an external circuit, and an insulating layer for insulating them. Although not shown, the cross bar structure without the switching element also forms a lower structure including the wiring W / L and / or the diode DI on the substrate 10 as described with reference to FIG. 3A.

Referring to FIG. 4B, a first interlayer insulating film 30 is formed on the insulating film 20. The first interlayer insulating film 30 may be an insulating film formed by a chemical vapor deposition process, a plasma enhanced chemical vapor deposition, or a silicon on glass (SOG) process. Subsequently, a mask pattern, for example, a photoresist film PR, is formed on the insulating film 20 to selectively expose only the memory cell region (MC1 of FIG. 1) in which the lower electrode having a small height is to be formed. Thereafter, by partially etching the exposed insulating film surface by using a known etching process, the first interlayer insulating film 30 may be locally recessed to have thickness variations H1 and H2 in adjacent memory cell regions. have.

Referring to FIG. 4C, holes (not shown) are formed in the first interlayer insulating layer 30 to expose the contact pads 20C. Subsequently, a lower electrode material layer (not shown) suitable to fill the holes is formed on the first interlayer insulating film 30, and the etch back or chemical mechanical polishing is performed until the surface of the first interlayer insulating film 30 is exposed. The same planarization process may be performed to form lower electrodes BE embedded in the holes, respectively.

Referring to FIG. 4D, in some embodiments, the embedded lower electrode material layer is over-etched using the etching selectivity of the first interlayer insulating layer 30 and the lower electrode BE to recess the predetermined depth d. The lower electrode BE may be formed. The recess process may be achieved by an etch back process. The groove G1 is defined in the first interlayer insulating layer 30 by the recessed lower electrodes BE.

The method of manufacturing the recessed lower electrode BE may also be applied to the lower electrode BE of the cross bar structure illustrated in FIGS. 3A and 3B, and subsequent processes related thereto will be described with reference to FIGS. 4G and 4H. will be.

Referring to FIG. 4C and to FIG. 4E, the lower electrodes BE and the lower electrodes BE are formed on the substrate 10 on which the lower electrodes BE having different heights are formed in the holes of the first interlayer insulating film 30. A resistive memory material layer ML 'is formed in contact with each other. Subsequently, an upper electrode material layer TE 'may be further formed on the resistive memory material layer ML'. Any one or both of these layers ML ', TE' may be formed by a chemical vapor deposition, physical vapor deposition or atomic layer deposition process, the present invention is not limited thereto.

In some embodiments, an etch stop material layer ES 'may be further formed on the upper electrode material layer TE' to provide a flattened final top structure as shown in FIG. 1. As the etch stop material layer ES ', a material having an excellent etching selectivity with the second interlayer insulating film 40 which will be described later, and having an etching selectivity with the upper electrode material layer TE' of the underlying material may be selected. have.

Thereafter, as shown in FIG. 4F, the layers ML ′, TE ′, and ES ′ may be simultaneously patterned to form nonvolatile memory elements SE electrically separated from each other and electrically connected to the lower electrode BE, respectively. have. As illustrated in FIG. 4E, when the etch stop material layer ES 'is further formed, the etch stop layer ES may cover the nonvolatile memory elements SE, respectively.

As another example, as described with reference to FIG. 4D, when the lower electrode BE is recessed, the nonvolatile memory elements SE may be manufactured as follows. Referring to FIG. 4G, the resistive memory material layer ML ′ fills the groove G1 on the resultant of FIG. 4D, that is, on the first interlayer insulating layer 30 on which the recessed lower electrodes BE are formed. The upper electrode material layer TE 'is formed on the resistive memory material layer M1'. In some embodiments, the spacer 30sp may be further formed on the sidewall of the groove G1 before forming the resistive memory material layer ML '. By using the insulating spacer 30sp, it is possible to define the contact area between the lower electrode BE and the resistive memory film ML below the critical dimension CD of the photolithography process.

Subsequently, when the upper electrode material layer TE 'and the resistive memory layer ML' are sequentially etched and patterned through a photolithography process and an etching process, the upper electrode TE and the resistive memory as shown in FIG. 3A are patterned. You can get a stack of membranes (ML).

As another embodiment, referring to FIG. 4H, similar to FIG. 4G, the groove G1 is formed on the resultant of FIG. 4D, that is, the first interlayer insulating layer 30 on which the recessed lower electrodes BE are formed. The resistive memory material layer ML 'is formed to fill. Thereafter, as shown in FIG. 4I, an etch back process is performed until the surface of the first interlayer insulating film 30 is exposed so that the resistive memory material layer ML 'remains only in the groove G1, thereby resisting the resistive memory film. (ML) can be formed. On this result, the upper electrode material layer TE 'is formed and, by the photolithography process and the etching process, a nonvolatile memory element SE having a resistive memory film ML defined only in the hole as shown in FIG. 3B. ) Can be obtained.

As described above, after forming the nonvolatile memory element SE including the lower electrode BE, the resistive memory layer ML, and the upper electrode ML having various structures, forming an upper wiring such as a bit line. Subsequent processes can be performed.

Referring to FIG. 4J, a second interlayer insulating material layer 40 ′ covering the nonvolatile memory elements SE is formed on the first interlayer insulating layer 30. The second interlayer insulating material layer 40 ′ may have a non-uniform surface for each region of the adjacent memory cells MC1 and MC2 because of the lower electrodes BE having different heights.

In some embodiments, as shown in FIG. 4K, a planarization process, such as chemical mechanical polishing (CMP), is performed to a depth indicated by the dotted line PL in FIG. 4J, so that the second interlayer insulating film 40 having a uniform surface. ) May be formed.

 Referring to FIG. 4L, via plugs are formed in the second interlayer insulating film 40 to electrically connect the memory cells MC1 and MC2 to the upper wiring, for example, the bit lines B / L of FIG. 1. Via holes G2 are formed in the second interlayer insulating film 40. The via holes G2 may be formed by a photolithography process and an etching process using an etching selectivity between the second interlayer insulating film 40 and the etch stop layer ES.

Subsequently, after removing a portion of the etch stop layer ES exposed through the via holes G2, a conductive material layer suitable to fill the via holes G2 is formed on the second interlayer insulating film 40, and the second The planarization process such as etch back or chemical mechanical polishing may be performed until the surface of the interlayer insulating layer 40 is exposed, thereby forming via plugs 40V1 and 40V2 embedded in the via holes G2. . Subsequently, when the bit line B / L is formed on the second interlayer insulating layer 40, a nonvolatile memory device as shown in FIG. 1 may be manufactured.

Alternatively, via plugs 40V1 and 40V2 and bit lines B / L may be formed in a single process by the same material. For example, a conductive material layer suitable for filling the via holes G2 may be formed on the second interlayer insulating film 40, and a bit line patterning process may be performed.

Although the above-described manufacturing method mainly describes the 1T / 1R structure, those skilled in the art can understand that the above-described manufacturing method may be applied to the cross bar structure as shown in FIGS. 3A and 3B.

5 is a block diagram schematically illustrating a nonvolatile memory device 300 according to an embodiment of the present invention.

Referring to FIG. 5, the nonvolatile memory device 300 may include a memory cell array 310, a row driver 320, a row decoder 330, an auxiliary decoder 340, a column decoder 350, and a sense amplifier / write driver. 360 may be included.

The memory cell array 310 may include a plurality of word lines, a plurality of bit lines, and a plurality of memory cells described above disposed at intersections of the plurality of word lines and the plurality of bit lines. In some embodiments, the plurality of word lines may include a plurality of main word lines and a plurality of sub word lines.

The row driver 320 may generate a driving voltage V _D which is a voltage applied to the plurality of word lines of the memory cell array 310. The row decoder 330 may decode a predetermined bit value of the row address X_ADD into a first address signal corresponding to the plurality of main word lines to activate at least one main word line. The auxiliary decoder 340 may decode the remaining bit values of the row address X_ADD into second address signals corresponding to the plurality of sub word lines to activate at least one sub word line. Here, the main word line may be a global word line, and the sub word line may be a local word line. In another embodiment, the semiconductor device 300 may not include the auxiliary decoder 340, and the row decoder 330 may decode the row address X_ADD into address signals corresponding to the plurality of word lines. .

The column decoder 350 may select at least one corresponding bit line by decoding the column address Y_ADD. The sense amplifier / write driver 360 may receive data of the memory cells to perform a read operation on the memory cells included in the memory cell array 310, or may perform a write operation on the memory cells. A voltage suitable for the plurality of bit lines of 310 may be provided.

6 is a schematic diagram illustrating a memory card 400 according to an embodiment of the present invention.

Referring to FIG. 6, the memory card 400 may include a controller 410 and a memory unit 420 in the housing 430, and the controller 410 and the memory unit 420 may exchange electrical signals. Can be. For example, according to a command of the controller 410, the memory unit 420 and the controller 410 may exchange data. Accordingly, the memory card 400 may store data in the memory unit 420 or output data from the memory unit 420 to the outside.

For example, the memory unit 420 may include the nonvolatile memory device disclosed with reference to FIGS. 1 to 5. The memory card 400 may be used as a data storage medium of various portable devices. For example, the memory card 400 may be standardized as a multimedia card (MMC) or a secure digital (SD) card.

7 is a block diagram illustrating an electronic system 500 according to an embodiment of the present invention.

Referring to FIG. 7, the electronic system 500 may include a processor 510, a memory unit 520, and an input / output device 530, which communicate data with each other using a bus 540. can do. The processor 510 may execute a program and control the system 500. The input / output device 530 may be used to input or output data of the system 500. The system 500 may be connected to an external device, for example, a personal computer or a network, using the input / output device 530 to exchange data with the external device. The memory unit 520 may store code and data for the operation of the processor 510. The memory unit 520 may include the aforementioned nonvolatile memory device.

The electronic system 500 may configure various electronic control devices that require a memory. For example, electronic system 500 may be a microcontroller, mobile phone, multimedia data player, navigation device, storage device such as a solid state drive (SSD), or various household appliances. It may be an electronic system such as.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It will be clear to those who have knowledge.

100, 200A, 200B,: nonvolatile memory device
MC1, MC2, MC: Memory Cell SE: Nonvolatile Memory Element
ML: resistive memory film TE: upper electrode
BE: lower electrode TR: transistor
30, 40: interlayer insulating film 40V1, 40V2: via plugs
W / L, B / L: Bit Line

Claims (19)

A nonvolatile memory device comprising a substrate and a plurality of memory cells formed on the substrate.
Each of the plurality of memory cells,
A first interlayer insulating layer having a different thickness for each of the adjacent memory cell regions in which the plurality of memory cells are formed;
A lower electrode defined in the hole in the first interlayer insulating layer and having a different height from other adjacent lower electrodes;
A resistive memory film on the lower electrode; And
An upper electrode on the resistive memory layer;
A first lower electrode having a smaller height in the lower electrodes of the plurality of memory cells has a width smaller than that of another second lower electrode having a large height, or between the first lower electrode and the resistive memory layer. The contact area of the non-volatile memory device having a smaller contact area between the second lower electrode and the resistive memory layer, so that the difference in resistance value according to the height difference of the lower electrodes is compensated. The method of claim 1,
And a position in which the contact interface between the lower electrode and the resistive memory layer is adjacent to the memory cell in a direction perpendicular to the substrate according to the height difference of the lower electrode. The method of claim 1,
Each of the plurality of memory cells further comprises a transistor,
And the lower electrode is electrically connected to any one of a source / drain region of the transistor. The method of claim 1,
Each of the plurality of memory cells further comprises a diode,
And the lower electrode is electrically connected to one terminal of the diode. The method of claim 1,
A plurality of first conductive lines formed on the substrate; And
Further comprising a plurality of second conductive lines crossing each of the plurality of first conductive lines and defining intersections,
The plurality of memory cells are respectively disposed at the intersections,
Wherein one of the plurality of first and second conductive lines is a word line and the other is a bit line. The method of claim 1,
The plurality of memory cells are arranged in an array of a plurality of rows and a plurality of columns,
And the lower electrodes alternately have a first height and a second height different from the first height in alternating directions of the plurality of rows and the plurality of columns, respectively. delete The method of claim 1,
The upper surface of the lower electrode has the same height as the upper surface of the first interlayer insulating film,
And the resistive memory film is stacked on the first interlayer insulating film. The method of claim 1,
The lower electrodes are recessed to form a groove in the hole,
And the resistive memory layer is partially or entirely filled in the groove. The method of claim 9,
A spacer may be formed between the sidewall of the groove and the resistive memory layer only on the first lower electrode of the plurality of memory cells, thereby reducing the contact area between the first lower electrode and the resistive memory layer. And less than the contact area between the electrode and the resistive memory film. The memory device of claim 1, wherein the nonvolatile memory device comprises:
A second interlayer insulating film formed on the first interlayer insulating film to cover the upper electrode; And
Via plugs for electrically connecting the upper electrode and an external circuit through the second interlayer insulating film,
Each of the via plugs has a different height for each of the adjacent memory cells to compensate for a difference in height of the lower electrode of the lower surface. The method of claim 1,
The nonvolatile memory device is a phase change random access memory (PRAM) or a resistive random access memory (RRAM). Forming a first interlayer insulating film on the substrate;
Locally recessing the first interlayer insulating layer such that thicknesses of adjacent memory cell regions are different from each other;
Forming holes in the first interlayer insulating film;
Forming a lower electrode material layer to fill the holes on the first interlayer insulating film;
Planarization to remove the lower electrode material layer until the surface of the first interlayer insulating film is exposed to form lower electrodes in the holes; And
Forming a resistive memory film and an upper electrode sequentially on the lower electrode,
Forming the holes such that the width of the first hole in the locally recessed memory cell region is smaller than the width of the second hole in the memory cell region that is not locally recessed, or locally recessed among the lower electrodes. The contact area between the first lower electrode in the memory cell region and the resistive memory film is smaller than the contact area between the resistive memory film and the second lower electrode in the memory cell region that is not locally recessed. A method of manufacturing a nonvolatile memory device, in which a difference in resistance due to a height difference is compensated for. delete The method of claim 13,
Over-etching the lower electrode material layer to recess below the surface of the first interlayer insulating film to define a groove in the holes. The method of claim 15,
A portion or all of the resistive memory film is filled in the groove,
A spacer may be selectively formed between the sidewall of the groove and the resistive memory layer only on the first lower electrode, thereby forming a contact area between the first lower electrode and the resistive memory layer. A method of manufacturing a nonvolatile memory device, characterized in that it is less than the contact area between. The method of claim 13,
In the forming of the resistive memory layer and the upper electrode in sequence,
Forming a resistive memory material layer over said first interlayer insulating film;
Forming an upper electrode material layer on the resistive memory material layer; And
And simultaneously patterning the resistive memory material layer and the upper electrode material layer. The method of claim 17,
Prior to the patterning, forming an etch stop material layer on the top electrode material layer;
Forming an etch stop layer on the upper electrode material layer by the patterning;
Forming a second interlayer insulating layer on the first interlayer insulating layer to cover the etch stop layer;
Planarizing the second interlayer insulating film;
Forming via holes in the planarized second interlayer insulating layer exposing the etch stop layer;
Removing the etch stop layer exposed through the via holes; And
Forming via plugs for connection with an external circuit in the via holes. The method of claim 18,
The nonvolatile memory device may be a phase change random access memory (PRAM) or a resistive random access memory (RRAM).

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