CN205911311U - Slot power device - Google Patents
Slot power device Download PDFInfo
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- CN205911311U CN205911311U CN201620738421.9U CN201620738421U CN205911311U CN 205911311 U CN205911311 U CN 205911311U CN 201620738421 U CN201620738421 U CN 201620738421U CN 205911311 U CN205911311 U CN 205911311U
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Abstract
The utility model discloses a slot power device. The utility model provides a pair of slot power device is through forming first slot in semiconductor substrate to with first prevention layer, filler material layer set up in in the first slot, and form the static isolation structure in the filler material layer of first slot, and then realized that the static isolation structure sets up in semiconductor substrate, avoided the static isolation structure to be higher than the second slot, the condition of third slot, make semiconductor substrate level, the effective solution because uneven subsequent deposit technology step covering power of messenger of traditional static isolation structure is not good, especially the photoetching appearance is even glues harmfully, the exposure is unusual, step department photosensitive resist is thin partially unable effective in the etching stopper scheduling problem, thereby realize device structure, make parameter and reliability satisfy the requirement of product.
Description
Technical field
This utility model is related to field of semiconductor devices, more particularly to a kind of groove power device.
Background technology
In semiconductor technology, power discrete device includes the devices such as power mosfet, high power transistor and igbt.In early days
Power device is all based on planar technology and produces, but the development with semiconductor technology, small size, high-power, high-performance one-tenth
The trend of quasiconductor development.Trench process, due to raceway groove is become vertical from level, eliminates planar structure parasitism jfet resistance
Impact, so that cellular size is substantially reduced, on this basis increase primitive unit cell density, improve unit area chip in raceway groove beam overall
Degree it is possible to channel width-over-length ratio on unit silicon chip for the device is increased so that electric current increase, conducting resistance decline and
Relevant parameter is optimized it is achieved that smaller size of tube core has more high-power and high performance target, therefore trench process
Get more and more and apply in New Type Power Devices.
Static discharge (electro static discharge, esd) is a kind of rapid electric charge between two objects
Transfer phenomena, is accompanied by very big electric field intensity and electric current density, if this energy can not effectively be discharged in this phenomenon, it will
Lead to device gate dielectric layer to puncture, or even so that silicon substrate and dielectric layer is punctured, burn out.At present in circuit product, most
Electrostatic isolation structure in integrated circuit is all realized by doped silicon in a silicon substrate, and this will take certain silicon chip face
Long-pending, but for device products, typically realize electrostatic isolation structure it becomes possible to save certain in polysilicon layer (solid space)
Area, thus cost-effective.But the electrostatic isolation structure realized using polysilicon, there is also a variety of drawbacks.It is illustrated in figure 1
Tradition has the trench power device structure schematic diagram of electrostatic protection function, and whole device can be divided into esd region, gate trace area
Domain and primitive unit cell region.Wherein, in esd region, electrostatic isolation structure 3 is exactly to realize esd using the multigroup p/n of polysilicon doping is alternate
Defencive function.Because electrostatic isolation structure 3 will have very big electric field intensity and electric current density it is therefore desirable to by electrostatic isolation
Structure 3 and bulk silicon substrate 1 are effectively isolated out, and therefore need thicker dielectric layer 2 to isolate below electrostatic isolation structure, thick
Degree h1 typically requires and is more thanSimultaneously as polysilicon needs thickness h 2 to be typically larger than in itselfTherefore can deposit
In about 1 μm even greater than 1 μm of step difference, this uneven structure can make the technique step of follow-up metallization medium layer 4
Cover not good, particularly spin coating bad for photoetching, and exposure is abnormal, and at step, photoresist is partially thin cannot be effectively as etch stopper
Layer, makes device architecture cannot realize, and so that the parameter of product and reliable sexual satisfaction is required.
How to pass through the step difference optimized product structure, technological process reduction is produced due to electrostatic isolation structure, make whole
Semiconductor substrate surface is flat, and effectively solving makes follow-up depositing operation step due to the unevennessization of conventional electrostatic isolation structure
Covering power is not good, and particularly spin coating bad for photoetching, and exposure is abnormal, and at step, photoresist is partially thin cannot be effectively as etching
The problems such as barrier layer, thus realizing device architecture, making parameter and the requirement of reliable sexual satisfaction product, being those skilled in the art institute
Content to be studied.
Utility model content
The purpose of this utility model is to provide a kind of groove power device, solves due to conventional electrostatic isolation structure
Semiconductor substrate surface uneven and affect follow-up depositing operation Step Coverage ability, spin coating not in particularly photoetching
Good, exposure is abnormal, at step photoresist partially thin cannot effectively as etching barrier layer the problems such as.
For solving above-mentioned technical problem, this utility model provides a kind of groove power device, comprising:
Semiconductor substrate；
First groove, second groove and the 3rd groove in described Semiconductor substrate；
Positioned at the semiconductor substrate surface of described first groove region and the diapire of described first groove and side wall
First trapping layer；
Semiconductor substrate surface positioned at described second groove and the 3rd groove region and second groove and the 3rd ditch
Gate dielectric layer on the diapire of groove and side wall；
Encapsulant layer in first groove, second groove and the 3rd groove, and described gate dielectric layer, the first prevention
Layer and the upper surface flush of encapsulant layer；
The first doped region in the encapsulant layer in described first groove and the second doped region, described first doping
Area and the second doped region are spaced apart, collectively as electrostatic isolation structure；
The p trap of first groove, second groove and the 3rd groove both sides in described Semiconductor substrate；
N-type area on first groove, second groove and p trap described in the 3rd groove both sides in described Semiconductor substrate；
Dielectric layer in described Semiconductor substrate；
Contact hole, described contact hole runs through described dielectric layer and extends respectively to the filling material of first groove and second groove
In the bed of material and in the p trap of the 3rd groove side；And
P-type area positioned at described contact hole bottom.
Optionally, for described groove power device, the depth of described first groove is 1 μm -3.5 μm, and width is 1 μ
M-10 μm, the depth of described second groove is 1 μm -3.5 μm, and width is 0.5 μm -2 μm, the depth of described 3rd groove is 1 μm -
3.5 μm, width is 0.1 μm -0.6 μm.
Optionally, for described groove power device, described first trapping layer is silicon dioxide trapping layer, silicon nitride resistance
Only one or more combination of layer, silicon oxynitride trapping layer.
Optionally, for described groove power device, the thickness of described first trapping layer is
Optionally, for described groove power device, the thickness of described encapsulant layer is 0.3 μm -1 μm.
Optionally, for described groove power device, described first doped region and the second doped region penetrate described first
Encapsulant layer in groove.
Optionally, for described groove power device, described dielectric layer is silica dioxide medium layer, silicon nitride medium
Layer, one or more combination of silicon oxynitride dielectric layer, polycrystalline silicon medium layer.
Optionally, for described groove power device, the depth that described contact hole is located in described Semiconductor substrate is
0.1μm-0.8μm.
Optionally, for described groove power device, also include:
Metal level in described Semiconductor substrate, described metal level fills described contact hole；And
Passivation layer on described metal level.
Compared with prior art, a kind of groove power device that this utility model provides, by shape in the semiconductor substrate
Become first groove, and the first trapping layer, encapsulant layer are arranged in described first groove, and the filling material in first groove
Form electrostatic isolation structure in the bed of material, and then achieve electrostatic isolation structure setting in the semiconductor substrate, it is to avoid electrostatic every
From structure be higher than second groove, the 3rd groove situation so that semiconductor substrate surface is smooth, effectively solving is due to conventional electrostatic
The unevenness of isolation structure makes follow-up depositing operation Step Coverage ability not good, particularly photoetching bad, the exposure that spin coating
Abnormal, at step photoresist partially thin cannot effectively as etching barrier layer the problems such as, thus realizing device architecture, make parameter and can
Requirement by sexual satisfaction product.
Brief description
Fig. 1 is the structural representation of groove power device in prior art；
Fig. 2 is the flow chart of the groove power device manufacture method in this utility model one embodiment；
Fig. 3-12 is that the structure in the manufacturing process of groove power device in this utility model embodiment one embodiment is shown
It is intended to.
Specific embodiment
Below in conjunction with schematic diagram, groove power device of the present utility model and manufacture method are described in more detail,
Which show preferred embodiment of the present utility model it should be appreciated that those skilled in the art can change described here reality
With new, and still realize advantageous effects of the present utility model.Therefore, description below is appreciated that for art technology
Personnel's is widely known, and is not intended as to restriction of the present utility model.
Referring to the drawings this utility model more particularly described below by way of example in the following passage.According to following explanation and power
Sharp claim, advantages and features of the present utility model will become apparent from.It should be noted that, accompanying drawing all in the form of very simplification and
All using non-accurately ratio, only in order to purpose that is convenient, lucidly aiding in illustrating this utility model embodiment.
This utility model provides a kind of groove power device and manufacture method, the manufacture method bag of described groove power device
Include:
Step s11, offer Semiconductor substrate；
Step s12, form first groove, second groove and the 3rd groove in described Semiconductor substrate；
The diapire of step s13, the semiconductor substrate surface in described first groove region and described first groove and
First trapping layer is formed on the wall of side；
Step s14, the semiconductor substrate surface in described second groove and the 3rd groove region and second groove and
Gate dielectric layer is grown on the diapire of the 3rd groove and side wall；
Step s15, formation encapsulant layer simultaneously fill completely described first groove, second groove and the 3rd groove；
Step s16, planarized so that described semiconductor substrate surface expose gate dielectric layer, the first trapping layer and
Encapsulant layer, and the upper surface flush of described gate dielectric layer, the first trapping layer and encapsulant layer；
Step s17, in described Semiconductor substrate, first groove, second groove and the 3rd groove both sides form p trap；
Shape in step s18, first groove, second groove and p trap described in the 3rd groove both sides in described Semiconductor substrate
Become n-type area, the encapsulant layer in described first groove forms the first doped region；
Step s19, form the second doped region in the encapsulant layer in described first groove, described first doped region and
Second doped region is spaced apart, forms electrostatic isolation structure；
Step s20, on the semiconductor substrate formation dielectric layer；
, to form contact hole, described contact hole extends respectively to first groove and second for step s21, the described dielectric layer of etching
In the encapsulant layer of groove and in the p trap of the 3rd groove side；And
Step s22, described contact hole bottom formed p-type area.
Incorporated by reference to Fig. 2 and Fig. 3-12, groove power device of the present utility model and manufacture method are situated between in detail below
Continue.Wherein Fig. 2 is the flow chart of the groove power device manufacture method in this utility model one embodiment；Fig. 3-12 is this practicality
The structural representation in the manufacturing process of groove power device in new embodiment one embodiment.
First, execution step s11, as shown in figure 3, provide Semiconductor substrate 10.Described Semiconductor substrate 10 can be silicon
Substrate, germanium silicon substrate ,-group element compound substrate or well known to a person skilled in the art other semiconductive material substrate,
Silicon substrate is used in the present embodiment.More specifically, the silicon substrate adopting in the present embodiment could be formed with mos field effect crystalline substance
The semiconductor device such as body pipe, igbt isolated-gate field effect transistor (IGFET), Schottky.
Specifically, in this step s11, the described Semiconductor substrate with specific doping type, refer to according to product
The N-shaped of property doped certain impurity level and p-type semiconductor substrate.
Then, execution step s12, forms first groove 11a, second groove 11b and the in described Semiconductor substrate 10
Three groove 11c.Please continue to refer to Fig. 3, can be to adopt dry etching to etch silicon in described Semiconductor substrate 10, obtain described
First groove 11a, second groove 11b and the 3rd groove 11c.The depth of described first groove 11a is 1 μm -3.5 μm, and width is 1
μm -10 μm, the depth of described second groove 11b is 1 μm -3.5 μm, and width is 0.5 μm -2 μm, the depth of described 3rd groove 11c
Spend for 1 μm -3.5 μm, width is 0.1 μm -0.6 μm.In this utility model, the described first groove 11a purpose of formation be for
By electrostatic isolation structure fabrication afterwards in this first groove 11a, and described first groove 11a region is esd area,
Accordingly, described second groove 11b region is grid lead area, and described 3rd groove 11c region is primitive unit cell area.
Then, execution step s13, refer to Fig. 4, in Semiconductor substrate 10 table of described first groove 11a region
First trapping layer 11 is formed on the diapire of face and described first groove 11a and side wall.In this utility model embodiment, described
The material of one trapping layer 11 is the material such as silicon dioxide, silicon nitride, silicon oxynitride, or is described silicon oxide, silicon nitride, nitrogen oxidation
Silicon, etc. one or more of material combination.
Specifically, in this step s13, described in the present embodiment, the material of the first trapping layer 11 is chosen as silicon oxide, thickness
ForFor exampleDeng.In this step pass through formed the first trapping layer 11 it is achieved that
The isolation of electrostatic isolation structure and substrate, and pass through further to adjust the thickness of the first trapping layer 11, it is to avoid packing material
Layer is blocked up, optimizes the ion implantation process of electrostatic isolation structure.
Specifically, this step s13 includes: step s131, refer to Fig. 4, forms first in described Semiconductor substrate 10
Trapping layer 11.
Step s132, etches described first trapping layer 11, removes the quasiconductor outside described first groove 11a region
First trapping layer 11 on substrate 10 surface, only retains diapire and the side that described first trapping layer 11 covers described first groove 11a
The part of wall and the portion of described first trapping layer 11 described first groove 11a region in described Semiconductor substrate 10
Point.Can be the diluter boe corrosive liquid adopting in the present embodiment completing.
Then, carry out step s133, carry out high temperature reparation.Preferably, executing height in 1000 DEG C of -1200 DEG C of temperature ranges
Warm sacrificial oxidation, the diapire to described second groove 11b and the 3rd groove 11c and side wall carry out high temperature reparation, produce aboutFirst oxide layer of thickness, then removes described first oxide layer using diluter boe corrosive liquid rinsing.
Then execution step s14, please continue to refer to Fig. 4, in described second groove 11b and the 3rd groove 11c region
Semiconductor substrate 10 surface and the diapire of second groove 11b and the 3rd groove 11c and side wall on grow gate dielectric layer 12.Described
The growth of gate dielectric layer 12 can be using mixing oxychloride to complete, and temperature range is 1000 DEG C -1200 DEG C, described gate dielectric layer 12
Thickness range bePreferably, when the thickness of gate dielectric layer 12 isWhen, can be used as follow-up
The masking layer of injection use (thickness relationship of gate dielectric layer 12 to vth the multiple parameters such as qg, its thickness according to product attribute Lai
Fixed, therefore those skilled in the art can be according to the thickness being actually needed setting gate dielectric layer 12).
Then, execution step s15, refer to Fig. 5, formed encapsulant layer 13 and fill completely described first groove 11a, the
Two groove 11b and the 3rd groove 11c.Preferably, the material of described encapsulant layer 13 is chosen as the polysilicon that undopes, that is, do not mix
Miscellaneous any p or p-type impurity polysilicon.This step primary concern is that because electrostatic isolation structure needs by isolation material
More accurately regional injection is carried out on the bed of material 13, realizes esd isolation features, if there is doping during deposition, after
There is larger uncertainty in the continuous p-type of adjustment electrostatic isolation structure and the concentration of N-shaped, the function of electrostatic isolation structure can be produced
Raw impact.
Specifically, in step s15, the polycrystalline that undopes of described deposition, to bear esd pressure due to needing to have for its thickness
Releasability, it usually needs be thicker thanSuch as 0.3 μm -1 μm.
Then, refer to Fig. 6, execution step s151, form the second trapping layer 14, described second trapping layer 14 covers first
The encapsulant layer 13 of groove 11a region, exposes second groove 11b and the 3rd groove 11c region.
Specifically, can be first the second trapping layer 14 to be formed on whole Semiconductor substrate 10, then carry out chemical wet etching
The second trapping layer outside removal first groove 11a region.
Optionally, the material of described second trapping layer 14 is the material such as silicon dioxide, silicon nitride, silicon oxynitride, or for institute
State silicon oxide, silicon nitride, silicon oxynitride, etc. one or more of material combination.Specifically, the second trapping layer described in the present embodiment
14 material is silicon oxide, and thickness is
Afterwards, execution step s152, is carried out to the encapsulant layer 13 in described second groove 11b and the 3rd groove 11c
Doping.Specifically, can be to be doped by the way of phosphorus pre-deposition.The second trapping layer 14 retaining then plays and prevents first
Encapsulant layer 13 in groove 11a is not doped to.
Afterwards, execution step s16, refer to Fig. 7, is planarized, so that described Semiconductor substrate 10 surface exposure
Go out gate dielectric layer 12, the first trapping layer 11 and encapsulant layer 13, and described gate dielectric layer 12, the first trapping layer 11 and filling material
The bed of material 13 upper surface flush.Specifically, this step includes removing the second trapping layer on described Semiconductor substrate 10 surface successively
14th, encapsulant layer 13, part the first trapping layer 11, makes Semiconductor substrate 10 surface exposure go out gate dielectric layer 12, first and stops
Layer 11 and encapsulant layer 13, and described gate dielectric layer 12, the first trapping layer 11 and encapsulant layer 13 upper surface flush.
The removal of described second trapping layer 14 generally can be carried out using wet processing.
The removal of described encapsulant layer 13 generally can adopt chemical mechanical milling tech (cmp), it would however also be possible to employ returns
Carving technology, makes the gate dielectric layer 12 on encapsulant layer 13 and Semiconductor substrate 10 surface in groove flush.
And it is possible to first the encapsulant layer of first groove 11a region is ground to and the first resistance using cmp technique
Only layer 11 flushes, then the first trapping layer 11 that dry etching exposes, to the thickness of gate dielectric layer 12, then uses cmp technique to incite somebody to action again
The encapsulant layer 13 of first groove 11a protrusions is ground to gate dielectric layer 12 and the first trapping layer 11 place plane, so that
The total upper surface flush obtaining.
As seen from Figure 7, after planarization, in first groove, form electrostatic isolation layer 15a, in second groove, form grid
Material layer 15b, forms gate material layers 15c in the 3rd groove.
Afterwards, execution step s17, as shown in figure 8, first groove 11a, second groove in described Semiconductor substrate 10
11b and the 3rd groove 11c both sides form p trap 16.Specifically, first time ion implanting and annealing can be carried out, partly lead described
In body substrate 10, first groove 11a, second groove 11b and the 3rd groove 11c both sides form p trap 16.
In this step s17, described first time ion implanting is injected using boron ion with being annealed into, and Implantation Energy is 60kev-
150kev, implantation dosage 1e13/cm2-1e14/cm2, annealing temperature be 1000 DEG C -1200 DEG C.
Because the implantation concentration of described p trap 16 is thin relative to what the doping of encapsulant layer 13 needed, therefore can be with full wafer
It is directly injected into.
Specifically, need the gate dielectric layer 12 and the first trapping layer 11 that the remain thickness on Semiconductor substrate 10 surface
Degree is consistent, and if thickness is more thanInjection atom will be made to be not easy to penetrate, special using of regrowing after can floating to the greatest extent
The oxide layer sheltered in injection.
More specifically, if the gate dielectric layer remaining 12 and the first trapping layer 11 are on Semiconductor substrate 10 surface
Thickness is less thanWill not be good as the effect sheltered of injection, therefore, the gate dielectric layer 12 remaining and the first trapping layer
11 thickness on Semiconductor substrate 10 surface should be
Afterwards, execution step s18, refer to Fig. 9, first groove 11a, second groove in described Semiconductor substrate 10
N-type area 17a, the encapsulant layer 13 in described first groove 11a are formed on 11b and p trap 16 described in the 3rd groove 11c both sides
Middle formation the first doped region 17b.Specifically, second ion implanting, first ditch in described Semiconductor substrate 10 can be carried out
Groove 11a, second groove 11b and the 3rd groove 11c both sides form n-type area 17a, the packing material in described first groove 11a
Form the first doped region 17b, the junction depth depth of described n-type area 17a is less than the depth of described p trap 16, described first doping in layer
Area 17b penetrates the encapsulant layer 13 in described first groove 11a.
Generally in actual process, the implantation dosage of the first doped region 17b of n-type area 17a of device and electrostatic isolation structure
Be more or less the same, can by the design adjustment width of the first doped region 17b of electrostatic isolation structure and quantity, make n-type area 17a and
The injection of the first doped region 17b of electrostatic isolation structure is processed simultaneously, reduces photoetching, injection processing cost.
Described second ion implanting is using phosphonium ion injection, and Implantation Energy is 60kev-150kev, implantation dosage
1e14/cm2-1e16/cm2.
From the implantation dosage of step s17 and step s18, the doping content of n-type area 17a of formation is more than p trap 16
Doping content, therefore described n-type area 17a is N-shaped heavily doped region.
Afterwards, execution step s19, as shown in Figure 10, forms the in the encapsulant layer 13 in described first groove 11a
Two doped regions 18, described first doped region 17a and the second doped region 18 are spaced apart, and doping type is different, formed electrostatic every
From structure.Specifically, third time ion implanting can be carried out, be formed in the encapsulant layer 13 in described first groove 11a
Second doped region 18, described first doped region 17b and the second doped region 18 are spaced apart, and described second doped region 18 penetrates described
Encapsulant layer 13 in first groove 11a, forms electrostatic isolation structure.
Described third time ion implanting is using boron ion injection, and Implantation Energy is 60kev-150kev, implantation dosage
1e14/cm2-1e16/cm2.
Specifically, in this step s19, the first doped region 17b of described electrostatic isolation structure and the second doped region 18, need
The coupling of n and p Implantation Energy, dosage, only electrostatic isolation structure are done according to the p/n spacing of electrostatic isolation structure and number
P/n spacing and number, n and p Implantation Energy, dosage match and surplus abundance in the case of, just enable optimal esd
Expressive ability, makes full use of the area of electrostatic isolation structure, reduces chip area.
More specifically, under the conditions of identical esd design and processes, electrostatic isolation structural area is bigger, and the logarithm of n/p is got over
Many, its electrostatic isolation structure pressure bigger, usual esd ability is stronger；
More specifically, esd test typically requires more than 2000v, may require that more than 4000v even in special construction
More than 6000v, now the design of esd, process optimization are particularly important.
Afterwards, can also continue to execution step s20, refer to Figure 11, dielectric layer is formed on described Semiconductor substrate 10
19.Specifically, described dielectric layer 19 can be formed using depositing operation and do backflow annealing.The process optimization of described backflow annealing
The planarization process when being formed for the dielectric layer 19, is also that above the first doped region 17b and the second doped region 18 are injected simultaneously, with
And the annealing activation process of the injection of n-type area 17a.Described backflow annealing temperature is 800 DEG C -1000 DEG C.
Continue executing with step s21, please continue to refer to Figure 11, etch described dielectric layer 19 to form contact hole 19a, 19b and
19c, in the first doped region 17b that described contact hole 19a, 19b and 19c extend respectively in first groove 11a, second groove
In the encapsulant layer 13 of 11b and in the p trap 16 of the 3rd groove 11c side.Described contact hole 19a, 19b and 19c are located at described
Depth h3 in Semiconductor substrate 10 is equal to the depth after the annealing of n-type area 17a, 0.1 μm -0.8 μm of its depth.
Continue executing with step s22, as shown in figure 11, in described contact hole 19a, p-type area 19d is formed on 19b and 19c bottom.
Specifically, carry out the 4th secondary ion injection and anneal, form described p-type area 19d.Described 4th secondary ion is injected to injection element
B11 or bf2Or first note b11 notes bf again2.
Specifically, in step s22, Implantation Energy is 20kev-100kev, and implantation dosage is 1e14/cm2-1e16/cm2,
For example can be using zero angle injection.After the implantation, optional boiler tube or short annealing (rta), annealing temperature be 500 DEG C-
1000℃.
Continue executing with step s23, refer to Figure 12, metal level 20, described metal are formed on described Semiconductor substrate 10
The layer 20 described contact hole 19a of filling, 19b and 19c are simultaneously contacted with described p-type area 19d.Specifically, the metal level of described deposition
22 can close for titaniferous (ti), titanium nitride (tin), titanium silicide (tisi), tungsten (w), aluminum (al), silicated aluminum (alsi), copper sial
Metal or the compound materials such as golden (alsicu), copper (cu) or nickel (ni).Specifically, described metal level 20 can be to adopt dry method
The metal connecting line being formed after etching.
Further, after the completion of step s23, have been carried out the metallization of device, can according to product need increase
Passivation layer is protected, and completes the processing of device Facad structure；
Further, after the completion of Facad structure, complete device through a series of postchannel process such as thinning, back of the body gold, scribing
The final realization of part.
Below incorporated by reference to Fig. 3-Figure 12 it is seen that this utility model provide groove power device, comprising:
Semiconductor substrate 10；
First groove 11a, second groove 11b and the 3rd groove 11c in described Semiconductor substrate 10；Preferably, institute
The depth stating first groove 11a is 1 μm -3.5 μm, and width is 1 μm -10 μm, and the depth of described second groove 11b is 1 μm of -3.5 μ
M, width is 0.5 μm -2 μm, and the depth of described 3rd groove 11c is 1 μm -3.5 μm, and width is 0.1 μm -0.6 μm；
Positioned at Semiconductor substrate 10 surface of described first groove 11a region and the diapire of described first groove 11a
With the first trapping layer 11 of side wall, preferably, the material of described first trapping layer 11 be silicon dioxide, silicon nitride, silicon oxynitride
One kind or combination, the thickness that described first trapping layer 11 is located at described first groove 11a diapire is
Semiconductor substrate 10 surface and second groove positioned at described second groove 11b and the 3rd groove 11c region
Gate dielectric layer 12 on the diapire and side wall of 11b and the 3rd groove 11c；Preferably, the thickness of described gate dielectric layer 12 is
Encapsulant layer 13 in first groove 11a, second groove 11b and the 3rd groove 11c, and described grid dielectric
Layer the 12, first trapping layer 11 and the upper surface flush of encapsulant layer 13, the thickness of described encapsulant layer 13 is 0.3 μm of -1 μ
m；
The first doped region 17b in the encapsulant layer 13 of 11a in described first groove and the second doped region 18, institute
State the first doped region 17b and the second doped region 18 is spaced apart, and doping type is different, collectively as electrostatic isolation structure；
The p trap of first groove 11a, second groove 11b and the 3rd groove 11c both sides in described Semiconductor substrate 10
16；
First groove 11a, second groove 11b and p trap described in the 3rd groove 11c both sides in described Semiconductor substrate 10
N-type area 17a on 16；The junction depth depth of described n-type area 17a is less than the depth of described p trap 16；
Dielectric layer 19 in described Semiconductor substrate 10；
Contact hole 19a, 19b and 19c, described contact hole 19a, 19b and 19c run through described dielectric layer 19 and extend respectively to
In the first doped region 17b in first groove 11a, in the encapsulant layer 13 in second groove 11b and the 3rd groove 11c side
P trap 16 in, described contact hole 19a, 19b and 19c be located at described Semiconductor substrate 10 in depth be equal to n-type area 17a anneal
Depth afterwards, 0.1 μm -0.8 μm of its depth；
Positioned at described contact hole 19a, p-type area 19d of 19b and 19c bottom；
Metal level 20, described metal level 20 fills described contact hole 19a, 19b and 19c is simultaneously connected with described p-type area 19d
Touch；Preferably, the material of described metal level 20 is titanium, titanium nitride, titanium silicide, tungsten, aluminum, silicated aluminum, copper silmin, copper or nickel
Compound on metal or metal；And
Passivation layer on described metal level 20.
Thus, this utility model provides a kind of groove power device and manufacture method, by providing Semiconductor substrate；?
Form first groove, second groove and the 3rd groove in described Semiconductor substrate；In partly leading of described first groove region
Form the first trapping layer on the diapire of body substrate surface and described first groove and side wall；In described second groove and the 3rd groove
Gate dielectric layer is grown on the diapire of the semiconductor substrate surface of region and second groove and the 3rd groove and side wall；Formation is filled out
Fill material layer and fill completely described first groove, second groove and the 3rd groove；Planarized so that described Semiconductor substrate
Surface exposure goes out gate dielectric layer, the first trapping layer and encapsulant layer, and described gate dielectric layer, the first trapping layer and packing material
The upper surface flush of layer；In described Semiconductor substrate, first groove, second groove and the 3rd groove both sides form p trap；Institute
State formation n-type area on first groove in Semiconductor substrate, second groove and p trap described in the 3rd groove both sides, in described first ditch
Form the first doped region in encapsulant layer in groove；Form the second doping in the encapsulant layer in described first groove
Area, described first doped region and the second doped region are spaced apart, and doping type is different, form electrostatic isolation structure；Described
Dielectric layer is formed on Semiconductor substrate；Etch described dielectric layer to form contact hole, described contact hole extends respectively to the first ditch
In first doped region of groove, in the encapsulant layer of second groove and in the p trap of the 3rd groove side；And in described contact hole
P-type area is formed on bottom.And then achieving electrostatic isolation structure setting in the semiconductor substrate, it is to avoid electrostatic isolation structure is higher than
, so that semiconductor substrate surface is smooth, effectively solving is due to conventional electrostatic isolation structure for second groove, the situation of the 3rd groove
Unevenness makes follow-up depositing operation Step Coverage ability not good, and particularly spin coating bad for photoetching, and exposure is abnormal, at step
Photoresist partially thin cannot effectively as etching barrier layer the problems such as, thus realizing device architecture, so that parameter and reliable sexual satisfaction is produced
The requirement of product.
Further, a kind of trench power device structure of the present utility model and manufacture method, can be used in including but
It is not limited in the products such as cmos, bcd, power mosfet, high power transistor, igbt and Schottky.
Obviously, those skilled in the art can carry out various changes and modification without deviating from this practicality to this utility model
New spirit and scope.So, if of the present utility model these modification and modification belong to this utility model claim and
Within the scope of its equivalent technologies, then this utility model is also intended to comprise these changes and modification.
Claims (9)
1. a kind of groove power device, comprising:
Semiconductor substrate；
First groove, second groove and the 3rd groove in described Semiconductor substrate；
Positioned at the semiconductor substrate surface of described first groove region and the diapire of described first groove and side wall first
Trapping layer；
Semiconductor substrate surface positioned at described second groove and the 3rd groove region and second groove and the 3rd groove
Gate dielectric layer on diapire and side wall；
Encapsulant layer in first groove, second groove and the 3rd groove, and described gate dielectric layer, the first trapping layer and
The upper surface flush of encapsulant layer；
The first doped region in the encapsulant layer in described first groove and the second doped region, described first doped region and
Second doped region is spaced apart, and doping type is different, collectively as electrostatic isolation structure；
The p trap of first groove, second groove and the 3rd groove both sides in described Semiconductor substrate；
N-type area on first groove, second groove and p trap described in the 3rd groove both sides in described Semiconductor substrate；
Dielectric layer in described Semiconductor substrate；
Contact hole, described contact hole run through described dielectric layer and extend respectively in the first doped region of first groove, the second ditch
In the encapsulant layer of groove and in the p trap of the 3rd groove side；And
P-type area positioned at described contact hole bottom.
2. groove power device as claimed in claim 1 it is characterised in that described first groove depth be 1 μm -3.5 μm,
Width is 1 μm -10 μm, and the depth of described second groove is 1 μm -3.5 μm, and width is 0.5 μm -2 μm, the depth of described 3rd groove
Spend for 1 μm -3.5 μm, width is 0.1 μm -0.6 μm.
3. groove power device as claimed in claim 1 is it is characterised in that described first trapping layer stops for silicon dioxide
Layer, silicon nitride trapping layer, one kind of silicon oxynitride trapping layer.
4. groove power device as claimed in claim 1 is it is characterised in that the thickness of described first trapping layer is
5. groove power device as claimed in claim 1 is it is characterised in that the thickness of described encapsulant layer is 0.3 μm of -1 μ
m.
6. groove power device as claimed in claim 1 is it is characterised in that described first doped region and the second doped region are worn
Encapsulant layer in described first groove thoroughly.
7. groove power device as claimed in claim 1 is it is characterised in that described dielectric layer is silica dioxide medium layer, nitrogen
SiClx dielectric layer, silicon oxynitride dielectric layer, one kind of polycrystalline silicon medium layer.
8. groove power device as claimed in claim 1 is it is characterised in that described contact hole is located in described Semiconductor substrate
Depth be 0.1 μm -0.8 μm.
9. groove power device as claimed in claim 1 is it is characterised in that also include:
Metal level in described Semiconductor substrate, described metal level fills described contact hole；And
Passivation layer on described metal level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620738421.9U CN205911311U (en) | 2016-07-12 | 2016-07-12 | Slot power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620738421.9U CN205911311U (en) | 2016-07-12 | 2016-07-12 | Slot power device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205911311U true CN205911311U (en) | 2017-01-25 |
Family
ID=57805235
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620738421.9U Active CN205911311U (en) | 2016-07-12 | 2016-07-12 | Slot power device |
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| CN (1) | CN205911311U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024701A (en) * | 2016-07-12 | 2016-10-12 | 杭州士兰集成电路有限公司 | Trench power device and manufacturing method |
| CN106024696A (en) * | 2016-07-12 | 2016-10-12 | 杭州士兰集成电路有限公司 | Trench power device and manufacturing method |
-
2016
- 2016-07-12 CN CN201620738421.9U patent/CN205911311U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024701A (en) * | 2016-07-12 | 2016-10-12 | 杭州士兰集成电路有限公司 | Trench power device and manufacturing method |
| CN106024696A (en) * | 2016-07-12 | 2016-10-12 | 杭州士兰集成电路有限公司 | Trench power device and manufacturing method |
| CN106024696B (en) * | 2016-07-12 | 2023-04-28 | 杭州士兰集成电路有限公司 | Trench power device and manufacturing method |
| CN106024701B (en) * | 2016-07-12 | 2023-06-16 | 杭州士兰集成电路有限公司 | Trench power device and manufacturing method |
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