CN205789987U - groove power device - Google Patents
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- CN205789987U CN205789987U CN201620741893.XU CN201620741893U CN205789987U CN 205789987 U CN205789987 U CN 205789987U CN 201620741893 U CN201620741893 U CN 201620741893U CN 205789987 U CN205789987 U CN 205789987U
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Abstract
This utility model discloses a kind of groove power device.nullA kind of groove power device that this utility model provides，By forming the first groove in the semiconductor substrate、Second groove、3rd groove，And at the diapire formation first medium layer of described groove，Sidewall at the first groove forms second dielectric layer，On the first medium layer of the first groove, the encapsulant layer between second dielectric layer forms electrostatic isolation structure，And then achieve the setting of electrostatic isolation structure in the semiconductor substrate，Avoid electrostatic isolation structure higher than the second groove、The situation of the 3rd groove，Make semiconductor substrate surface smooth，Effectively solve to make follow-up depositing operation Step Coverage ability the best due to the unevenness of conventional electrostatic isolation structure，Particularly photoetching occurs that spin coating is bad，Exposure is abnormal，At step, photoresist is the thinnest cannot be effectively as problems such as etching barrier layers，Thus realize device architecture，Parameter and reliability is made to meet the requirement of product.
Description
Technical field
This utility model relates to field of semiconductor devices, particularly relates to a kind of groove power device.
Background technology
In semiconductor technology, power discrete device includes the devices such as power MOSFET, high power transistor and IGBT.In early days
Power device is all based on planar technology and produces, but along with the development of semiconductor technology, small size, high-power, high-performance one-tenth
The trend of quasiconductor development.Trench process, owing to raceway groove is become vertical from level, eliminates planar structure parasitism JFET resistance
Impact, make cellular size be substantially reduced, increase primitive unit cell density on this basis, improve the beam overall of raceway groove in unit are chip
Degree, it is possible to device channel width-over-length ratio on unit silicon chip is increased so that electric current increases, conducting resistance declines and
Relevant parameter is optimized, it is achieved that smaller size of tube core has greater power and high performance target, therefore trench process
Get more and more and apply in New Type Power Devices.
Static discharge (Electro Static Discharge, ESD) is a kind of rapid electric charge between two objects
Transfer phenomena, is attended by the biggest electric field intensity and electric current density in this phenomenon, if this energy can not effectively be discharged, it will
Cause device gate-oxide to puncture, even make silicon substrate and dielectric layer puncture, burn out.At present in circuit product, most integrated
Electrostatic isolation structure in circuit is realized by doped silicon the most in a silicon substrate, and this will take certain silicon area,
But for device products, it is common that realize electrostatic isolation structure at polysilicon layer (solid space), it becomes possible to save certain face
Long-pending, thus cost-effective.But the electrostatic isolation structure using polysilicon to realize, there is also all drawbacks.It is illustrated in figure 1 biography
System has the trench power device structure schematic diagram of electrostatic protection function, and whole device can be divided into ESD region, gate trace region
With primitive unit cell region.Wherein, in ESD region, electrostatic isolation structure 3 uses the alternate ESD that realizes of polysilicon doping many groups P/N to protect exactly
Protective function.Owing to electrostatic isolation structure 3 will exist the biggest electric field intensity and electric current density, it is therefore desirable to electrostatic isolation is tied
Structure 3 and bulk silicon substrate 1 are effectively isolated out, and therefore need thicker dielectric layer 2 to isolate below electrostatic isolation structure 3, thick
Degree h1 typically requires and is more thanSimultaneously as polysilicon itself needs thickness h 2 to be typically larger thanTherefore can deposit
Be even greater than the step difference of 1 μm in about 1 μm, this uneven structure can make the platform of the technique of follow-up metallization medium layer 4
Rank cover the best, and particularly photoetching occurs that spin coating is bad, and exposure is abnormal, and at step, photoresist is the thinnest cannot be effectively as etching resistance
Barrier, makes device architecture to realize, and makes the parameter of product and reliability can not meet requirement.
How to pass through the step difference optimized product structure, technological process reduction produces due to electrostatic isolation structure, make whole
Semiconductor substrate surface is smooth, effectively solves to make follow-up depositing operation step due to the unevennessization of conventional electrostatic isolation structure
Covering power is the best, and particularly photoetching occurs that spin coating is bad, and exposure is abnormal, and at step, photoresist is the thinnest cannot be effectively as etching
The problems such as barrier layer, and how to combine bottom thick oxide layer (Thick Bottom Oxide, TBO) technique, it is thus achieved that high-performance
The electrostatic isolation structure of ESD ability, thus realize device architecture, make parameter and reliability meet the requirement of product, be this technology
The content that field personnel are to be studied.
Utility model content
The purpose of this utility model is to provide a kind of groove power device, solves caused by conventional electrostatic isolation structure
Semiconductor substrate surface uneven and affect follow-up depositing operation Step Coverage ability, particularly photoetching occurs that spin coating is not
Good, exposure is abnormal, and at step, photoresist is the thinnest cannot be effectively as problems such as etching barrier layers.
For solving the problems referred to above, this utility model provides a kind of groove power device, including:
Semiconductor substrate；
The first groove, the second groove and the 3rd groove being positioned in described Semiconductor substrate；
It is positioned at the first medium layer of the diapire of described first groove diapire, the second groove and the 3rd groove；
The grid being positioned on the sidewall of described semiconductor substrate surface and described first groove, the second groove and the 3rd groove are situated between
Electric layer；
It is positioned at the encapsulant layer in the first groove, the second groove and the 3rd groove, and described gate dielectric layer and fill material
The upper surface flush of the bed of material；
It is positioned at the first doped region in the encapsulant layer of described first groove and the second doped region, described first doping
District and the second doped region are spaced apart, and doping type is different, collectively as electrostatic isolation structure；
It is positioned in described first groove against the sidewall of described first groove and exposes the groove of described first medium layer；
It is positioned at the first groove in described Semiconductor substrate, the second groove and the p-well of the 3rd groove both sides；
It is positioned at the N-type region in p-well described in the first groove in described Semiconductor substrate, the second groove and the 3rd groove both sides；
Being positioned at the second dielectric layer in described Semiconductor substrate, described second dielectric layer fills described groove；
Contact hole, described contact hole runs through described second dielectric layer and extends respectively to the first doped region of the first groove
In, in the encapsulant layer of the second groove and in the p-well of the 3rd groove side；And
It is positioned at the p type island region bottom described contact hole.
Optionally, for described groove power device, the degree of depth of described first groove is 0.8 μm-2.5 μm, and width is 1
μm-10 μm, the degree of depth of described second groove is 0.8 μm-2.5 μm, and width is 0.5 μm-2 μm, and the degree of depth of described 3rd groove is
0.8 μm-2.5 μm, width is 0.1 μm-0.6 μm.
Optionally, for described groove power device, described first medium layer is silica dioxide medium layer, silicon nitride Jie
Matter layer, one or more combinations of silicon oxynitride dielectric layer.
Optionally, for described groove power device, the thickness of described first medium layer is
Optionally, for described groove power device, the thickness of described encapsulant layer is 0.3 μm-1 μm.
Optionally, for described groove power device, described first doped region and the second doped region penetrate described first
Encapsulant layer in groove.
Optionally, for described groove power device, the width of described groove is 0.2 μm-1.5 μm.
Optionally, for described groove power device, described second dielectric layer is silica dioxide medium layer, silicon nitride Jie
Matter layer, the one of silicon oxynitride dielectric layer or combination.
Optionally, for described groove power device, described contact hole is positioned at the degree of depth in described Semiconductor substrate and is
0.1μm-0.8μm。
Optionally, for described groove power device, also include:
Being positioned at the metal level in described Semiconductor substrate, described metal level fills described contact hole；And
It is positioned at the passivation layer on described metal level.
Compared with prior art, a kind of groove power device that this utility model provides, by shape in the semiconductor substrate
Become the first groove, and at the diapire formation first medium layer of described first groove, the sidewall at the second groove forms second medium
Layer, forms electrostatic isolation structure on first medium layer, and then achieves electrostatic isolation structure and be arranged between second dielectric layer
In Semiconductor substrate, it is to avoid electrostatic isolation structure is higher than the second groove, the situation of the 3rd groove so that semiconductor substrate surface
Smooth, effectively solve to make follow-up depositing operation Step Coverage ability the best due to the unevenness of conventional electrostatic isolation structure, special
Not being that photoetching occurs that spin coating is bad, exposure is abnormal, at step photoresist the thinnest cannot effectively as problems such as etching barrier layers, from
And realize device architecture, make parameter and reliability meet the requirement of product.
Accompanying drawing explanation
Fig. 1 is the structural representation of groove power device in prior art；
Fig. 2 is the flow chart of the groove power device manufacture method in this utility model one embodiment；
Fig. 3-12 is that the structure in the manufacturing process of the groove power device in this utility model embodiment one embodiment is shown
It is intended to.
Detailed description of the invention
Below in conjunction with schematic diagram, groove power device of the present utility model and manufacture method are described in more detail,
Which show preferred embodiment of the present utility model, it should be appreciated that those skilled in the art can revise described here reality
With novel, and still realize advantageous effects of the present utility model.Therefore, description below is appreciated that for art technology
Personnel's is widely known, and is not intended as restriction of the present utility model.
Referring to the drawings this utility model the most more particularly described below in the following passage.According to following explanation and power
Profit claim, advantage of the present utility model and feature will be apparent from.It should be noted that, accompanying drawing all use the form simplified very much and
All use non-ratio accurately, only in order to purpose convenient, aid illustration this utility model embodiment lucidly.
This utility model provides a kind of groove power device and manufacture method, the manufacture method bag of described groove power device
Include:
Step S11, it is provided that Semiconductor substrate；
Step S12, forms the first groove, the second groove and the 3rd groove in described Semiconductor substrate；
Step S13, the diapire at described first groove, the second groove and the 3rd groove forms first medium layer；
Step S14, on the sidewall of described semiconductor substrate surface and described first groove, the second groove and the 3rd groove
Growth gate dielectric layer；
Step S15, forms encapsulant layer in described first groove, the second groove and the 3rd groove and fills full described
First groove, the second groove and the 3rd groove；
Step S16, planarizes so that described semiconductor substrate surface exposes gate dielectric layer and encapsulant layer,
And described gate dielectric layer and the upper surface flush of encapsulant layer；
Step S17, in described Semiconductor substrate, the first groove, the second groove and the 3rd groove both sides form p-well；
Step S18, shape in p-well described in the first groove, the second groove and the 3rd groove both sides in described Semiconductor substrate
Become N-type region, the encapsulant layer in described first groove forms the first doped region；
Step S19, forms the second doped region in the encapsulant layer in described first groove, described first doped region and
Second doped region is spaced apart, and doping type is different；
Step S20, etches the encapsulant layer formation in described first groove the most sudden and the most violent against the sidewall of described first groove
Expose the groove of described first medium layer, remain the first doped region and the second doped region collectively as electrostatic isolation structure；
Step S21, forms second dielectric layer on the semiconductor substrate, and described second dielectric layer fills described groove；
Step S22, etches described second dielectric layer to form contact hole, and described contact hole extends respectively to the first groove
In first doped region, in the encapsulant layer of the second groove and in the p-well of the 3rd groove side；And
Step S23, forms p type island region bottom described contact hole.
Incorporated by reference to Fig. 2 and Fig. 3-12, groove power device of the present utility model and manufacture method are situated between in detail below
Continue.The flow chart of the groove power device manufacture method during wherein Fig. 2 is this utility model one embodiment；Fig. 3-12 is this practicality
Structural representation in the manufacturing process of the groove power device in new embodiment one embodiment.
First, step S11 is performed, as shown in Figure 3, it is provided that Semiconductor substrate 10.Described Semiconductor substrate 10 can be silicon
Substrate, germanium silicon substrate, III-group Ⅴ element compound substrate or well known to a person skilled in the art other semiconductive material substrate,
The present embodiment uses silicon substrate.More specifically, the silicon substrate used in the present embodiment could be formed with MOS field effect crystalline substance
The semiconductor device such as body pipe, IGBT isolated-gate field effect transistor (IGFET), Schottky.
Concrete, in this step S11, described in there is the Semiconductor substrate of specific doping type, refer to according to product
The N-type of property doped certain impurity level and P-type semiconductor substrate.
Then, perform step S12, described Semiconductor substrate 10 is formed the first groove 11a, the second groove 11b and the
Three groove 11c.Please continue to refer to Fig. 3, can be in described Semiconductor substrate 10, use dry etching etching silicon, it is thus achieved that described
First groove 11a, the second groove 11b and the 3rd groove 11c.The degree of depth of described first groove 11a is 0.8 μm-2.5 μm, width
Being 1 μm-10 μm, the degree of depth of described second groove 11b is 0.8 μm-2.5 μm, and width is 0.5 μm-2 μm, described 3rd groove 11c
The degree of depth be 0.8 μm-2.5 μm, width is 0.1 μm-0.6 μm.In this utility model, the described first groove 11a mesh of formation
Be in order to by electrostatic isolation structure fabrication afterwards in this first groove 11a, and described first groove 11a region is
ESD district, accordingly, described second groove 11b region is grid lead district, and described 3rd groove 11c region is former
Born of the same parents district.
Then, perform step S121, carry out high temperature reparation.It is also preferred that the left perform height in 1000 DEG C of-1200 DEG C of temperature ranges
Temperature sacrificial oxidation, carries out high temperature repair described first groove 11a, the second groove 11b and the diapire of the 3rd groove 11c and sidewall
Multiple, produce aboutThe sacrificial oxide layer of thickness, then uses diluter BOE corrosive liquid to rinse.
Then, perform step S13, refer to Fig. 4, at described first groove 11a, the second groove 11b and the 3rd groove 11c
Diapire formed first medium layer 11.In this utility model embodiment, the material of described first medium layer 11 be silicon dioxide,
The material such as silicon nitride, silicon oxynitride, or be described silicon oxide, silicon nitride, silicon oxynitride, etc. material one or more combination.
Concrete, in this step S13, described in the present embodiment, the material of first medium layer 11 is chosen as silicon oxide, thickness
For
Concrete, in this step S13, use high density plasma CVD (HDPCVD) to form described the
One dielectric layer 11.And from fig. 4, it can be seen that described first medium layer 11 be made only in described first groove 11a, the second groove 11b and
The diapire of the 3rd groove 11c, other positions of Semiconductor substrate 10 are then uncovered.
Thus, this step achieves thick oxide layer bottom combination (Thick Bottom Oxide, TBO) technique and carries out groove
The manufacture processing of power device, is favorably improved sensitivity and the response speed of device, reduces energy consumption.
Then, perform step S14, refer to Fig. 5, described Semiconductor substrate 10 surface and described first groove 11a, the
Two groove 11b and the sidewall growth gate dielectric layer 12 of the 3rd groove 11c.The growth of described gate dielectric layer 12 can use mixes chlorine oxygen
Having changed, temperature range is 1000 DEG C-1200 DEG C, and the thickness range of described gate dielectric layer 12 isPreferably
, when the thickness of gate dielectric layer 12 isTime, (gate dielectric layer 12 can be used as the masking layer being subsequently implanted into
Thickness relationship to Vth the multiple parameters such as Qg, its thickness determines according to product attribute, and therefore those skilled in the art can depend on
According to being actually needed the thickness setting gate dielectric layer 12).
Then, perform step S15, formed in described first groove 11a, the second groove 11b and the 3rd groove 11c and fill
Material layer 13 also fills full described first groove 11a, the second groove 11b and the 3rd groove 11c.It is also preferred that the left described packing material
Layer 13 material be any P of plain polysilicon, i.e. undoped p or N-type impurity polysilicon.This step is primarily due to
Electrostatic isolation structure needs by carrying out more accurate regional injection on encapsulant layer 13, it is achieved ESD function, if heavy
There is doping during Ji, follow-up first doped region of adjustment electrostatic isolation structure and the concentration of the second doped region will be deposited
In bigger uncertainty.
Concrete, in step S15, the polycrystalline that undopes of described deposition, it is pressure that its thickness bears ESD owing to needs possess
Releasability, it usually needs be thicker thanSuch as 0.3 μm-1 μm.
Then, perform step S151, refer to Fig. 5, described Semiconductor substrate 10 is formed the first trapping layer 14, described
First trapping layer 14 covers the encapsulant layer 13 on described first groove 11a region.The material of described first trapping layer 14
Material is silicon dioxide, silicon nitride, the one of silicon oxynitride or combination, the most in the present embodiment, can be chosen as silicon oxide material
Matter.The thickness of described first trapping layer 14 is
Then, step S152 is performed, with described first trapping layer 14 as mask, to the second groove 11b and the 3rd groove 11c
In encapsulant layer 13 be doped.Concrete, can be that the method using phosphorus pre-deposition is doped.
Then, perform step S16, as shown in Fig. 5-Fig. 6, planarize so that described Semiconductor substrate 10 surface is naked
Expose gate dielectric layer 12 and encapsulant layer 13, and described gate dielectric layer 12 and the upper surface flush of encapsulant layer 13.Specifically
, this step S16 includes: removes described first trapping layer 14 successively and is partially filled with material layer 13, exposing gate dielectric layer 12
With encapsulant layer 13, and described gate dielectric layer 12 and encapsulant layer 13 upper surface flush.Concrete, concrete, can adopt
Remove described first trapping layer 14 with wet etching, and for being partially filled with the removal of material layer 13, then can use chemistry machine
Tool grinds (CMP) technique, it would however also be possible to employ returns carving technology, so that gate dielectric layer 12 exposes, is achieved in quasiconductor table
On face smooth.
Afterwards, perform step S17, as it is shown in fig. 7, first groove 11a, the second groove in described Semiconductor substrate 10
11b and the 3rd groove 11c both sides form p-well 15.Concrete, ion implanting and annealing for the first time can be carried out, partly lead described
In body substrate 10, the first groove 11a, the second groove 11b and the 3rd groove 11c both sides form p-well 15.
In this step S17, described first time ion implanting uses boron ion implanting with being annealed into, and Implantation Energy is 60KeV-
150KeV, implantation dosage 1E13/cm2-1E14/cm2, annealing temperature is 1000 DEG C-1200 DEG C.
Owing to the implantation concentration of described p-well 15 is thin relative to what the doping of encapsulant layer 13 needed, therefore can be with full wafer
It is directly injected into.
Concrete, if the gate dielectric layer remained 12 thickness is more thanInjection atom will be made to be not easy to wear
Thoroughly, regrow after can floating to the greatest extent to be specifically designed to and inject the oxide layer sheltered.
More specifically, if the thickness of the gate dielectric layer remained 12 is less thanWill as injecting the effect sheltered
The best, therefore, the gate dielectric layer 12 remained thickness on Semiconductor substrate 10 surface should be
Afterwards, perform step S18, refer to Fig. 8, first groove 11a, the second groove in described Semiconductor substrate 10
N-type region 16, the encapsulant layer 13 in described first groove 11a is formed in p-well 15 described in 11b and the 3rd groove 11c both sides
Middle formation the first doped region 17.Concrete, second time ion implanting, first groove in described Semiconductor substrate 10 can be carried out
11a, the second groove 11b and the 3rd groove 11c both sides form N-type region 16, in the encapsulant layer in described first groove 11a
Forming the first doped region 17, the junction depth degree of depth of described N-type region 16 is less than the degree of depth of described p-well 15, and described first doped region 17 is worn
Encapsulant layer in the most described first groove 11a.
Generally in actual process, the N-type region 16 of device and the implantation dosage phase of the first doped region 17 of electrostatic isolation structure
Difference is little, can make N-type region 16 and electrostatic by the width of the first doped region 17 of design adjustment electrostatic isolation structure and quantity
The injection of the first doped region 17 of isolation structure is processed simultaneously, reduces photoetching, injects processing cost.
Described second time ion implanting is for using phosphonium ion to inject, and Implantation Energy is 60KeV-150KeV, implantation dosage
1E14/cm2-1E16/cm2。
From step S17 and the implantation dosage of step S18, the doping content of the N-type region 16 of formation is mixed more than p-well 15
Miscellaneous concentration, the most described N-type region 16 is N-type heavily doped region.
Afterwards, perform step S19, as it is shown in figure 9, the encapsulant layer 13 of 11a is formed in described first groove the
Two doped regions 18, described first doped region 17 and the second doped region 18 are spaced apart, and doping type is different.Concrete, permissible
Carry out third time ion implanting, the encapsulant layer 13 in described first groove 11a forms the second doped region 18, described the
One doped region 17 and the second doped region 18 are spaced apart.
Described third time ion implanting is for using boron ion implanting, and Implantation Energy is 60KeV-150KeV, implantation dosage
1E14/cm2-1E16/cm2。
Concrete, in this step S19, the first doped region 17 and the second doped region 18 of described electrostatic isolation structure, need
The coupling of N and P Implantation Energy, dosage, only electrostatic isolation structure is done according to the P/N spacing of electrostatic isolation structure and number
P/N spacing and number, N and P Implantation Energy, the matching and in the case of surplus abundance of dosage, optimal ESD could be realized
Expressive ability, makes full use of the area of electrostatic isolation structure, reduces chip area.
More specifically, under the conditions of identical ESD design and processes, electrostatic isolation structural area is the biggest, and the logarithm of N/P is more
Many, its electrostatic isolation structure pressure the biggest, usual ESD ability is the strongest；
More specifically, ESD test typically requires more than 2000V, may require that more than 4000V even in special construction
More than 6000V, now the design of ESD, process optimization are particularly important.
Afterwards, perform step S20, refer to Figure 10, etch encapsulant layer in described first groove 11a formed against
The sidewall of described first groove 11a also exposes the groove 19 of described first medium layer 11, remains the first doped region 17 and second
Doped region 18 is collectively as electrostatic isolation structure.Concrete, this step performs dry etching, by described recessed after can using photoetching
Groove 19 is formed.By the existence of this groove 19, and in this groove 19, fill second dielectric layer (seeing step S21) further,
The sidewall (namely Semiconductor substrate 10) of electrostatic isolation structure with groove is separated, so that it is guaranteed that electrostatic isolation structure is not to periphery
Structure produces impact.
Concrete, the width of described groove 19 is 0.2 μm-1.5 μm.
Afterwards, perform step S21, refer to Figure 11, described Semiconductor substrate 10 is formed second dielectric layer 20, described
Second dielectric layer 20 fills full described groove 19.The material of described second dielectric layer 20 is silicon dioxide, silicon nitride, silicon oxynitride
One or combination.In the present embodiment, such as selective oxidation silicon.Described second dielectric layer 20 fills full described groove 19, and
It is formed on gate dielectric layer 12.Concrete, depositing operation can be used to form described second dielectric layer 20 and do backflow annealing.Institute
The process optimization second dielectric layer 20 that stating refluxes the anneals planarization process when being formed, is also to above the first doped region simultaneously
17 and second doped region 18 inject, and the annealing activation process of the injection of N-type region 16.Described backflow annealing temperature is 800 DEG C-
1000℃。
Continue executing with step S22, please continue to refer to Figure 11, etch described second dielectric layer 20 to form contact hole 20a,
20b and 20c, described contact hole 20a, 20b and 20c extend respectively in the first doped region 17, the packing material of the second groove 11b
In layer 13 and in the p-well 15 of the 3rd groove 11c side.Described contact hole 20a, 20b and 20c are positioned in described Semiconductor substrate 10
Degree of depth h3 equal to N-type region 16 anneal after the degree of depth, its degree of depth 0.1 μm-0.8 μm.
Continue executing with step S23, as shown in figure 11, bottom described contact hole 20a, 20b and 20c, form p type island region 20d.
Concrete, the 4th secondary ion can be carried out and inject and annealing, form described p type island region 20d.Described 4th secondary ion is injected to inject
Element B 11 or BF2, it is also possible to it is that first note B11 notes BF again2。
Concrete, in step S23, Implantation Energy is 20KeV-100KeV, and implantation dosage is 1E14/cm2-1E16/cm2,
Zero angle such as can be used to inject.After the implantation, optional boiler tube or short annealing (RTA), annealing temperature is 500 DEG C-
1000℃。
Continue executing with step S24, refer to Figure 12, described Semiconductor substrate 10 is formed metal level 21, described metal
Layer 21 is filled described contact hole 20a, 20b and 20c and contacts with described p type island region 20d.Concrete, the metal level of described deposition
21 can be titaniferous (Ti), titanium nitride (TiN), titanium silicide (TiSi), tungsten (W), aluminum (Al), silicated aluminum (AlSi), the conjunction of copper sial
Metal or the compound materials such as gold (AlSiCu), copper (Cu) or nickel (Ni).Concrete, described metal level 21 can be to use dry method
The metal connecting line formed after etching.
Further, after step S24 completes, have been carried out the metallization of device, can according to product need increase
Passivation layer is protected, and completes the processing of device Facad structure；
Further, after Facad structure completes, complete device through a series of postchannel process such as thinning, the back of the body gold, scribings
The final realization of part.
Below incorporated by reference to Fig. 3-Figure 12, it is seen that the groove power device that this utility model provides, including:
Semiconductor substrate 10；
The first groove 11a, the second groove 11b and the 3rd groove 11c being positioned in described Semiconductor substrate 10；It is also preferred that the left
The degree of depth of described first groove 11a is 0.8 μm-2.5 μm, and width is 1 μm-10 μm, and the degree of depth of described second groove 11b is 0.8 μ
M-2.5 μm, width is 0.5 μm-2 μm, and the degree of depth of described 3rd groove 11c is 0.8 μm-2.5 μm, and width is 0.1 μm-0.6 μm；
It is positioned at the first medium layer 11 of the diapire of described first groove 11a, the second groove 11b and the 3rd groove 11c；Preferably
, the material of described first medium layer 11 is silicon dioxide, silicon nitride, the one of silicon oxynitride or combination, described first medium
The thickness of layer 11 is
It is positioned at described semiconductor substrate surface and described first groove 11a, the second groove 11b and the side of the 3rd groove 11c
Gate dielectric layer 12 on wall；It is also preferred that the left the thickness of described gate dielectric layer 12 is
It is positioned at the encapsulant layer 13 in the first groove 11a, the second groove 11b and the 3rd groove 11c, and described grid dielectric
Layer 12 and the upper surface flush of encapsulant layer 13；It is also preferred that the left the thickness of described encapsulant layer 13 is 0.3 μm-1 μm；
The first doped region 17 and the second doped region 18, the institute being positioned in the encapsulant layer 13 of described first groove 11a
State the first doped region 17 and the second doped region 18 is spaced apart, and doping type is different, collectively as electrostatic isolation structure；
It is positioned in described first groove 11a against the sidewall of described first groove 11a and exposes described first medium layer
The groove 19 of 11；It is also preferred that the left the width of described groove 19 is 0.2 μm-1.5 μm；
It is positioned at the first groove 11a in described Semiconductor substrate 10, the second groove 11b and the p-well of the 3rd groove 11c both sides
15；
It is positioned at p-well described in the first groove 11a in described Semiconductor substrate 10, the second groove 11b and the 3rd groove 11c both sides
N-type region 16 on 15, the junction depth degree of depth of described N-type region 16 is less than the degree of depth of described p-well 15；
Being positioned at the second dielectric layer 20 in described Semiconductor substrate 10, described second dielectric layer 20 fills described groove 19；
Contact hole 20a, 20b and 20c, described contact hole 20a, 20b and 20c run through described second dielectric layer 20 and prolong respectively
Extend in the encapsulant layer 13 in the first doped region 17 in the first groove 11a, in the second groove 11b and the 3rd groove 11c
In the p-well 15 of side, the degree of depth that described contact hole 20a, 20b and 20c are positioned in described Semiconductor substrate 10 is equal to described N-type region
The degree of depth after 16 annealing, its degree of depth 0.1 μm-0.8 μm；
It is positioned at the p type island region 20d bottom described contact hole 20a, 20b and 20c；
Be positioned at the metal level 21 in described Semiconductor substrate 10, described metal level 21 fill described contact hole 20a, 20b and
20c also contacts with described p type island region 20d；It is also preferred that the left the material of described metal level 21 be titanium, titanium nitride, titanium silicide, tungsten, aluminum,
Metal or the compounds of metal such as silicated aluminum, copper silmin, copper or nickel；And
It is positioned at the passivation layer on described metal level 21.
Thus, this utility model discloses a kind of groove power device and manufacture method.The one that this utility model provides
Groove power device and manufacture method, by providing Semiconductor substrate；Described Semiconductor substrate is formed the first groove, second
Groove and the 3rd groove；Diapire at described first groove, the second groove and the 3rd groove forms first medium layer；Described half
Gate dielectric layer is grown on the sidewall of conductor substrate surface and described first groove, the second groove and the 3rd groove；Described first
Form encapsulant layer in groove, the second groove and the 3rd groove and fill full described first groove, the second groove and the 3rd ditch
Groove；Planarize so that described semiconductor substrate surface exposes gate dielectric layer and encapsulant layer, and described gate dielectric layer
Upper surface flush with encapsulant layer；The first groove, the second groove and the 3rd groove both sides shape in described Semiconductor substrate
Become p-well；N-type region is formed in p-well described in first groove, the second groove and the 3rd groove both sides in described Semiconductor substrate,
Encapsulant layer in described first groove forms the first doped region；Encapsulant layer in described first groove is formed
Second doped region, described first doped region and the second doped region are spaced apart, and doping type is different；Etch described first groove
In encapsulant layer formed against the sidewall of described first groove and expose the groove of described first medium layer, remain first
Doped region and the second doped region are collectively as electrostatic isolation structure；Form second dielectric layer on the semiconductor substrate, described
Second dielectric layer fills described groove；Etching described second dielectric layer to form contact hole, described contact hole extends respectively to
In first doped region of one groove, in the encapsulant layer of the second groove and in the p-well of the 3rd groove side；And connect described
P type island region is formed bottom contact hole.And then achieve electrostatic isolation structure and arrange in the semiconductor substrate, it is to avoid electrostatic isolation structure
Higher than the second groove, the situation of the 3rd groove so that semiconductor substrate surface is smooth, effectively solve due to conventional electrostatic isolation junction
The unevenness of structure makes follow-up depositing operation Step Coverage ability the best, and particularly photoetching occurs that spin coating is bad, and exposure is abnormal, platform
At rank, photoresist is the thinnest effectively as problems such as etching barrier layers, thus cannot realize device architecture, makes parameter and reliability full
The requirement of foot product.
Further, a kind of trench power device structure of the present utility model and manufacture method, can be used in include but
It is not limited in the products such as CMOS, BCD, power MOSFET, high power transistor, IGBT and Schottky.
Obviously, those skilled in the art can carry out various change and modification without deviating from this practicality to this utility model
Novel spirit and scope.So, if of the present utility model these amendment and modification belong to this utility model claim and
Within the scope of its equivalent technologies, then this utility model is also intended to comprise these change and modification.
Claims (10)
1. a groove power device, including:
Semiconductor substrate；
The first groove, the second groove and the 3rd groove being positioned in described Semiconductor substrate；
It is positioned at the first medium layer of the diapire of described first groove diapire, the second groove and the 3rd groove；
It is positioned at the grid dielectric on the sidewall of described semiconductor substrate surface and described first groove, the second groove and the 3rd groove
Layer；
It is positioned at the encapsulant layer in the first groove, the second groove and the 3rd groove, and described gate dielectric layer and encapsulant layer
Upper surface flush；
Be positioned at the first doped region in the encapsulant layer of described first groove and the second doped region, described first doped region and
Second doped region is spaced apart, and doping type is different, collectively as electrostatic isolation structure；
It is positioned in described first groove against the sidewall of described first groove and exposes the groove of described first medium layer；
It is positioned at the first groove in described Semiconductor substrate, the second groove and the p-well of the 3rd groove both sides；
It is positioned at the N-type region in p-well described in the first groove in described Semiconductor substrate, the second groove and the 3rd groove both sides；
Being positioned at the second dielectric layer in described Semiconductor substrate, described second dielectric layer fills described groove；
Contact hole, described contact hole run through described second dielectric layer and extend respectively to the first groove the first doped region in,
In the encapsulant layer of two grooves and in the p-well of the 3rd groove side；And
It is positioned at the p type island region bottom described contact hole.
2. groove power device as claimed in claim 1, it is characterised in that the degree of depth of described first groove is 0.8 μm-2.5 μ
M, width is 1 μm-10 μm, and the degree of depth of described second groove is 0.8 μm-2.5 μm, and width is 0.5 μm-2 μm, described 3rd groove
The degree of depth be 0.8 μm-2.5 μm, width is 0.1 μm-0.6 μm.
3. groove power device as claimed in claim 1, it is characterised in that described first medium layer is silica dioxide medium
Layer, one or more combinations of silicon nitride medium layer, silicon oxynitride dielectric layer.
4. groove power device as claimed in claim 1, it is characterised in that the thickness of described first medium layer is
5. groove power device as claimed in claim 1, it is characterised in that the thickness of described encapsulant layer is 0.3 μm-1 μ
m。
6. groove power device as claimed in claim 1, it is characterised in that described first doped region and the second doped region penetrate
Encapsulant layer in described first groove.
7. groove power device as claimed in claim 1, it is characterised in that the width of described groove is 0.2 μm-1.5 μm.
8. groove power device as claimed in claim 1, it is characterised in that described second dielectric layer is silica dioxide medium
Layer, silicon nitride medium layer, the one of silicon oxynitride dielectric layer or combination.
9. groove power device as claimed in claim 1, it is characterised in that described contact hole is positioned in described Semiconductor substrate
The degree of depth be 0.1 μm-0.8 μm.
10. groove power device as claimed in claim 1, it is characterised in that also include:
Being positioned at the metal level in described Semiconductor substrate, described metal level fills described contact hole；And
It is positioned at the passivation layer on described metal level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620741893.XU CN205789987U (en) | 2016-07-12 | 2016-07-12 | groove power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620741893.XU CN205789987U (en) | 2016-07-12 | 2016-07-12 | groove power device |
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| Publication Number | Publication Date |
|---|---|
| CN205789987U true CN205789987U (en) | 2016-12-07 |
Family
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| Application Number | Title | Priority Date | Filing Date |
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| CN201620741893.XU Active CN205789987U (en) | 2016-07-12 | 2016-07-12 | groove power device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113360020A (en) * | 2021-06-01 | 2021-09-07 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| CN113421829A (en) * | 2021-08-23 | 2021-09-21 | 上海南麟电子股份有限公司 | Power device structure with ESD and preparation method thereof |
-
2016
- 2016-07-12 CN CN201620741893.XU patent/CN205789987U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113360020A (en) * | 2021-06-01 | 2021-09-07 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| CN113360020B (en) * | 2021-06-01 | 2024-03-26 | 武汉天马微电子有限公司 | Display panel and display device |
| CN113421829A (en) * | 2021-08-23 | 2021-09-21 | 上海南麟电子股份有限公司 | Power device structure with ESD and preparation method thereof |
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