DE10234996B4 - Method for producing a transistor arrangement with trench transistor cells with field electrode - Google Patents

Abstract

Method for producing a transistor arrangement having at least one trench transistor cell, in which
in a process layer (2) of a semiconductor substrate (7) at least one trench (6) is introduced with a width d _T ,
the trench (6) is lined at least in sections with a first dielectric layer (321) and a field electrode (63) is arranged on portions of the trench (6) lined by the first dielectric layer (321),
the first dielectric layer (321) is formed by an etching step of portions of the trench wall not covered by the field electrode (63) and a gap formed by the field electrode (63) and the semiconductor substrate (7) up to a body height (72) of the trench (6 ), wherein the body height (72) corresponds to a transition channel zone / drift zone (71) in the semiconductor substrate (7),
a gate dielectric layer (33) is provided at portions of the trench wall,
a second dielectric layer (322) is disposed at least on the field electrode (63),
the trench (6) is filled with the material of the gate electrode (62), ...

Description

• – in eine Prozessschicht eines Halbleitersubstrats mindestens ein Graben eingebracht wird,
• – im Graben jeweils voneinander und von der Prozessschicht elektrisch isoliert eine Feldelektrode und eine Gate-Elektrode vorgesehen werden und
• – in der Prozessschicht mindestens jeweils eine Driftzone, eine Kanalzone und eine Sourcezone ausgebildet werden.

The present invention relates to a method for producing a transistor arrangement having at least one trench transistor cell with field electrode, in which

• At least one trench is introduced into a process layer of a semiconductor substrate,
• - In the trench in each case and from the process layer electrically insulated, a field electrode and a gate electrode may be provided and
• - In the process layer at least one respective drift zone, a channel zone and a source zone are formed.

Today's common U-shaped metal oxide semiconductor (UMOSFET) MOS transistors are characterized by a very low specific on-state resistance compared to older types of MOS power transistors (DMOSFET, double-diffused MOSFET, VMOSFET, V-shaped MOSFET). r _{DS, On} ) off.

there is the gate electrode of a trench transistor cell in a trench (Trench) arranged in the semiconductor substrate. The source and drain zones the trench transistor cell are in opposite directions Formed areas of the semiconductor substrate. One controlled by the gate electrode Channel section then extends in a vertical direction the semiconductor substrate. As a result, the on-resistance is through a significant increase in the Channel width per unit area clearly reduced.

A further improvement of the properties of trench MOS power transistors is achieved by the arrangement of a field electrode in the trench. Gate electrode and field electrode are arranged in the trench, that the gate electrode of the channel region and the field electrode substantially one adjoining the channel zone Opposite drift path. The field electrode shields the gate electrode against the drain zone , whereby the gate-drain capacitance greatly reduced or, at a connection of the field electrode to the source potential, in a less critical Gate-source capacitance is converted.

The 2 FIG. 10 illustrates the basic structure of a trench transistor cell of conventional trench MOS power transistors (UMOSFET). A semiconductor substrate of a trench MOS power transistor consists of an n ⁺⁺ doped base substrate 1 and one on the base substrate 1 usually epitaxially grown, n-doped process layer 2 , The basic substrate 1 forms a drain zone 10 out. The process layer (hereinafter epitaxial layer) 2 points next to the basic substrate 1 an n-doped drift zone 21 , followed by a p-doped channel zone 22 and between the channel zone 22 and the basic substrate 1 opposite substrate surface 20 an n ⁺⁺ doped source zone 23 on. In the epitaxial layer 2 are trenches 6 arranged, which can reach into the base substrate. Inside the trenches 6 are each about the drift zone 22 opposite a field electrode 63 and about the channel zone 22 opposite a gate electrode 62 arranged. The field electrode 63 is with a first dielectric layer (field plate) 321 electrically against the epitaxial layer 2 isolated. The gate electrode 62 is against the epitaxial layer 2 by means of the gate dielectric layer (gate oxide) 33 and against the field electrode 63 with a second dielectric layer 322 isolated. The source zone 23 and usually the canal zone 22 are connected to the source terminal of the trench MOS power transistor, the drain zone 10 with the drain terminal and the gate electrode 62 connected to the gate terminal.

The trenches 6 may be formed as a strip, as a grid, or in the form of other polygons, whereby strip-shaped or honeycomb-shaped trench transistor cells are formed.

The Indian 2 The illustrated trench MOS power transistor is of the n-channel MOS transistor type for the enhancement mode. In this case, the structure can also be transferred to the other three conventional embodiments (p-channel, depletion mode) of MOS transistors with correspondingly changed dopings.

At the in 2 the trench MOS power transistor shown, the current between the source terminal and the drain terminal is controlled by a potential U _GS between the gate terminal and the source terminal. If U _GS ≤ 0, then no current flows between source and drain, since the channel zone 22 blocked a carrier transport. Will the gate electrode 62 in the trench subjected to a positive voltage, so minority carriers accumulate in the p-doped channel zone 22 (Electrons) in a thin layer along the gate oxide 33 opposite the gate electrode 62 , This n-channel 221 (Inversion layer) forms a conductive transition between the source zone 23 and the drift zone 21 , its extension into the channel zone from the height of the at the gate electrode 62 depends on the applied potential. The field electrode 63 , which is connected here to the source terminal, prevents a capacitive coupling of the gate electrode 62 with the drain zone 10 or the drift zone 21 , A gate-drain capacitance C _GD is thereby transformed into a gate-source capacitance C _GS and a drain-source capacitance C _DS , whose respective influence on switching losses of the trench MOS power transistor substantially is lower.

at the optimization of the expression of trench MOS power transistors are in addition to a low gate-drain capacitance as possible Low-resistance connection of the gate electrodes, a uniform thickness the gate dielectric layer and continuous transitions of dielectric layers, in particular on corners and edges of the relief, of importance.

A method of fabricating a trench transistor device having two gate polysilicon regions is disclosed in U.S. Pat US 5,283,201 (Tsang et al.). Another procedure is from the US 5,801,417 (Tsang et al.). In both methods, trenches are introduced into a semiconductor substrate in which already doped layers for a source zone and a channel zone are formed.

From the US 6,051,468 (Hsieh) a method for producing a transistor arrangement with trench transistor cells is known in which a polysilicon layer is deposited to form the gate electrodes and then etched back into the trenches to below the silicon edge. By forming spacer masks along the trench wall above the gate electrodes, an asymmetrical formation of the source zones in the course of a oblique implantation via the vertical trench wall in the section above the gate electrodes, which is necessary to avoid a channeling effect, is avoided.

The US 6,198,127 B1 (Kocon) describes another method for producing a transistor arrangement with trench transistor cells with a gate electrode arranged in the trench.

From the WO 97/00536 A1 For example, a method for forming a doped trench wall in the course of a manufacturing process for semiconductor devices is known. In this case, a trench is formed in a semiconductor substrate by means of a mask. The trench is partially filled with a filling material and the side walls of the trench above the filling with still resting mask doped by oblique implantation.

In the WO 2001/71817 A2 (Hsieh et al.) Describes a method for producing a transistor arrangement with trench transistor cells, in which the gate oxide in the trench is first applied as a thick gate oxide layer. In an upper portion of the trench, the thick gate oxide layer is removed and then a thin gate oxide layer is deposited. The partial removal of the thick gate oxide layer or the application of the thin gate oxide layer are masked in each case by a section-wise filling of the trench.

Another known method for the production of a UMOS trench transistor is known from the US 5,998,833 (Baliga) known. The method described therein is in the 3 in the nine steps 3a to 3i shown schematically. The subfigures show 3a to 3i in each case a schematic cross section through the region of two strip-shaped trench transistor cells. These are trench transistor cells of the n-channel type with accumulation behavior.

The US 5,242,845 refers to a trench transistor cell in which the gate electrode horseshoe-like surrounds a floating silicon structure in the trench.

As in 3a is shown on a heavily n ⁺⁺ -doped base substrate 1 an epitaxial layer 2 grew up. The epitaxial layer 2 is n-doped in situ during growth.

In two successive steps are then each with the help of implantation masks starting from a base substrate 1 opposite substrate surface 20 the epitaxial layer 2 Dopants in the epitaxial layer 2 implanted and diffused out.

Each results in a horizontal to the substrate surface 20 layered source zone 23 below the substrate surface 20 and a channel zone 22 below the source zone 23 , Between the canal zone 22 and the basic substrate 1 forms the remaining portion of the epitaxial layer 2 a drift zone 21 out.

Subsequently, on the substrate surface 20 a hard mask 30 deposited. The hard mask 30 consists of an oxide layer 301 and an oxidation barrier 302 , The hard mask 30 is structured by means common in semiconductor process technology. It will be in openings 61 the hard mask exposes sections of the substrate surface. It arises in the 3c illustrated structure.

In the subsequent process step, the epitaxial layer 2 in the area of the openings 61 the hard mask 30 etched. Trenches are created 6 passing through the source zone 23 , the canal zone 22 and at least in sections also through the drift zone 21 extend. In doing so, the trenches 6 form a plurality of trenches running parallel to one another or form a lattice structure by trenches running perpendicularly or transversely thereto in a cross-sectional plane (not illustrated). Subsequently, for example, by thermal oxidation of the epitaxial layer 2 and masking by the oxidation barrier 302 , a first dielectric layer 321 (hereinafter oxide layer) formed lining the inside of the trenches.

The result of this process step is in 3d shown.

Then, doped polycrystalline silicon (polysilicon) is deposited on the structure thus formed. The thickness of the deposited layer is at least as large as half the open trench width. Thereafter, the polysilicon is etched back far enough that it is the trenches 6 only up to about one through the transition channel zone / drift zone 71 defined body height 72 crowded. The field electrode thus produced 63 is in the 3e shown.

This is followed by etching of the oxide layer 321 where the oxidation barrier 302 , usually silicon nitride, and the polysilicon of the field electrode 63 serve as etching masks. This will make the oxide layer 321 above the field electrodes 63 away from the trench wall. The result of this etching step is in 3f shown.

At the cleared sections of the trench walls, for example, a second dielectric layer is now again formed by thermal oxidation 322 which also extends across the surface of the polysilicon of the field electrode 63 extends. The second dielectric layer thus produced 322 forms a gate oxide in sections 33 , In the next step, polycrystalline silicon is again deposited on the surface of the structure and subsequently etched back until it reaches the trenches 6 about to substrate surface 20 crowded.

As in 3g is shown in this way, the gate electrode 62 above the field electrodes 63 in the trenches 6 educated. Subsequently, the exposed polysilicon of the gate electrodes 623 thermally oxidized, leaving the trenches 6 with a third dielectric layer 323 be covered.

Subsequently, the hard mask 30 removed by etching.

As in 3h is shown on the substrate surface 20 the n ⁺⁺ doped source zone 23 exposed. The gate electrodes 62 are each through the dielectric layer 323 isolated to the substrate surface.

In the further course can now on the top of the semiconductor body, a source terminal metallization 53 be applied to the source zones 23 contacted. On the back side of the semiconductor substrate becomes a drain metallization 51 applied to the drain zone 10 contacted.

The 3i illustrates trench transistor cells in cross-section as produced by the method of FIG US 5,998,833 emerge.

A disadvantage of the known methods for producing a trench MOS power transistor with gate and field electrodes arranged in trenches is, inter alia, the circumstance that subsequent process steps influence the formation of the doped zones as a result of the early doping of channel and source zones and the variability of subsequent process steps in favor of the stability of the structure of channel and source zones. Thus, for example, have transistor arrangements that are designed for low operating voltages, very small channel lengths and a correspondingly small on-resistance R _{DS (on)} on. With such transistor arrangements, even minor retroactive influences on the characteristic of the channel zone lead to a disadvantageous increase in the on-resistance R _{DS (on)} . A permissible thermal budget for production steps to be carried out according to the characteristics of the sewer zone is then very small.

Farther arise approximately in the formation of the gate oxide by thermal Oxidation at the trench inner surfaces at the same time resting on the substrate surface hard mask due to different expansion coefficients of or Hardmask and substrate materials thermomechanical stresses in areas of the substrate adjacent to the hard mask. These result in a dilution of the gate oxide generated by thermal oxidation in the hard mask adjacent areas and thus in a reduction of the dielectric strength of the gate oxide in the areas of the gate oxide adjoining the hard mask. Without further action is in the sequence a pass the gate electrode over the substrate surface at the areas of reduced withstand voltage to the source zone without loss in the specification for the dielectric strength of the transistor arrangement can not be realized.

It is therefore an object of the invention to provide a method for producing a transistor arrangement having at least one trench transistor cell with trench-arranged gate and field electrodes available, in which increases the variability of the available process steps over known methods and / or training of channel and source zones is largely independent of subsequent process steps; In this case, it should be possible to lead the gate electrode and / or the field electrode out of the trenches over the substrate surface without sacrificing the dielectric strength of the transistor arrangement, and to provide a trench transistor cell and a transistor arrangement with a low gate-source capacitance and high gate resistance. Source breakdown voltage for Will be provided.

These Task is in a method of the type mentioned by solved specified in claim 1 features. Advantageous developments the method according to the invention emerge from the subordinate claims.

According to the procedure becomes at least the source zone or channel region of trench transistor cells a transistor arrangement at the earliest after the introduction of trenches in a semiconductor substrate by implantation and activation or Diffusion formed. This prevents influencing the Source and channel structures through the previous process steps. The thermal stress on the doped source or channel zone is exposed, is significantly reduced. The variability of the mint the source or channel zones previous process steps elevated, because the thermal load implied by them is no longer a consideration limited to the doped structures becomes. As all process steps continue until the formation of the doped Zones do not enter into their thermal budget, increases the permissible Proportion of subsequent process steps at the permissible thermal budget of the doped structures and thus in turn the variability of subsequent Process steps.

The Method therefore comprises providing a semiconductor substrate, consisting of a heavily doped base substrate, which is also a drain zone forms, as well as arranged on the base substrate process layer, their opposite to the base substrate surface a sub stratoberfläche formed. Subsequently, trenches are introduced in the process layer from the substrate surface. Following that are the trenches lined with a first dielectric layer, the at least in sections on the inside of the trench oriented inner surfaces (trench wall) is arranged. In doing so, the ditch will rise up from a ditch bottom to a body height lined on the finished in the trained semiconductor substrate a transition Drift zone / channel zone is provided. In addition to this trough-like design the first dielectric layer in the lower trench region is on This section of the procedure also includes a complete lining of the trenches with the first dielectric layer or an arrangement of the first dielectric layer at least in sections on the substrate surface possible. In a further process step is in the lower trench area, which extends from the bottom of a trench to the height of the body, a field electrode from an electrically conductive Material arranged. Is the conductive material of the field electrode For example, highly doped polysilicon, so the arrangement the field electrode by depositing polysilicon in the trenches and on the substrate surface in a layer thickness that is larger as half the open trench width. Then the material is in an etching step regressed. The etching step will be canceled once the conductive material the trenches only until about body height, So the later transition Drift zone / channel zone, fills. Hereinafter, in the non-conductive material of the field electrode filled Areas of the trenches generates a gate dielectric layer on the trench walls, the in the finished semiconductor substrate arranged in the trench gate electrode of the in the semiconductor substrate arranged channel zone electrically isolated.

The Doping of the process layer is weak compared to that of the base substrate. Such a weak or low doped layer is for example produced in a known manner by an epitaxial process. In the following, the low-doped process layer is independent of their production process also referred to as epitaxial layer, as is common in the context of power transistors. But this is supposed to be a process for producing the process layer in the following by no means limited to epitaxial procedures.

is at the ditch walls of the between the body height and the substrate surface (Silicon edge) extending upper trench area still the first arranged dielectric layer whose thickness compared to the Thickness of the gate dielectric layer is usually much larger, so can the gate dielectric layer by re-etching this first dielectric layer are pronounced.

Becomes completely removes the first dielectric layer in the upper trench region, Thus, the gate dielectric layer can be formed on the trench wall in the upper trench region be provided by thermal oxidation or by deposition (hereinafter gate oxide). As a rule, at the same time as education The gate oxide is also a further dielectric layer as an oxide layer on the surface of the Field electrode pronounced.

Particularly in the case of transistor arrangements with trench transistor cells in which the field electrode is connected to the source potential, the design of the dielectric layer which electrically isolates the field electrode from the gate electrode disposed above and / or adjacent thereto becomes more important. The arrangement formed by the gate electrode, the field electrode and the intervening dielectric layer determines the gate-source capacitance of the transistor arrangement. Due to the significant reduction in the gate-drain capacitance C _GD , a reduction in the gate-source capacitance becomes more important if the product is to be used Gate charge and specific on-resistance of the transistor assembly (Figure of Merit, FOM) are further reduced. Furthermore, the dielectric isolation between the gate electrode and the field electrode must have at least one quality which makes a breakdown between the gate electrode and a field electrode connected to the source potential less likely than a breakdown between the gate electrode and the drain -Electrode.

The second dielectric layer and the gate dielectric layer are respectively provided as oxide layers. The expression of the two oxide layers at least one process step during the the two oxide layers at the same time but with different rates grow up so that the second dielectric layer thus produced on the field electrode (second oxide layer) at its thinnest point one at least 5% higher Layer thickness than the thinnest Position of the generated gate dielectric layer (Gate oxide).

One such difference in the layer thickness of gate oxide and oxide layer on the field electrode leaves For example, bring about by an oxidation process, at the feeder of oxygen compared to usual Oxidation reduced and the oxidation time at a End temperature of the oxidation process is extended.

A Reduction of the gate-source capacitance requires a higher layer thickness the dielectric layer between the gate electrode and the Source potential connected field electrode. On the other hand the layer thickness of the gate dielectric layer but given functionally, so can not be increased arbitrarily. The inventive method allows in a simple way, for example without additional masking steps, the gate dielectric layer and the dielectric layer the field electrode at the same time in a common process step train while doing the respect the layer thickness opposite Requirements to meet both layers.

The Gate oxide and the oxide layer on the field electrode become, for example deposited by means of an HDP (high density plasma) process. Such Deposition is far more prevalent on planar surfaces instead of. Leave it selectively opposed the Grabenwandung an oxide layer on the field electrode and the depositing the first dielectric layer surrounding the field electrode, whereby in a particularly simple manner, a marked difference between the Layer thickness of the gate oxide and the layer thickness of the oxide layer the field electrode can be generated.

The Gate oxide and the second oxide layer can, for example, on the Field electrode by a diffusion-limited deposition of silicon oxide be formed by means of tetraethylorthosilane (TEOS). At a With diffusion-limited deposition, silicon oxide grows preferentially on horizontal surfaces on. On the vertical trench walls that grows Silicon oxide with decreasing rate against the trench bottom, so the layer thickness of a gate oxide produced in this way in the direction of the trench bottom decreases. There is no difference in the layer thickness of the gate oxide the layer thickness of the oxide layer on the field electrode. However, it will This ensures that the thinnest point of the oxide layer not thinner on the field electrode is considered the thinnest Location of the gate oxide. With the use of TEOS can be equal layer thicknesses in the region of the gate oxide and the oxide layer on the field electrode achieve with only one common, unmasked process step.

According to the invention one on both the trench wall and the surface of the field electrode related wet oxidation. For wet oxidation during the Oxidation process fed both oxygen and hydrogen. The Presence of hydrogen leads at significantly different oxidation rates on the heavily doped Polysilicon the field electrode on the one hand and about a crystalline Silicon of the trench wall forming channel region of the semiconductor substrate on the other hand. The hydrogen content is calculated so that a significant layer thickness difference between the gate oxide and the oxide layer is achieved on the field electrode. Because the presence hydrogen generally accelerates the oxidation process takes place the wet oxidation at one compared to a conventional dry oxidation reduced Temperature between 500 degrees Celsius and 1000 degrees Celsius. By the reduced oxidation temperature becomes an increase of the oxidation layers so far slowed down that the layer thickness of the gate oxide safely inside the specified tolerance width can be realized. To this Way can be advantageously layer thickness differences between the gate oxide and the oxide layer on the field electrode by about 100% achieve. The moisture oxidation is also with a previous HDP process combined.

Another advantage of wet oxidation is the reduced extent of oxide thin spots at the edges of the oxide layers formed. Oxide thin points are formed when, as a result of different thermal expansion coefficients of two adjacent materials in the region of their interfaces, mechanical stresses build up in the materials. The mechanical stresses locally reduce the oxidation rate, so that thinning in such places grows in there Layers occur.

the Process in which the gate oxide and the oxide layer on the field electrode are pronounced in different thicknesses, followed by a dry oxidation process. This dry oxidation process occurs at a process temperature, in which the oxide layers formed start to flow viscously, whereby Oxiddünnstellen Thickened or evened out at corners and edges. The required process temperature depends on of further process parameters and is usually more than 1000 Centigrade. If such a dry oxidation process follows a wet oxidation process, For example, 75% of the gate oxide thickness becomes wet and the remainder Grown 25% dry. About that In addition, the dry oxidation process improves the quality of the silicon / silicon oxide interface, such as by the incorporation of charge carriers or the emergence of open silicon bonds is reduced. By the said combination of wet oxidation and subsequent dry oxidation So follows in a particularly advantageous manner, a simultaneous training of gate oxide and oxide layer on the field electrode in different Layer thicknesses and thickened oxide thin points. Furthermore, the Process further optimization with respect to the gate-source capacitance and the gate-drain capacitance of the transistor arrangement, because alternative forms the first dielectric layer (field plate), which is in angle and manufacturing process, without sacrificing quality Gate oxide can be realized.

The Embodiment of the invention described above to form a Gate oxide and an oxide layer on the field electrode can be simply in a method of manufacturing a transistor arrangement with trench transistor cells integrate with field electrode, since the formation of the channel and Source zones by doping takes place later and by a thermal loading in the course of the gate oxide formation is not negative can be influenced.

In a further step of the method according to the invention are in the trenches the gate electrodes arranged through the second dielectric Layer of the underlying field electrode and through the Gate dielectric layer from the surrounding semiconductor substrate electrically are isolated.

Either the channel as well as the source zone after the introduction of the trenches formed in the semiconductor substrate, since then both doped regions independently from the previous process steps.

To a particularly preferred embodiment the method according to the invention become the channel or the source zone or both after the arrangement the gate electrodes formed in the trenches. This reduces in particular the thermal load of the doped Structures by an amount different from the process steps between the Introduction of the trenches and placing the gate electrode.

One Introduction of the dopants after stamping out of the gate electrodes also advantageous because doping of the semiconductor substrate over the Trench wall suppressed becomes. This results in a homogeneous doping and better controllability of the implantation process.

To Another particularly preferred embodiment of the invention the first dielectric layer after the introduction of the trenches in one Layer thickness applied, which is greater by at least a factor of two as that of the gate oxide. Subsequently, the trenches are almost complete with filled the material of the field electrode. Are the trench transistor cells and with it the trenches in strips pronounced, this results in a plan view of the material with the Field electrode and the first dielectric layer filled trench one strip Arrangement of the field electrode in the trench center and the first dielectric layer on both sides of the field electrode.

In In a following process step, the dielectric layer is in Space between the epitaxial layer and the field electrode to a trench depth, defined by the later pronounced transition channel zone / drift zone (Body height), removed. In the by the back etching of the first dielectric layer resulting gaps now at least at the freed sections of the trench wall and the freed surfaces the field electrode formed a second dielectric layer, which forms the gate oxide at the trench walls. If the application of the second dielectric layer by thermal oxidation, so arises the dielectric layer only at the trench walls and on the exposed surface sections the field electrode.

at an arrangement of the second dielectric layer by deposition the second dielectric layer extends over the trench wall, the isolated surface sections the field electrode and over the etched back surfaces of the first dielectric layers.

The interspaces between the field electrode and the semiconductor substrate, which are lined with the dielectric layers when the trenches are in the form of a strip, is then replaced by the interstices between the field electrode and the semiconductor substrate Material of the gate electrode introduced. With this method, formation of the gate and field electrodes arranged in the trench transistor cell is achieved, in which, in an upper trench region above the body height, a field electrode arranged in the trench center is surrounded by sections of the gate electrode.

According to a further preferred embodiment of the method according to the invention, the section-wise lining of the trenches with a first dielectric layer comprises the following steps:
In a first step, the first dielectric layer is masked at least on the trench walls or unmasked applied to the entire process surface including the trench walls and masked removed.

following On the first dielectric layer, a first auxiliary layer is formed applied, wherein the material of the first auxiliary layer completely fills the trenches.

Then be Parts of the first auxiliary layer removed again, with the trenches up to the height of the body remain filled by remanent sections of the first auxiliary layer. As a result, the dielectric layer does not become the one of the remanent sections of the first auxiliary layer covered sections either removed or reduced in thickness, through Reducing the layer thickness of the first dielectric layer the Gate oxide emerges. In subsequent steps, the remanent ones are first Removed sections of the first auxiliary layer again.

There the first auxiliary layer according to the expression of the first dielectric Layer or the first dielectric layer and the gate oxide completely again is removed, the material of the etching layer alone under manufacturing technology Chosen points of view become. By a suitable choice of the material of the first auxiliary layer can in a particularly advantageous manner gradual transitions between the first dielectric Layer and the gate oxide are generated. In a realization the first auxiliary layer of a material whose etching properties a precise one Control of the etching process allow the transition the first dielectric layer to the gate oxide in the trench in particular advantageously with the transition Drift zone / channel zone in the semiconductor substrate to be matched.

In Preferably, before the reduction or the removal of first dielectric layer in not of the first auxiliary layer Covered sections a second auxiliary layer in edge areas of trenches arranged in which further arranged one of the two in the trenches Electrodes over the substrate surface guided becomes. The second auxiliary layer fills the trenches in marginal areas above the Body height and covers sections adjacent to the margins of the trenches the substrate surface.

at a subsequent removal or reduction of the first dielectric Layer remains the first dielectric layer in the second of the Auxiliary layer covered areas obtained in the original layer thickness. this makes possible in the consequence a lead out the gate electrode and / or the field electrode such during the Removing or reducing the first dielectric layer covered trenches over the substrate surface without loss in the dielectric strength of the transistor arrangement.

In a further embodiment of the method according to the invention, after removing the remanent portions of the auxiliary layer, the trenches are completely lined with the first dielectric layer, the first dielectric layer having a layer thickness d _o in an upper region of the trench facing the substrate surface and a lower region in an upper region of the trench has a layer thickness d _u , which is greater than d _o .

The introduction of the field electrode is now carried out by conformal deposition of the material of the field electrode in a layer thickness d _A which is at least half as large as the width of a space enclosed by the first dielectric layer in the lower trench region to the body height gap. As a result of the uniform growth of the material of the field electrode in the case of conformal deposition, the gap in the lower trench region is completely filled and covered by a layer of the material of the field electrode of defined thickness. By subsequent isotropic etching back of the material of the field electrode, the material of the field electrode can now be removed in a precise and thus advantageous manner just completely from the upper region of the trench.

In Advantageously, the material of the auxiliary layer is a photoresist, the one before a partial regressive the first dielectric layer subjected to a post-bake process becomes.

Farther is advantageously before the application of the auxiliary layer a bonding agent for provided the material of the auxiliary layer, after insertion the field electrode is removed again.

The mint the gate dielectric layer at portions in the upper region of the Trench wall can be formed by deposition or oxidation of silicon of the semiconductor substrate.

According to a particularly preferred embodiment of the invention, the gate dielectric layer is produced by reducing the layer thickness d _{ds of} the first dielectric layer arranged in these regions to a layer thickness d _GD . In this case, the reduction of the layer thickness takes place in neither by the auxiliary layer nor by the field electrode covered portions of the trench wall. This embodiment of the method according to the invention includes an additional application of a further dielectric layer on the field electrode.

The another dielectric layer on the field electrode may alternatively to do so in a further preferred embodiment of the invention result in a process in which the material of the further dielectric Layer also over the reduced first dielectric layer in the upper trench region above the body height is arranged. In this way, a multilayer gate oxide is formed.

alternative to the two previous embodiments of the invention the first dielectric layer is not covered by either an auxiliary layer completely removed by the field electrode covered portions of the trench inner surface, such that the gate dielectric layer is formed exclusively by sections of a applied in a subsequent process second dielectric Layer is formed.

The first and second dielectric layers are each as thermal oxide, as deposited oxide, as nitride, as oxide nitride or as a multi-layer structure feasible.

According to a further preferred embodiment of the invention, after a reduction of the layer thickness d _{dS of} the first dielectric layer or after the removal of the first dielectric layer in sections not covered by the field electrode, the field electrode is further etched back in an additional step.

Especially after removing the first dielectric layer from the upper one Range is due to the etching properties the material of the first dielectric layer, this also in the intermediate space etched back between the field electrode and the semiconductor substrate. Thereby In the middle of the trench, the field electrode is exposed. At a subsequent arrangement of the gate electrode becomes an upper portion the field electrode in a transition region between upper and lower regions of the trench from the gate electrode surround.

This results in an increased Capacity between the gate electrode and the field electrode, by the method step according to the invention on simple and advantageous way is reduced.

The Material of the gate electrode or the field electrode is customary a conductive one Polysilicon. conductive Polysilicon usually has a relatively high specificity ohmic resistance.

Of the Resistance of the gate electrode or the field electrode can by Providing a second material component of the gate electrode or field electrode be reduced. Advantageously, the further component the material of the gate and / or field electrode a metal silicide, preferably by silicidation of the polysilicon is produced.

A trench transistor cell according to the invention is arranged in a semiconductor substrate, in each of which a drain zone, a drift zone, a channel zone and a source zone are formed successively and essentially horizontally stratified. Furthermore, a trench is provided in the semiconductor substrate which is lined with a gate oxide substantially to a body height which is opposite to the transition between drift zone and channel zone in the semiconductor substrate, with a first dielectric layer and between the body height and the substrate surface. Substantially from the trench bottom to the upper edge of the first dielectric layer, a field electrode extends between approximately the body height and the substrate surface (FIG. 20 ) connects a gate electrode, wherein between the gate electrode and the field electrode, a second oxide layer is arranged. According to the invention, the second oxide layer has at least one layer thickness at each point between the field electrode and the gate electrode, which corresponds to the layer thickness at the thinnest point of the gate oxide. From the trench transistor cell according to the invention can be realized transistor arrangements such as MOS power transistors and IGBTs.

The inventive method and the trench transistor cell according to the invention are in advance related to n-channel MOS transistors shown. However, the inventive method can be as well as the trench transistor cell according to the invention also readily transferred to p-channel MOS transistors or IGBTs.

Also an integration into an IC process in a known manner, such as by a conductive Sinker in the semiconductor substrate is in a obvious to those skilled Way executable.

The invention will be explained in more detail with reference to the figures, wherein for corresponding components identical reference numerals be used.

It demonstrate:

1 the sequence of the method according to the invention according to a first embodiment,

2 a schematic diagram of a trench MOS power transistor,

3 a known method for producing a trench MOS power transistor,

4 a section of the method according to the invention according to a second embodiment,

5 a section of the method according to the invention according to a third embodiment,

6 a section of the inventive method according to a fourth embodiment and the invention,

7 a portion of the inventive method according to a fifth embodiment and

8th Embodiments for the arrangement of the gate dielectric layer and the dielectric layer between field electrode and gate electrode.

In the subfigures 1a to 1n the inventive method is shown according to a first embodiment in eleven steps. The figures each represent a cross section through the same trench transistor cell in an active cell region (left) and an edge region (right) in two mutually parallel cross-sectional planes. In the edge region are structures for contacting the field electrodes and gate arranged in trenches Electrodes provided.

According to a first embodiment of the method according to the invention is thus on an n ⁺ -doped base substrate 1 an epitaxial layer by an epitaxial process 2 generated. During the growth (in situ) of the epitaxial layer 2 this is n-doped. After that, on the base substrate 1 opposite substrate surface 20 the epitaxial layer 2 a hard mask 30 produced, for example, by depositing TEOS in a layer thickness of 400 nm. On the hard mask 30 in turn, a first photoresist layer 43 deposited and patterned by photolithographic technique. The result of the preceding process steps is in the 1a shown.

Subsequently, the hard mask 30 to the through the patterned photoresist layer 43 etched sections. The result is a textured hard mask 30 with openings 61 at which the epitaxial layer 2 , like in the 1b shown, exposed.

Subsequently, trenches 6 into the epitaxial layer 2 etched and remanent sections of the hard mask 30 or the first photoresist layer 43 away.

In 1c the structure thus obtained is shown, in which on the base substrate 1 arranged epitaxial layer 2 the trenches 6 are arranged. The trenches 6 may be a strip-like structure formed of a plurality of parallel trenches 6 , or have a network structure. A network structure is created by the fact that in a cross-sectional plane parallel to the plane shown transverse trenches the trenches shown in cross-section 6 connect with each other.

In the following process step is on by the trenches 6 structured epitaxial layer 2 a first dielectric layer 321 deposited or generated by thermal oxidation.

In 1d is that on the surface of the epitaxial layer 2 and on the inner surfaces of the trenches 6 deposited or produced dielectric layer 321 together with the epitaxial layer 2 and the basic substrate 1 shown.

This is followed in a next process step, a deposition of polycrystalline silicon (polysilicon). The deposition takes place with a layer thickness which is greater than half the trench width. Then it is ensured that the trenches 6 completely filled with the polysilicon. On the deposited in this way polysilicon 631 (Field polysilicon) becomes a second photoresist layer 44 deposited and patterned in a photolithographic process.

In 1e are those with the polysilicon 631 filled trenches 6 shown. Above the right ditch 6 '' , which represents a trench in the edge region, lies a remanent section of the photoresist layer 44 on.

At the non-remanent sections of the photoresist 44 covered portions of the polysilicon layer 631 an etching step is carried out. The etching step is stopped as soon as the material of the polysilicon layer 631 in uncovered trenches 6 back to the desired depth, typically the body height.

In 1f are remaining sections 63 . 632 the polysilicon layer 631 shown. This forms the section 63 in the left ditch 6 ' a field electrode. The section 632 in the right ditch 6 '' serves for contacting the field electrode 63 in a direction perpendicular to the cross-sectional plane, vertical extension of the left trench 6 '

In the next process step, the dielectric layer 321 etched back, taking the sections 63 and 632 forming field polysilicon forms a mask.

After the etching step, the results in 1g illustrated arrangement. The dielectric layer 321 is still in sections here 32 , below the field polysilicon 63 . 632 in front.

Then the gate dielectric layer becomes 331 (hereinafter gate oxide) deposited or produced by thermal oxidation.

In 1h is the gate dielectric layer 331 shown in sections, the surface of the epitaxial layer 2 , the polycrystalline sections 63 and 632 , as well as the isolated sections of the inner surfaces of the trenches 6 covered. In lower areas (field areas) of the trenches 6 below the body height 72 are field electrodes 63 arranged over polycrystalline structures 632 over the substrate surface 20 the epitaxial layer 2 are guided.

This is followed by the deposition of a second layer 621 made of polycrystalline silicon (gate polysilicon) 621 , This deposition also takes place in a layer thickness which is greater than half the width of the open trench. In border areas, the polycrystalline layer 621 through a third photoresist layer 45 be masked and patterned again in a photolithographic process.

In the 1i the result of this process step is shown. The gate polysilicon 621 covers the substrate surface and is partially covered by a third layer of photoresist 45 masked.

Subsequently, the gate polysilicon 621 in the non-remanent sections of the photoresist layer 45 Covered areas as far as etched back to the trenches 6 ' only just up to the substrate surface 20 (hereinafter also silicon edge) fills. Subsequently, remanent sections of the photoresist layer 45 away. The result is in the 1j shown. From the gate polysilicon 621 are gate electrodes 62 in the upper areas of the trenches 6 ' of the active cell field and other sections 622 emerged in the border area. About the sections 622 becomes the gate electrode 62 over the substrate surface 20 guided.

A first variant of the by the 1 The first exemplary embodiment of the method according to the invention shown now provides for the application of a highly conductive layer (silicide layer, eg tungsten silicide). 41 at least on the gate polysilicon 62 in front. Such a silicide layer has a very good conductivity and reduces the ohmic resistance in the supply to the gate electrodes 62 the trench transistor cells. In a second variant of the first embodiment of the method according to the invention, the gate electrode 62 with or without highly conductive component with an oxide layer, a nitride layer or a multilayer system as a diffusion barrier 42 sealed to outdiffuse dopants from the gate polysilicon 62 . 622 to prevent. The highly conductive layer 41 and / or the diffusion barrier 42 may also be elsewhere in the process, such as after reformation of the gate dielectric layer or the formation of channel and source regions 22 . 23 to be ordered.

In 1k an arrangement is shown in which both a highly conductive layer 41 , as well as the diffusion barrier 42 on the gate electrode 62 was applied. The diffusion barrier 42 is applied on the whole surface. Is shown in 1k however, only the essential part of this layer on the gate electrode 62 ,

In the next process step, the implantation of the source zone 23 and the channel zone 22 prepared. For this purpose, for example, the gate oxide 33 in sections from the substrate surface 20 removed and applied a litter or provided an implantation mask.

Like in the 1l then, in successive implantation, activation and diffusion processes, the p-channel zone is then formed 22 as well as the n ⁺⁺ -conducting source zone 23 pronounced. The untreated portion of the epitaxial layer 2 forms a drift layer 21 out. Source and channel zones 23 . 22 extend at least in each case in the active cell field between the trenches 6 ,

Alternatively, the implantation is also carried out by the relatively thin gate oxide 33 therethrough.

In the following process step, a further dielectric layer 35 deposited on the arrangement. This dielectric layer forms an intermediate oxide 35 for the isolation of the source zone, or for an improved capacitive decoupling of the field polysilicon 632 and the gate polysilicon 622 against a subsequently applied metallization level.

In the 1m is the abge on the structure different intermediate oxide layer 35 shown, the sections of the source zone 23 or the gate oxide 33 covered. In the dielectric layer 35 be openings 521 . 531 . 532 etched, which either end before the silicon layer or extend into this. There are openings 532 in which the source zone 23 is exposed, openings 531 containing the field polysilicon 532 open in sections, as well as openings 521 containing the gate polysilicon 622 Expose in sections.

Furthermore, a patterned metallization is applied over the array, which includes a source terminal metallizations 53 and a gate connection metallization 52 having. The gate connection metallization 52 contacted via vias 521 the sections 622 of the gate polysilicon. Further, in this example, the source terminal metallization contacts 53 via vias 532 the source zones 23 as well as the canal zones 22 and via vias 531 the sections 632 of the field polysilicon. This is followed by the application of a drain connection metallization 51 on the back of the semiconductor substrate, which is the basic substrate 1 that is a drain zone 10 trains, contacts.

Alternatively, the field polysilicon 632 from one of the source terminal metallization 53 contacted isolated additional field metallization.

The 2 and the 3 were already explained at the beginning.

The two 4a and 4b schematically illustrate the region of a trench transistor cell before or after a characteristic of a second embodiment of the invention method step.

This process step closes after the formation of a field electrode 63 removing or reducing the first dielectric layer 321 in not from the field electrode 63 covered areas.

These already explained method steps lead to a in the 4a illustrated arrangement. When re-etching the first dielectric layer 321 becomes the first dielectric without further action 321 also in the space between the field electrode 63 and the epitaxial layer 2 to below the surface of the field electrode 63 regressed. This will make the field electrode 63 in an upper, the substrate surface 20 facing area, partially uncovered.

According to the second embodiment of the method according to the invention, the exposed upper region of the field electrode is now in an additional process step 63 to below the substrate surface 20 oriented surface of the first dielectric layer 32 regressed. By the associated with this process step reduction of the field electrode 63 in a reduced field electrode 63 ' Advantageously, a reduction of a capacitance between the field electrode 63 ' and a subsequently formed gate electrode 62 associated.

In the 5a to 5e the method steps characterizing a third exemplary embodiment of the invention are simplified and illustrated schematically on the basis of a cross section through the region of a trench transistor cell.

The in the 5a The arrangement shown in the usual way by applying a first dielectric layer 321 on the through ditches 6 structured epitaxial layer 2 out. The following will be applied to the first dielectric layer 321 a first auxiliary layer, for example a photoresist layer 46 , applied to the trenches 6 completely filled.

In a subsequent process step, the photoresist layer 46 regressed so that remanent portions of the photoresist layer 46 only in lower areas of the trenches 6 remain as in the 5b is shown.

In the 5b is the ditch 6 of the 5a shown in two different cross-sectional planes. The cross section drawn in the left part 6 '' sets the ditch 6 in the edge region of a transistor arrangement, in which a contacting of the trench 6 arranged gate electrode and the field electrode takes place. The right cross section 6 ' sets the ditch 6 in the active region of the trench transistor cell.

In the edge area, additional coverage of the upper trench area and the adjacent substrate surface occurs 20 through a second auxiliary layer 47 ,

A body height 72 , about to the trenches 6 with the material of the photoresist layer 46 are filled corresponds to a formed in the later process flow transition between a channel and a drift zone in the semiconductor substrate. The required fill level can be realized with a material having a smaller etch rate with smaller deviations than with a high etch rate material.

In a subsequent method step, the first dielectric layer 321 in the neither through the photoresist layer 46 still through the second auxiliary layer 47 covered areas at least reduced in their layer thickness or, as in the 5c shown, completely removed. After patterning the first dielectric layer 321 become the remanent sections of the two auxiliary layers 46 . 47 away.

The result of this process step is in 5c shown. The lower part of the trench 6 ' in the active cell array is with the first dielectric layer 321 in trough-shaped lined up to the body height lower area. In the border area of the trench shown on the left 6 '' is the first dielectric layer 321 in undiminished layer thickness from the ditch 6 '' over the substrate surface 20 pulled out.

Subsequently, the field polysilicon is deposited and up to the collar of the first dielectric layer 321 etched back in the lower trench formed trough. Of the 5d , which represents the result of this process step, are sections of the first dielectric layer 321 to take that over from the field electrode 63 protrude surface formed.

In a variant of this embodiment of the method according to the invention, a method step is inserted, which comprises the first dielectric layer 321 to at least the surface of the field electrode 63 regresses.

From this process goes in the 5e shown arrangement, wherein the field electrode 63 through the first dielectric layer 321 Essentially completely fills pan formed.

In the 6a to 6e the method according to the invention is shown schematically according to a fourth embodiment with reference to a cross section through the region of a trench transistor cell.

According to the 6a First, in a known manner, a first dielectric layer 321 on the through ditches 6 structured epitaxial layer 2 applied. Subsequently, the lower areas of the trenches 6 in a known manner with egg ner auxiliary layer, such as a photoresist layer 46 masked, as in the 6b shown.

With the photoresist layer 46 as a mask, the dielectric layer 321 reduced in their layer thickness. It does not form in through the photoresist layer 46 covered portions on the substrate surface, a second dielectric layer 331 and on the inner surfaces of the trench 6 in the upper area a gate oxide 33 or an auxiliary layer. Thereafter, the photoresist layer 46 away. In the 6c shows the state of the arrangement after the previous process step.

In the following process step, a field polysilicon 631 conformed to the arrangement deposited. The deposition takes place with a layer thickness which is greater than half the width of the first dielectric layer 321 in the lower trench region formed trough and smaller than half the collar width of one through the gate oxide 33 in the upper trench area formed collar. In a conformal deposition of the field polysilicon in the layer thickness explained above results in the 6d illustrated arrangement.

In the following method step, the field polysilicon is then etched back by an amount which corresponds to the previously deposited layer thickness, supplemented by a slight overetching (overetching). The field polysilicon essentially becomes the transition of the first dielectric layer 321 to the gate oxide 33 regressed, as in the 6e shown.

In the 7a to 7d The relevant method steps of a fifth embodiment of the inventions to the invention process are illustrated by a cross section through the region of a trench transistor cell.

It is, as from the 7a shows a field polysilicon after deposition only to about the substrate surface 20 the epitaxial layer 2 regressed. The field electrode 63 then fills together with the first dielectric layer 321 the ditch 6 partially or as shown here almost completely off.

Hereinafter, the first dielectric layer 321 in through the field electrode 63 etched back to masked areas. It is, as from the 7b indicates the first dielectric layer 321 up to a body height 72 etched back and forms sections 32 which corresponds to a drift zone / channel zone transition formed in the later process sequence in the semiconductor substrate.

In this way, between the field electrode 63 and the epitaxial layer 2 forming gaps becomes one compared to the first dielectric layer 32 thin gate oxide 33 applied. The application of the gate oxide 33 can be done by deposition or by thermal oxidation. In the 7c is the state of the arrangement after the application of the gate oxide 33 shown by thermal oxidation. The layers formed by thermal oxidation sections 322 on the substrate surface 20 the epitaxial layer 2 on the inner surfaces of the trenches 6 in the upper area formed gate oxide 33 and the second dielectric layer formed on the surface of the field electrode 322 ' are from the 7c to ent to take.

In the now with the gate oxide 33 or portions of the second dielectric layer 322 ' formed in a subsequent process step, such as by deposition and etching back, the gate polysilicon is introduced, which then, as the 7d it can be seen, a the field electrode 63 in the upper trench area surrounding gate electrode 62 formed.

In the 8a to 8e The relevant process steps for the development of a gate oxide and a dielectric layer on the field electrode according to the inventive method are illustrated with reference to a cross section through the region of a trench transistor cell.

The 8a shows a ditch 6 a trench transistor cell operating in a process layer 2 , in turn, arranged on a base substrate 1 , is introduced. The ditch 6 is below about a body-drain junction 201 at a distance b to a substrate surface 20 with a first dielectric layer 32 lined. The first dielectric layer 32 isolated a field electrode 63 against one from the base substrate 1 and the process layer 2 formed semiconductor substrate 7 , As a result of etch back of the first dielectric layer 32 after introduction of the field electrode 63 is the first dielectric layer 32 to below the upper edge of the field electrode 63 regressed.

In the 8b is the in 8a shown arrangement according to a conventional thermal oxidation step. Due to the thermal oxidation in each case on the material of the lightly doped process layer 2 and the field electrode 63 Oxide layers formed. In sections, this will be a gate oxide 33 at the freed sections of the trench wall, a second oxide layer 36 on the exposed sections of the field electrode 63 and another oxide layer 322 on the substrate surface 20 educated. In this case, the gate oxide 33 , the oxide layer 36 on the field electrode 63 and the further oxide layer 322 on the substrate surface 20 in about the same thickness on. Thermal oxidation with conventional process control forms at junctions between the first dielectric layer 32 and the gate oxide 33 and between the first dielectric layer 32 and the oxide layer 36 on the field electrode 63 Oxide thin spots A, B off. Another oxide thin point C results in the oxide layer 36 on the field electrode 63 at the exposed edges of the field electrode 63 ,

The 8c represents the conditions after a wet oxidation of the in 8a Here, the oxide layer 36 on the field electrode 63 produced with a significantly higher layer thickness than the gate oxide 33 , The thinnings of the oxide thin points A, B, C are significantly lower than after a conventional thermal oxidation.

In the 8d is the state of the in the 8c shown trench transistor cell after a following on a wet oxidation dry oxidation at about 1100 degrees Celsius and a subsequent introduction of a gate electrode 62 in the ditch 6 to about the top of the trench 6 shown schematically. The thinnings of the oxide thin bodies A, B, C were markedly reduced by higher oxidation rates present there.

The 8e indicates the state of an arrangement according to 8a again, after on the field electrode 63 an oxide layer 36 generated by a HDP process. In this case, the HDP oxide formed thereby can be deposited to varying degrees. In the example shown, the HDP oxide extends beyond a lower edge of the gate oxide 33 out. In this embodiment, one against the breakdown resistance of the gate oxide 33 higher penetration resistance of the oxide layer 36 on the field electrode 63 ensured.

Examples:

at In all the examples below, the order of some steps, for example, the implantation procedures, vary. The gate electrode can consist of several layers or be reinforced in sections with a highly conductive material. In the region of the trench, the gate electrode can also over the silicon surface protrude. Also p-channel transistors and IGBTs are possible. The Process sequence can be used in an IC process in which the drain zone over an n-sinker is guided onto the substrate surface.

Example A:

• a) providing a highly doped n ⁺ substrate as a starting material.
• b) depositing an n-epitaxial layer with a dopant concentration of 1 × 10 ¹⁴ cm ^-3 to 1 × 10 ¹⁸ cm ^-3 .
• c) etching the trenches with a structured trench mask (oxide, TEOS 400 nm, photoresist). Remove the trench mask. mint of the trench as a strip or as a grid for a cell structure.
• d) applying an insulating layer of a few nm to a few microns thick. The insulation layer can also be a multilayer system (thermal Oxide, deposited oxide, nitride).
• e) depositing a field electrode, wherein the material of the field electrode doped polysilicon, silicides (tungsten silicide) and other conductive Ma may contain materials. A polysilicon is deposited with a layer thickness that is at least half the trench width, reduced by the thickness of the insulating layer.
• f) masked or unmasked back etching of the field electrode until clearly below the substrate surface of the epitaxial layer.
• g) optionally masking a portion of the insulation layer, such as through photoresist.
• h) Partial or complete Remove the insulation layer in not from the field electrode or Photoresist covered areas. Growing the gate oxide in one Thickness from a few nm to over 100 nm according to the requirements of a threshold voltage.
• i) depositing the gate electrode (doped polysilicon, silicide, Tungsten).
• j) Masked or unmasked etching back of the material of the gate electrode to below the substrate surface (Silicon top edge).
• k) optionally applying a highly conductive layer (silicide layer, Tungsten silicide) on the material of the gate electrode to increase their conductivity.
• l) Optional sealing of the gate material with an oxide layer (deposited oxide, nitride, multi-layer system) to avoid an outdiffusion of dopants.
• m) implantation, unmasked or by field oxide or its own Photographic technique masked, and subsequent outdiffusion of the channel zone.
• n) implantation of the source zone unmasked or by field oxide or masking your own photographic technique and activation or outdiffusion.
• o) deposition of a dielectric to isolate gate and source metallization.
• p) etching the contact holes. In this case, the etching on the substrate surface stop or alternatively etch through the source zone completely or almost completely.
• q) Masked implantation of the p ⁺⁺ body contact either in each cell or in stripe-like form of the cells only piecemeal. In the case of a subsequent metal deposition, both the source zone and the body contact region are connected in each cell or in each strip. When the contact hole is etched into the silicon, the implantation is optionally unmasked, provided that the source zone is not re-doped at the trench walls.
• r) deposition and structuring of the metallization.
• s) Optional deposition and structuring of the passivation.

Example B:

As Example A, however, after etching back the field electrode and a partial or complete Removing the first dielectric layer, the field electrode etched back to the gate-source capacitance to reduce. Optionally, a nitride layer is part of this the first dielectric layer. The nitride layer is structured and after etching back the field electrode as an etching mask to the etching the first dielectric layer used.

Example C:

• a) Provision of a highly doped n ⁺ base substrate.
• b) depositing an n-epitaxial layer with a dopant concentration of 1 × 10 ¹⁴ cm ^-3 to 1 × 10 ¹⁸ cm ^-3
• c) etching the trenches by means of a structured trench mask (oxide, for example TEOS 400 nm, photoresist). Remove the trench mask. The can trenches in strips or as a grid for a cell structure leads out.
• d) Applying a first dielectric layer of a few nm to a few μm Thickness. The first dielectric layer may also be a multilayer system be.
• e) optionally applying an adhesion promoter (for example nitrides).
• f) optionally applying an auxiliary layer over the Silicon edge and etch back the same into the area of the lower edge of the channel zone (p-well). Is this Material of the auxiliary layer of a photoresist, so there is a postback.
• g) Optional additional Masking a border construction.
• h) Optional etching of the oxide.
• i) Optional removal of the auxiliary layer.
• j) Optional growth of an auxiliary oxide.
• k) Optional removal of the bonding agent.
• l) depositing and masking back etching of the material of the field electrode.
• m) Optional removal of those not masked by the field electrode Sections of the first dielectric layer and growing the Gate oxide in a thickness of a few nm to over 100 nm according to the threshold voltage.
• n) depositing and doping the material of the gate electrode.
• o) Masked or unmasked etching back of the material of the gate electrode to below the silicon top edge.
• p) Optional sealing of the gate electrode with a diffusion barrier (deposited oxide, nitride, multi-layer system) to avoid outdiffusion of dopants.
• q) implantation and outdiffusion or annealing of the channel and source zone, each unmasked or by field oxide, polysilicon or their own Photographic technique masked.
• r) deposition of a dielectric to isolate gate and source metallization.
• s) etching the contact holes.
• t) deposition and patterning of the metallization.
• u) Optional deposition and structuring of the passivation.

Example D:

• a) providing an n ⁺ base substrate
• b) depositing an n-epitaxial layer having a dopant concentration of 1 × 10 ¹⁴ cm ^-3 to 1 × 10 ¹⁸ cm ^-3 .
• c) etching the trenches with a structured trench mask (oxide, for example TEOS 400 nm, photoresist), removing the trench mask. Execution of the trenches as Strip or as a grid of a cell structure.
• d) Applying a first dielectric layer of a few nm to a few μm Thickness. The first dielectric layer may also be a multilayer system be.
• e) applying an auxiliary layer (for example photoresist) over the Silicon edge and etch back the same to below the lower edge of the channel zone (p-well); is the material the auxiliary layer is a photoresist, so there is a postback.
• f) Optional additional Masking a border construction.
• g) Partial or complete etching of the first dielectric layer.
• h) removing the auxiliary layer.
• i) optionally growing an auxiliary oxide or an auxiliary layer.
• j) conformal deposition of the field electrode (polysilicon, silicide) wherein the layer thickness of the deposit is thicker than (trench width / 2 thickness of the first dielectric layer in the lower part) and thinner than (Trench width / 2 - thickness the first dielectric layer in the upper part). Masked isotropic Etchback, where the material of the field electrode by an isotropic etching back from the upper part is removed and remains in the lower part.
• k) Optional removal of the masked by the field electrode first dielectric layer and growth of the gate oxide according to the threshold voltage from a few nm to over 100 nm.
• l) depositing and doping the material of the gate electrode (typically polysilicon).
• m) Masked or unmasked etching back of the material of the gate electrode to below the silicon top edge.
• n) Optional sealing of the gate material with a diffusion barrier (deposited oxide, nitride, multilayer system).
• o) implantation and outdiffusion or healing of the canal zone and the source zone, either unmasked or by field oxide, polysilicon or masking your own photographic technique.
• p) deposition of a dielectric to isolate gate and source metallization.
• q) etching the contact holes.
• r) depositing and structuring of the metallizations.
• s) Optional switching off and structuring the passivation.

Example E:

As embodiment 1, however, the field electrode is only slightly etched back into the trench. The subsequent isotropic oxide removal undercuts the Oxide clearly. Growth of an oxide in the space between the field electrode and epitaxial layer. pour in of the material of the gate electrode. The gate electrode is thereby arranged in sections next to the field electrode.

Example F: Sub-step to fill a Trenching and formation of a dielectric layer (oxide layer) on the field electrode with simultaneous expression of a gate oxide.

• a) deposition of the material of the field electrode (phosphorus doped polysilicon)
• b) Refraining of the Material of the field electrode in the trench into about one Body height.
• c) wet chemical etching the first dielectric layer (field plate).
• d) Cleaning (HF-B, standard clean).
• e) Oxidation of gate oxide and oxide layer on the field electrode.
• f) deposition of the material of the gate electrode in the trench.
• g) Refraining of the Material of the gate electrode (polysilicon) to below the trench edge.

1

base substrate

10

drain region

2

process layer (epitaxial layer)

20

Substrate surface (silicon edge)

201

Body-drain junction

21

drift region

22

canal zone

221

channel

23

source zone

24

Body reinforcement zone

30

hard mask

301

oxide

302

oxidation barrier

32

structured first dielectric layer

321

first dielectric layer

322 322 '

second dielectric layer

323

third dielectric layer

33

gate oxide

331

Gate dielectric layer

34

field oxide

35

intermediate oxide

36

oxide on the field electrode

41

Highly conductive layer

42

diffusion barrier

43

first Photoresist layer

44

second Photoresist layer

45

third Photoresist layer

46

first Auxiliary layer (photoresist)

47

second Auxiliary layer (photoresist)

51

Drain contact metallization

52

Gate connecting metallization

53

Source contact metallization

521

contact hole

531

contact hole

532

contact hole

6 6 ', 6' '

dig (Trench)

60

Trench transistor cell

61

opening

62

Gate electrode

621

secluded Gate polysilicon

622

Gate-edge structure

63

field electrode

63 '

reduced field electrode

631

secluded Field polysilicon

632

Field-edge structure

7

Semiconductor substrate

71

crossing Canal Zone / drift region

72

Body height

b

distance

Claims (11)

Method for producing a transistor arrangement having at least one trench transistor cell, in which in a process layer ( 2 ) of a semiconductor substrate ( 7 ) at least one trench ( 6 ) is introduced with a width d _T , the trench ( 6 ) at least in sections with a first dielectric layer ( 321 ) and through the first dielectric layer ( 321 ) lined sections of the trench ( 6 ) a field electrode ( 63 ), the first dielectric layer ( 321 ) by an etching step of not by the field electrode ( 63 ) covered sections of the trench wall and from a through the field electrode ( 63 ) and the semiconductor substrate ( 7 ) formed space up to a body height ( 72 ) of the trench ( 6 ) is removed, the body height ( 72 ) with a transition channel zone / drift zone ( 71 ) in the semiconductor substrate ( 7 ) corresponds to a gate dielectric layer ( 33 ) is provided at portions of the trench wall, a second dielectric layer ( 322 ) at least on the field electrode ( 63 ), the trench ( 6 ) with the material of the gate electrode ( 62 ), where in the trench ( 6 ) on the second dielectric layer ( 322 ) a gate electrode ( 62 ) and the gate electrode ( 62 ) at the level of the canal zone ( 22 ) next to sections of the field electrode ( 63 ), in the process layer ( 2 ) at least one drift zone each ( 21 ), a channel zone ( 22 ) and a source zone ( 23 ), wherein the provision of the second dielectric layer ( 322 ) on the field electrode ( 63 ) and the gate dielectric layer ( 33 ) is carried out simultaneously and is carried out as a wet oxidation in the presence of oxygen and hydrogen, wherein the material of the field electrode ( 63 ) is oxidized at a higher rate than the material of the trench wall and a dry oxidation process is followed, so that the second dielectric layer ( 322 ) is formed at its thinnest point with a higher layer thickness than the gate dielectric layer ( 33 ) at its thinnest point as well as oxide thinnings (A, B, C) are avoided. Method according to claim 1, characterized in that both the channel zone ( 22 ) as well as the source zone ( 23 ) after the introduction of the trench ( 6 ) are formed by implantation, activation and / or diffusion. Method according to one of claims 1 to 2, characterized in that the channel zone ( 22 ) and / or the source zone ( 23 ) after arranging the gate electrode ( 62 ) be formed. Method according to one of claims 1 to 3, characterized in that the section-wise lining of the trench ( 6 ) with a first dielectric layer ( 321 ) comprises the following steps: applying the first dielectric layer at least in sections ( 321 ) on the through the trenches ( 6 ) structured substrate surface ( 20 ), Applying a first auxiliary layer ( 46 ) on the first dielectric layer ( 321 ), the trench ( 6 ) completely with the material of the first auxiliary layer ( 46 ), removing portions of the first auxiliary layer ( 46 ), the trench ( 6 ) up to body height ( 72 ) by remanent sections of the first auxiliary layer ( 46 ), at least reducing a layer thickness d _{dS of} the first dielectric layer ( 321 ) in the non-remanent sections of the first auxiliary layer ( 46 ) and removing the remanent portions of the first auxiliary layer ( 46 ). Method according to one of claims 1 to 4, characterized in that after the removal of portions of the first auxiliary layer ( 46 ) from the ditch ( 6 ) in the trench above the body height ( 72 ) a second, structured auxiliary layer ( 47 ) for contacting the gate and the field electrode ( 62 . 63 ) sections of the trench ( 6 ) and on subsequent areas of the substrate surface ( 20 ), the first dielectric layer ( 321 ) in neither of the remanent sections of the auxiliary layer ( 46 ) still from the second auxiliary layer ( 47 ) covered portions is reduced or removed in their layer thickness and then the remanent portions of the auxiliary layer ( 46 ) and the second auxiliary layer ( 47 ) are removed. Method according to one of claims 4 or 5, characterized in that after removing the remanent portions of the first auxiliary layer ( 46 ) the trenches ( 6 ) completely with the first dielectric layer ( 321 ), which are in an upper, between the body height ( 72 ) and the substrate surface ( 20 ) extending portion of the trench ( 6 ) a layer thickness d _o and in a lower region of the trench ( 6 ) has a layer thickness d _u , where d _u > d _o , and the introduction of the field electrode ( 63 ) comprises the following steps: compliant deposition of the material of the field electrode ( 63 ) in a layer thickness d _A for which the following applies: d _A > (d _T / 2 -d _u ) and d _A <(d _T / 2 -d _o ) (d _T = trench width) and isotropic etching back of the material of the field electrode ( 63 ), wherein the material at least straight from the upper region of the trench ( 6 ) Will get removed. Method according to one of claims 4 to 6, characterized in that the material of the first auxiliary layer ( 46 ) is a photoresist, which before the partial removal of the first dielectric layer ( 321 ) is subjected to a post-bake process. Method according to one of claims 4 to 7, characterized in that prior to the application of the first auxiliary layer ( 46 ) a bonding agent is applied and the adhesion promoter before the introduction of the field electrode ( 63 ) Will get removed. Method according to one of claims 1 to 8, characterized in that the first dielectric layer ( 321 . 322 ) is provided at least in sections as a thermal oxide, deposited oxide, nitride, oxynitride or as a multi-layer structure. Method according to one of claims 1 to 9, characterized in that the material of the field electrode ( 63 ) and / or the gate electrode ( 62 ) is provided at least in sections with a highly conductive component. Method according to claim 10, characterized in that that a silicide as a highly conductive component is provided.