DE10234996A1 - Production of a transistor arrangement comprises inserting a trench in a process layer of a semiconductor substrate, and forming a drift zone, a channel zone and a source zone in the process zone - Google Patents

Abstract

Production of a transistor arrangement comprises: (a) inserting a trench (6) in a process layer (2) of a semiconductor substrate (7; (b) providing a field electrode (63) and a gate electrode (62) separately from each other and electrically insulated by the process layer; and (c) forming a drift zone (21), a channel zone (22) and a source zone (23) in the process zone. Either the source zone or the channel zone is produced after the trench is formed in the semiconductor substrate. An Independent claim is also included for a trench transistor cell formed in a semiconductor substrate. Preferably after inserting the trench in the process layer, the trench is lined with a first dielectric layer and the field electrode is arranged on sections of the trench lined with the dielectric layer. After producing the field electrode, a gate dielectric layer is formed on sections of the trench wall and a second dielectric layer on the field electrode.

Description

• - in eine Prozessschicht eines Halbleitersubstrats mindestens ein Graben eingebracht wird,
• - im Graben jeweils voneinander und von der Prozessschicht elektrisch isoliert eine Feldelektrode und eine Gate- Elektrode vorgesehen werden und
• - in der Prozessschicht mindestens jeweils eine Driftzone, eine Kanalzone und eine Sourcezone ausgebildet werden.

The present invention relates to a method for producing a transistor arrangement with at least one trench transistor cell with field electrode, in which

• at least one trench is introduced into a process layer of a semiconductor substrate,
• a field electrode and a gate electrode are provided in the trench, electrically insulated from one another and from the process layer, and
• - At least one drift zone, one channel zone and one source zone are formed in the process layer.

Current trench MOS line transistors (UMOSFET, u-shaped metal oxide semiconductor field effect transistor) are distinguished from older types of MOS power transistors (DMOSFET, double diffused MOSFET, VMOSFET, v-shaped MOSFET) by a very low specific on-resistance ( r _{DS, On} ) off.

The gate electrode of a trench transistor cell is in a trench in the semiconductor substrate. The The source and drain zones of the trench transistor cell are in opposite areas of the semiconductor substrate educated. One controlled by the gate electrode The channel section then extends in a vertical direction through the semiconductor substrate. This will make the Starting resistance due to a significant increase in the channel width per Area unit significantly reduced.

Another improvement in the properties of trench MOS Power transistors is created by the arrangement of a Field electrode achieved in the trench. Gate electrode and field electrode are arranged in the trench so that the gate electrode the channel zone and the field electrode essentially one the drift section adjoining the channel zone. The field electrode shields the gate electrode from the Drain zone, which greatly reduces the gate-drain capacitance or, when the field electrode is connected to the source Potential, in a less critical gate-source capacity is converted.

FIG. 2 shows the basic structure of a trench transistor cell of conventional trench MOS power transistors (UMOSFET). A semiconductor substrate of a trench MOS power transistor consists of an n ⁺⁺ -doped base substrate 1 and one on the base substrate 1 in the Usually epitaxially grown, n-doped process layer 2 . The base substrate 1 forms a drain zone 10 . The process layer (hereinafter epitaxial layer) 2 then has an n-doped drift zone 21 on the base substrate 1 , then a p-doped channel zone 22, and an n ⁺⁺ -doped source zone between the channel zone 22 and the substrate surface 20 opposite the base substrate 1 23 on. Trenches 6 are arranged in the epitaxial layer 2 and can extend as far as the base substrate. A field electrode 63 is arranged inside the trenches 6 , approximately opposite the drift zone 22 , and a gate electrode 62 is arranged approximately opposite the channel zone 22 . The field electrode 63 is electrically insulated from the epitaxial layer 2 with a first dielectric layer (field plate) 321 . The gate electrode 62 is insulated against the epitaxial layer 2 by means of the gate dielectric layer (gate oxide) 33 and against the field electrode 63 with a second dielectric layer 322 . The source zone 23 and usually the channel zone 22 are connected to the source connection of the trench MOS power transistor, the drain zone 10 to the drain connection and the gate electrode 62 to the gate connection.

The trenches 6 can be designed as strips, as a grid, or in the form of other polygons, as a result of which strip-shaped or honeycomb-shaped trench transistor cells are formed.

The trench MOS power transistor shown in FIG. 2 is of the n-channel MOS transistor type for the enrichment operation. The structure can be transferred to the other three common embodiments (p-channel, depletion mode) of MOS transistors if the doping is changed accordingly.

In the trench MOS power transistor shown in FIG. 2, the current between the source connection and the drain connection is controlled by a potential U _GS between the gate connection and the source connection. If U _GS ≤ 0, then no current flows between the source and drain since the channel zone 22 blocks a charge carrier transport. If the gate electrode 62 is subjected to a positive voltage in the trench, minority carriers in the p-doped channel zone 22 (electrons) collect in a thin layer along the gate oxide 33 opposite the gate electrode 62 . This conductive channel 221 (inversion layer) forms a conductive transition between the source zone 23 and the drift zone 21 , the extent of which into the channel zone depends on the level of the potential applied to the gate electrode 62 . The field electrode 63 , which is connected here to the source connection, prevents capacitive coupling of the gate electrode 62 to the drain zone 10 or the drift zone 21 . A gate-drain capacitance C _GD is thereby transformed into a gate-source capacitance C _GS and a drain-source capacitance C _DS , the respective influence on switching losses of the trench MOS power transistor is significantly less.

When optimizing the expression of Trench MOS power transistors are next to a low gate-drain capacitance the lowest possible connection of the gate electrodes, a uniform thickness of the gate dielectric layer as well continuous transitions of dielectric layers, especially on Corners and edges of the relief, important.

A method of making a Trench transistor arrangement with two gate polysilicon regions is in the US 5,283,201 (Tsang et al.). Another procedure is known from US 5,801,417 (Tsang et al.). In both Processes are trenches in a semiconductor substrate introduced in the already doped layers for a source zone and a channel zone are pronounced.

Another known method for producing a UMOS trench transistor is known from US 5,998,833 (Baliga). The process described therein is illustrated schematically in Fig. 3 in the nine sub-steps a 3 to 31. The partial figures 3a to 31 each show a schematic cross section through the region of two stripe-shaped trench transistor cells. These are trench transistor cells of the n-channel type with enrichment behavior.

As shown in FIG. 3a, an epitaxial layer 2 is grown on a heavily n ⁺⁺ -doped base substrate 1 . The epitaxial layer 2 is n-doped in situ during the growth.

In two successive steps, dopants are then implanted and diffused into the epitaxial layer 2 using implantation masks, starting from a substrate surface 20 of the epitaxial layer 2 opposite the base substrate 1 .

This results in a source zone 23 layered horizontally to the substrate surface 20 below the substrate surface 20 and a channel zone 22 below the source zone 23 . The remaining portion of the epitaxial layer 2 forms a drift zone 21 between the channel zone 22 and the base substrate 1 .

A hard mask 30 is then deposited on the substrate surface 20 . The hard mask 30 consists of an oxide layer 301 and an oxidation barrier 302 . The hard mask 30 is structured using means customary in semiconductor process technology. Sections of the substrate surface are exposed in openings 61 of the hard mask. The structure shown in FIG. 3c is created.

In the subsequent method step, the epitaxial layer 2 is etched in the area of the openings 61 of the hard mask 30 . Trenches 6 are formed which extend through the source zone 23 , the channel zone 22 and at least in sections also through the drift zone 21 . The trenches 6 can form a plurality of trenches running parallel to one another or can form a lattice structure in a cross-sectional plane, not shown, by trenches running perpendicularly or transversely thereto. Then, for example by thermal oxidation of the epitaxial layer 2 and masking by the oxidation barrier 302 , a first dielectric layer 321 (hereinafter oxide layer) is formed which lines the inside of the trenches.

The result of this process step is shown in Fig. 3d.

Doped polycrystalline silicon (polysilicon) is then deposited on the structure thus formed. The thickness of the deposited layer is at least as large as half the open trench width. The polysilicon is then etched back to such an extent that it only fills the trenches 6 up to a body height 72 defined by the transition from channel zone to drift zone 71 . The field electrode 63 produced in this way is shown in FIG. 3e.

The oxide layer 321 is then etched , the oxidation barrier 302 , usually silicon nitride, and the polysilicon of the field electrode 63 serving as etching masks. As a result, the oxide layer 321 above the field electrodes 63 is removed from the trench wall. The result of this etching step is shown in FIG. 3f.

A second dielectric layer 322 , which also extends over the surface of the polysilicon of the field electrode 63 , is now again generated on the exposed sections of the trench walls by thermal oxidation, for example. The second dielectric layer 322 thus produced forms a gate oxide 33 in sections. In the next step, polycrystalline silicon is again deposited on the surface of the structure and subsequently etched back until it fills the trenches 6 approximately up to the substrate surface 20 .

In this way, as shown in FIG. 3 g, the gate electrode 62 is formed above the field electrodes 63 in the trenches 6 . The exposed polysilicon of the gate electrodes 623 is then thermally oxidized, so that the trenches 6 are covered with a third dielectric layer 323 .

The hard mask 30 is then removed by etching.

As shown in Fig. 3h, the n ⁺⁺ -type source region 23 is exposed on the substrate surface 20. The gate electrodes 62 are each insulated from the substrate surface by the dielectric layer 323 .

In the further course, a source connection metallization 53 can now be applied to the top of the semiconductor body, which contacts the source zones 23 . A drain metallization 51 , which contacts the drain zone 10 , is applied to the back of the semiconductor substrate.

FIG. 31 shows trench transistor cells in cross section as they result from the method according to US Pat. No. 5,998,833.

A disadvantage of the known methods for producing a trench MOS power transistor with gate and field electrodes arranged in trenches is, among other things, the fact that subsequent process steps influence the formation of the doped zones and the variability of subsequent process steps due to the early doping of channel and source zones in favor of the stability of the structure of channel and source zones. For example, transistor arrangements that are designed for low operating voltages have very short channel lengths and a correspondingly small switch-on resistance R _{DS (on)} . With such transistor arrangements, even minor subsequent influences on the characteristics of the channel zone lead to an adverse increase in the on-resistance R _{DS (on)} . An allowable thermal budget for manufacturing steps to be carried out after the channel zone has been formed is then very small.

Furthermore, there are about the formation of the gate oxide by thermal oxidation on the inner surface of the trench at the same time lying on the substrate surface Hard mask due to different expansion coefficients of the or the materials of the hard mask and the substrate thermomechanical stresses in adjacent to the hard mask Areas of the substrate. This results in a dilution of the Gate oxide generated by thermal oxidation in the Hard mask adjacent areas and therefore in one Reduction of the dielectric strength of the gate oxide in the Hard mask adjoining areas of the gate oxide. Without further measures are subsequently to pass the gate Electrode over the substrate surface at the areas reduced dielectric strength to the source zone without loss in the specification for the dielectric strength of the Transistor arrangement not feasible.

It is therefore an object of the invention to provide a method for Production of a transistor arrangement with at least one Trench transistor cell with gate and trench arranged To provide field electrodes, in which the Variability of the available process steps compared known methods increased and / or the formation of channel and source zones largely independent of subsequent ones Process steps is; thereby leading the gate Electrode and / or the field electrode from the trenches over the Substrate surface without sacrificing dielectric strength the transistor arrangement should be possible, and a Trench transistor cell and a transistor arrangement with low gate-source capacity and high Gate-source breakdown voltage can be provided.

This task is mentioned in a procedure of the beginning Art according to the invention in the characterizing part of Features specified 1 solved. A the Trench transistor cell solving the problem is in claim 24 and the transistor arrangement in claim 25 specified. Advantageous further developments of the invention Procedures result from the subordinate Dependent claims.

According to the method according to the invention, at least the source zone or the channel zone of trench transistor cells a transistor arrangement at the earliest after insertion of trenches in a semiconductor substrate by means of implantation and Activation or diffusion trained. So there is no an influence on the source and channel structures by the previous process steps. The thermal load, which the doped source or channel zone is exposed to significantly reduced. The variability of the expression of the Source or channel zones previous process steps increased because of the thermal stress implied by them no longer by considering the endowed Structures is limited. Since all process steps continue to to form the doped zones not in their thermal Incoming budget, the permissible proportion increases subsequent process steps on the permissible thermal budget of the endowed structures and thus in turn the variability subsequent process steps.

The method according to the invention thus includes provision a semiconductor substrate consisting of a highly doped Base substrate, which also forms a drain zone, and a process layer arranged on the base substrate, whose surface opposite the base substrate is a Forms substrate surface. Below are in the Process layer introduced trenches from the substrate surface. Then follow the trenches with a first one dielectric layer lined, at least in sections on the inner surfaces oriented towards the inside of the trench (Trench wall) is arranged. The trench is one Trench floor lined to a body height, at which in the fully formed semiconductor substrate a transition Drift zone / channel zone is provided. In addition to this tub-like Design of the first dielectric layer in the bottom The trench area is also a part of the process at this point complete lining of the trenches with the first dielectric Layer or an arrangement of the first dielectric Layer at least in sections on the substrate surface possible. In a further process step, the lower Trench area, which extends from the bottom of a trench to the Body height extends, a field electrode from an electrical conductive material arranged. Is the conductive material the Field electrode, for example, highly doped polysilicon, see above the field electrode is arranged by separating Polysilicon in the trenches and on the substrate surface in a layer thickness that is greater than half the open Grave width. Thereupon the material is subjected to an etching step regressed. The etching step is canceled as soon as the conductive material the trenches only up to about Body height, i.e. the later transition drift zone / channel zone, fills. Below is in the non-conductive material Areas of the trenches filled with field electrode Trench walls generated a gate dielectric layer, which in the manufacture the semiconductor substrate the gate arranged in the trench Electrode from that arranged in the semiconductor substrate Channel zone electrically isolated.

The doping of the process layer is weak compared to that of the base substrate. Such a weakly or lowly endowed Layer is, for example, in a known manner epitaxial process can be produced. The following is the low-doped process layer regardless of its Manufacturing process also referred to as an epitaxial layer, as in Connection with power transistors is common. But in the following a process for the production of the Process layer by no means based on epitaxial processes to be disabled.

Is on the trench walls between the body height and the substrate surface (silicon edge) extending upper Trench area still the first dielectric layer arranged whose thickness compared to the thickness of the Gate dielectric layer is usually significantly larger, the gate Dielectric layer by etching back this first dielectric layer are pronounced.

Becomes the first dielectric layer in the upper trench area completely removed, so can on the trench wall in the upper Trench area the gate dielectric layer by thermal Oxidation or by deposition (in Following gate oxide). Usually at the same time as education the gate oxide also becomes another dielectric layer as an oxide layer on the surface of the field electrode pronounced.

Particularly in the case of transistor arrangements with trench transistor cells, in which the field electrode is connected to the source potential, the configuration of the dielectric layer, which electrically isolates the field electrode from the gate electrode arranged above and / or next to it, is becoming increasingly important. The arrangement formed from the gate electrode, the field electrode and the interposed dielectric layer determines the gate-source capacitance of the transistor arrangement. The significant reduction in the gate-drain capacitance C _{GD means that} a reduction in the gate-source capacitance becomes more important if the product of the gate charge and the specific on-resistance of the transistor arrangement (Figure of Merit, FOM) is to be further reduced. Furthermore, the dielectric insulation between the gate electrode and the field electrode must have at least a quality that makes a breakdown between the gate electrode and a field electrode connected to the source potential less likely than a breakdown between the gate electrode and the drain -Electrode.

According to a particularly preferred embodiment of the inventive method are the second dielectric Layer and the gate dielectric layer each as Oxide layers are provided. The expression of the two includes Oxide layers at least one process step during which but the two oxide layers at the same time different rates grow up, so the second one generated dielectric layer on the field electrode (second oxide layer) at its thinnest point, at least 5% higher Layer thickness has the thinnest point of the generated Gate dielectric layer (gate oxide).

Such a difference in the layer thickness of gate oxide and For example, oxide layer on the field electrode by an oxidation process in which the Addition of oxygen compared to conventional oxidation processes reduced and the oxidation time at a final temperature of Oxidation process is extended.

A reduction in the gate-source capacitance requires one higher layer thickness of the dielectric layer between the Gate electrode and the one connected to source potential Field electrode. On the other hand, the layer thickness of the gate The dielectric layer, however, can be functionally predetermined not be increased arbitrarily. The method according to the invention enables it in a simple way, for example without additional masking steps, the gate dielectric layer and the dielectric layer on the field electrode at the same time in to train a common process step and thereby the conflicting requirements with regard to the layer thickness to fulfill both layers.

According to a first embodiment of the invention Formation of the gate oxide and the oxide layer on the Field electrode is made using an HDP (high density plasma) process A plasma oxide layer is deposited on the field electrode. Such a deposition is predominantly found planar surfaces instead. It can be used selectively compared to the Trench wall an oxide layer on the field electrode and the the first dielectric layer surrounding the field electrode deposit, which is a particularly simple way marked difference between the layer thickness of the gate oxide and the layer thickness of the oxide layer on the field electrode can be generated.

A second advantageous embodiment of such Method of forming the gate oxide and the second An oxide layer on the field electrode takes place through a diffusion-limited deposition of silicon oxide by means of Tetraethyl orthosilane (TEOS). With a diffusion limited Deposition grows silicon oxide preferentially on horizontal surfaces on. The silicon oxide grows on the vertical trench walls at a decreasing rate against the ditch bottom, so that the Layer thickness of a gate oxide thus generated in the direction Grabengrund decreases. But there is no difference in the Layer thickness of the gate oxide compared to the layer thickness of the Oxide layer on the field electrode. However, this way ensures that the thinnest part of the oxide layer is on the field electrode is not thinner than the thinnest point of the Gate oxide. The same can be done with the use of TEOS Layer thicknesses in the area of the gate oxide and the oxide layer on the field electrode with only one common, unmasked Achieve process step.

According to a further variant of the preferred embodiment of the method according to the invention takes place both on the Trench wall as well as on the surface of the field electrode related moisture oxidation. For moisture oxidation during of the oxidation process both oxygen and Hydrogen supplied. The presence of hydrogen leads to significantly different oxidation rates for that highly doped polysilicon of the field electrode on the one hand and about one crystalline silicon of the trench wall Channel zone of the semiconductor substrate, on the other hand. The Hydrogen content measured so that a clear Difference in layer thickness between the gate oxide and the oxide layer the field electrode is achieved. Since the presence of Hydrogen generally accelerates the oxidation process, the moist oxidation takes place with a conventional one Dry oxidation reduced temperature between 500 degrees Celsius and 1000 degrees Celsius. By the decreased Oxidation temperature becomes an increase in the oxidation layers slowed so far that the layer thickness of the gate oxide is safe can be realized within the specified tolerance range can. In this way, advantageously Differences in layer thickness between the gate oxide and the oxide layer achieve about 100% on the field electrode. The Moist oxidation is also associated with a previous HDP process combined.

Another advantage of wet oxidation is the reduced one Characterization of oxide thin points on the edges of the formed Oxide layers. Oxide thin spots arise when in succession different coefficients of thermal expansion of two neighboring materials in the area of their interfaces build up mechanical stresses in the materials. The mechanical stresses locally reduce the rate of oxidation, so that at such points thinning in layers growing there occur.

Preferably follows a process in which the gate oxide and the oxide layer on the field electrode in different thicknesses, a dry oxidation process. This dry oxidation process takes place at a Process temperature at which the oxide layers formed begin viscous to flow, causing oxide thin spots at corners and Edges are thickened or evened out. The required Process temperature depends on other process parameters and is usually more than 1000 degrees Celsius. follows such a dry oxidation process Moist oxidation process, for example, 75% of the gate oxide thickness damp and the remaining 25% grew dry. About that the dry oxidation process also improves quality the silicon / silicon oxide interface, for example by installing of load carriers or the emergence of more open ones Silicon bonds is reduced. Through the combination of Moist oxidation and subsequent dry oxidation thus follow in a particularly advantageous manner a simultaneous Formation of gate oxide and oxide layer on the field electrode in different layer thicknesses and with thickened Oxiddünnstellen. The process also enables another Optimization of gate-source capacitance and gate Drain capacitance of the transistor arrangement, as an alternative Characteristics of the first dielectric layer (field plate), the differ in angle and manufacturing process without Loss of quality of the gate oxide can be realized.

The invention described above Embodiments for forming a gate oxide and an oxide layer on the field electrode can therefore also be particularly easily in the inventive method for producing a Transistor arrangement with trench transistor cells with field electrode integrate because of the characteristics of channel and source zones by doping only later and by a thermal Impact in the course of gate oxide formation is not negative can be influenced.

In a further step of the method according to the invention the gate electrodes are arranged in the trenches through the second dielectric layer from the one below arranged field electrode and through the Gate dielectric layer electrically isolated from the surrounding semiconductor substrate are.

In a particularly preferred manner, both the channel and also the source zone after the trenches have been made Semiconductor substrate formed, since then both doped Areas independent of the previous process steps are.

According to a particularly preferred embodiment of the inventive method are the channel or the source zone or both according to the arrangement of the gate electrodes in the Trenches formed. This in particular reduces the thermal loading of the doped structures by an amount, the process steps between the introduction of the Trenches and the placement of the gate electrode is applied.

The doping is introduced after the Gate electrodes are also advantageous because doping the Semiconductor substrate is suppressed via the trench wall. This results in a homogeneous doping and a better one Controllability of the implantation process.

According to a further particularly preferred embodiment of the Invention becomes the first dielectric layer after the Introducing the trenches in a layer thickness that is at least a factor of two greater than that of Gate oxide. In the following, the trenches are almost completely covered the material of the field electrode. Are the trench Transistor cells and thus the trenches in strips pronounced, it results in a top view of the with the Material of the field electrode and the first dielectric Trench filled with a layered arrangement of the layer Field electrode in the middle of the trench and the first dielectric layer on both sides of the field electrode.

In a subsequent process step, the dielectric Layer in the space between the epitaxial layer and the field electrode to a trench depth due to the later distinction between the channel zone and the drift zone (Body height), removed. In the by etching back the first dielectric layer resulting gaps will now in each case at least on the exempted sections of the Trench wall and the exposed surfaces of the Field electrode formed a second dielectric layer to the the gate oxide forms the trench walls. Does that happen Application of the second dielectric layer by thermal Oxidation, so the dielectric layer is created exclusively on the trench walls and on the exempted ones Surface sections of the field electrode.

With an arrangement of the second dielectric layer Deposition extends the second dielectric layer over the trench wall, the exempted Surface sections of the field electrode and over the etched back Surfaces of the first dielectric layers.

In the case of the trenches with the stripes dielectric layers lined spaces between the field electrode and the semiconductor substrate then the material of the gate electrode is introduced. With This method is used to train the trench Transistor cell arranged gate and field electrodes achieved in an upper trench area above the Body height a field electrode arranged in the middle of the trench Sections of the gate electrode is surrounded.

According to a further preferred embodiment of the The method according to the invention comprises this in sections Lining the trenches with a first dielectric layer following steps:

In a first step, the first dielectric layer masked at least on the trench walls or unmasked on the entire process area including the Trench walls applied and masked removed.

Subsequently, a is on the first dielectric layer applied first auxiliary layer, the material of the first Auxiliary layer completely fills the trenches.

Then parts of the first auxiliary layer are again removed, the trenches up to body height by remanent Sections of the first auxiliary layer remain filled. In the As a result, the dielectric layer is not covered by the remanent sections of the first auxiliary layer covered Sections either removed or in their layer thickness reduced, by reducing the layer thickness of the first dielectric layer the gate oxide emerges. In Subsequent steps become the initially retentive sections removed the first auxiliary layer.

Since the first auxiliary layer after the expression of the first dielectric layer or the first dielectric layer and the gate oxide is completely removed, that can Material of the etching layer alone under manufacturing technology Aspects are chosen. By an appropriate choice of Materials of the first auxiliary layer can in particular advantageously gradual transitions between the first dielectric layer and the gate oxide are generated. at a realization of the first auxiliary layer from one material, the etching properties of which precisely control the Allow etching, the transition of the first dielectric Layer to gate oxide in the trench in a particularly advantageous Way with the transition drift zone / channel zone in Semiconductor substrate are brought into line.

In a preferred manner, before the reduction or Removal of the first dielectric layer in not from the first auxiliary layer covered sections a second Auxiliary layer arranged in edge areas of trenches in which Another one of the two arranged in the trenches Electrodes is guided over the substrate surface. The second Auxiliary layer fills the trenches in edge areas above the Body height and covered adjoining the edge areas of the trenches Sections of the substrate surface.

If the first is subsequently removed or reduced dielectric layer, the first dielectric layer remains in the areas covered by the second auxiliary layer in the original layer thickness obtained. This enables in the Follow a lead out of the gate electrode and / or Field electrode from such during removal or Reducing the first dielectric layer covered Trenches over the substrate surface without loss in the Dielectric strength of the transistor arrangement.

In a further embodiment of the method according to the invention, after the remanent sections of the auxiliary layer have been removed, the trenches are completely lined with the first dielectric layer, the first dielectric layer having a layer thickness d ₀ in an upper region of the trench facing the substrate surface and in a lower region of the trench has a layer thickness d _u which is greater than d _o .

The field electrode is then introduced by conformally depositing the material of the field electrode in a layer thickness d _A which is at least half as large as the width of an intermediate space enclosed by the first dielectric layer in the lower trench region up to the body height. Due to the uniform growth of the material of the field electrode with conformal deposition, the space in the lower trench area is completely filled and covered by a layer of the material of the field electrode of a defined thickness. Subsequent isotropic etching back of the material of the field electrode means that the material of the field electrode can now be completely and precisely removed from the upper region of the trench in a precise and therefore advantageous manner.

The material of the auxiliary layer is advantageously a Photoresist, which before a partial regression of the the first dielectric layer is subjected to a postbake process becomes.

Furthermore, before the application of the Auxiliary layer an adhesion promoter for the material of the Auxiliary layer is provided after the field electrode has been introduced is removed again.

The stamping of the gate dielectric layer on sections in the upper area of the trench wall can be separated or Oxidation of the silicon of the semiconductor substrate take place.

According to a particularly preferred embodiment of the invention, the gate dielectric layer is produced by reducing the layer thickness d _{ds of} the first dielectric layer arranged in these regions to a layer thickness d _GD . The layer thickness is reduced in those sections of the trench wall that are not covered by the auxiliary layer or by the field electrode. This embodiment of the method according to the invention includes an additional application of a further dielectric layer on the field electrode.

The further dielectric layer on the field electrode can alternatively in a further preferred embodiment the invention emerge from a process in which the Material of the further dielectric layer also over the reduced first dielectric layer in the upper trench region is placed above the body height. In this way a multilayered gate oxide is created.

As an alternative to the two previous embodiments The invention does not use the first dielectric layer in either through an auxiliary layer or through the field electrode completely covered sections of the inner trench surface, so the gate dielectric layer is only through Sections of an applied in a subsequent process second dielectric layer is formed.

The first and second dielectric layers are included in each case as thermal oxide, as deposited oxide, as Nitride, as oxide nitride or as a multilayer structure realizable.

According to a further preferred embodiment of the invention, after reducing the layer thickness d _{dS of} the first dielectric layer or after removing the first dielectric layer in sections not covered by the field electrode, the field electrode is further etched back.

Especially after removing the first dielectric Layer from the upper area is caused by the Etching properties of the material of the first dielectric layer, this also in the space between the field electrode and the Semiconductor substrate etched back. This will be in the middle the field electrode of the trench. At a Subsequent arrangement of the gate electrode becomes an upper section the field electrode in a transition area between the top and lower portion of the trench from the gate electrode surround.

This results in an increased capacity between the Gate electrode and the field electrode through the Method step according to the invention in a simple and advantageous manner is reduced.

The material of the gate electrode or the field electrode is usually a conductive polysilicon. conductive Polysilicon usually has a relatively high specific ohmic resistance.

The resistance of the gate electrode or the field electrode can by providing a second material component of the gate Electrode or field electrode can be reduced. Favorable Way the other component of the material is the gate and / or field electrode a metal silicide that preferably is generated by silicidation of the polysilicon.

A trench transistor cell according to the invention is arranged in a semiconductor substrate, in which a drain zone, a drift zone, a channel zone and a source zone are formed successively and essentially horizontally layered. Furthermore, a trench is provided in the semiconductor substrate, which is lined with a first dielectric layer and essentially between a body height, which is opposite the transition between drift zone and channel zone in the semiconductor substrate, and between the body height and the substrate surface. A field electrode extends essentially from the trench bottom to the upper edge of the first dielectric layer and is followed by a gate electrode between approximately the body height and the substrate surface ( 20 ), a second oxide layer being arranged between the gate electrode and the field electrode. According to the invention, the second oxide layer has at least one layer thickness at each point between the field electrode and the gate electrode, which corresponds to the layer thickness at the thinnest point of the gate oxide. Transistor arrangements such as MOS power transistors and IGBTs can be realized from the trench transistor cell according to the invention.

The inventive method and the inventive Trench transistor cell are in the previous Connection shown with n-channel MOS transistors. However, let the inventive method and the Trench transistor cell according to the invention also easily on p-channel MOS Transistors or IGBTs transferred.

Integration into an IC process in a known manner, through a conductive sinker in the semiconductor substrate, can be carried out in a manner which is obvious to the person skilled in the art.

The invention will be explained in more detail below with reference to the figures explained, for corresponding components identical reference numerals are used.

Show it:

Fig. 1 shows the sequence of the method according to the invention according to a first embodiment,

Fig. 2 is a schematic representation of a trench MOS power transistor,

Fig. 3 shows a known method for producing a trench power MOS transistor,

Fig. 4 shows a section of the inventive method according to a second embodiment,

Fig. 5 is a section of the inventive method according to a third embodiment,

Fig. 6 is a section of the inventive method according to a fourth embodiment of the invention and,

Fig. 7 shows a section of the inventive method according to a fifth embodiment, and

Fig. 8 embodiments of the arrangement of the gate dielectric layer and the dielectric layer between the field electrode and the gate electrode.

In the sub-figures 1a to 1n is the invention Method according to a first embodiment in eleven Process steps shown. The figures represent each a cross section through the same trench transistor cell in each case in an active cell area (left) and a border area (right) in two cross-sectional planes parallel to each other There are structures for contacting in the edge area the field electrodes arranged in trenches and Gate electrodes provided.

According to a first exemplary embodiment of the method according to the invention, an epitaxial layer 2 is thus generated on an n ⁺ -doped base substrate 1 by an epitaxial method. As the epitaxial layer 2 grows (in situ), it is n-doped. A hard mask 30 is then produced on the substrate surface 20 of the epitaxial layer 2 opposite the base substrate 1 , for example by depositing TEOS in a layer thickness of 400 nm. In turn, a first photoresist layer 43 is deposited on the hard mask 30 and structured using photolithographic technology. The result of the previous method steps is shown in Fig. 1a.

The hard mask 30 is then etched at the sections exposed by the structured photoresist layer 43 . A structured hard mask 30 is created with openings 61 , at which the epitaxial layer 2 , as shown in FIG. 1b, is exposed.

Trenches 6 are then etched into the epitaxial layer 2 and remanent sections of the hard mask 30 or the first photoresist layer 43 are removed.

In Fig. 1c, the structure thus obtained is shown, the trenches 6 are arranged in the arranged on the base substrate 1 epitaxial layer 2. The trenches 6 can have a strip-like structure, formed from a plurality of trenches 6 running in parallel, or a network structure. A network structure is created in that, in a cross-sectional plane parallel to the plane shown, transverse trenches connect the trenches 6 shown in cross section to one another.

In the following method step, a first dielectric layer 321 is deposited on the epitaxial layer 2 structured by the trenches 6 or produced by thermal oxidation.

In Fig. 1d on the surface of the epitaxial layer 2 and on the inner surfaces of the trenches 6 deposited or generated dielectric layer is shown together with the epitaxial layer 2 and the base substrate 1 321.

In a next process step, polycrystalline silicon (polysilicon) is deposited. Deposition takes place with a layer thickness that is greater than half the trench width. Then it is ensured that the trenches 6 are completely filled with the polysilicon. A second photoresist layer 44 is deposited on the polysilicon 631 (field polysilicon) deposited in this way and structured in a photolithographic process.

The trenches 6 filled with polysilicon 631 are shown in FIG. 1e. A remanent section of the photoresist layer 44 lies over the right trench 6 ″, which represents a trench in the edge region.

An etching step is carried out on the portions of the polysilicon layer 631 which are not covered by remanent portions of the photoresist 44 . The etching step is terminated as soon as the material of the polysilicon layer 631 in uncovered trenches 6 has been etched back to the desired depth, typically the body height.

The remaining sections 63 , 632 of the polysilicon layer 631 are shown in FIG. 1f. The section 63 forms a field electrode in the left trench 6 '. The section 632 in the right trench 6 ″ serves to contact the field electrode 63 in a vertical extension of the left trench 6 ′ perpendicular to the cross-sectional plane.

In the next method step, the dielectric layer 321 is etched back, the field polysilicon forming the sections 63 and 632 forming a mask.

After the etching step, the arrangement shown in FIG. 1g results. The dielectric layer 321 is still present in sections 32 below the field polysilicon 63 , 632 .

The gate dielectric layer 331 (hereinafter also gate oxide) is deposited thereon or generated by thermal oxidation.

In Fig. 1h, the gate dielectric is shown 331 in sections, the surface of the epitaxial layer 2, the polycrystalline portions 63 and 632, and the Released portions of the inner surfaces of the trenches 6 covers. In the lower areas (field areas) of the trenches 6 below the body height 72 , field electrodes 63 are arranged, which are guided over polycrystalline structures 632 over the substrate surface 20 of the epitaxial layer 2 .

A second layer 621 made of a polycrystalline silicon (gate polysilicon) 621 follows. This deposition also takes place in a layer thickness that is greater than half the open trench width. In edge areas, the polycrystalline layer 621 can again be masked and structured by a third photoresist layer 45 in a photolithographic process.

In the Fig. 11 shows the result of this process step. The gate polysilicon 621 covers the substrate surface and is partially masked by a third photoresist layer 45 .

The gate polysilicon 621 is then etched back in the areas not covered by remanent sections of the photoresist layer 45 to such an extent that it only fills the trenches 6 'just up to the substrate surface 20 (hereinafter also referred to as the silicon edge). Subsequently, remanent sections of the photoresist layer 45 are removed. The result is shown in Fig. 1j. The gate polysilicon 621 has been used to produce gate electrodes 62 in the upper regions of the trenches 6 ′ of the active cell field and further sections 622 in the edge region. The gate electrode 62 is guided over the substrate surface 20 via the sections 622 .

A first variant of the first exemplary embodiment of the method according to the invention represented by FIG. 1 now provides for the application of a highly conductive layer (silicide layer, for example tungsten silicide) 41 at least on the gate polysilicon 62 . Such a silicide layer has a very good conductivity and reduces the ohmic resistance in the supply to the gate electrodes 62 of the trench transistor cells. In a second variant of the first exemplary embodiment of the method according to the invention, the gate electrode 62 is sealed with or without a highly conductive portion with an oxide layer, a nitride layer or a multilayer system as a diffusion barrier 42 in order to prevent dopants from diffusing out of the gate polysilicon 62 , 622 , The highly conductive layer 41 and / or the diffusion barrier 42 can also be arranged at another point in the method, for example after the gate dielectric layer has re-formed or the channel and source zones 22 , 23 have been formed.

In Fig. 1k, an arrangement is shown in which both a highly conductive layer 41, and the diffusion barrier 42 was applied on the gate electrode 62. The diffusion barrier 42 is applied to the whole area per se. However 1k is shown in Fig., Only the functionally essential part of this layer on the gate electrode 62.

In the next process step, the implantation of the source zone 23 and the channel zone 22 is prepared. For this purpose, for example, the gate oxide 33 is removed in sections from the substrate surface 20 and a scatter oxide is applied or an implantation mask is provided.

As shown in FIG. 11, the p-type channel zone 22 and the n ⁺⁺ -type source zone 23 are then formed in successive implantation, activation and diffusion processes. The section of the epitaxial layer 2 that has remained untreated forms a drift layer 21 . Source and channel zones 23 , 22 each extend at least in the active cell field between the trenches 6 .

Alternatively, the implantation also takes place through the relatively thin gate oxide 33 .

In the following method step, a further dielectric layer 35 is deposited on the arrangement. This dielectric layer forms an intermediate oxide 35 for isolating the source zone or for an improved capacitive decoupling of the field polysilicon 632 and the gate polysilicon 622 against a subsequently applied metallization level.

In Fig. 1m, the deposited structure to the intermediate oxide layer 35 is shown, which sections the source region 23 and the gate oxide 33 covers. Openings 521 , 531 , 532 are etched in the dielectric layer 35 , which either end in front of or extend into the silicon layer. Openings 532 are created in which the source zone 23 is exposed, openings 531 which open the field polysilicon 532 in sections, and openings 521 which expose the gate polysilicon 622 in sections.

Furthermore, a structured metallization is applied over the arrangement, which has a source connection metallization 53 and a gate connection metallization 52 . The gate connection metallization 52 contacts the sections 622 of the gate polysilicon via vias 521 . Furthermore, in this example, the source connection metallization 53 contacts the source zones 23 and the channel zones 22 via vias 532 and the sections 632 of the field polysilicon via vias 531 . This is followed by the application of a drain connection metallization 51 on the rear side of the semiconductor substrate, which contacts the base substrate 1 , which forms a drain zone 10 .

Alternatively, the field polysilicon 632 is contacted by an additional field metallization isolated from the source connection metallization 53 .

The FIG. 2 and FIG. 3 have already been explained in the introduction.

Both Fig. 4a and Fig. 4b schematically represent the region of a trench transistor cell is before or after a characteristic of a second embodiment of the invention process step.

After the formation of a field electrode 63, this method step follows the removal or reduction of the first dielectric layer 321 in areas not covered by the field electrode 63 .

These method steps already explained lead to an arrangement shown in FIG. 4a. When etching back the first dielectric layer 321 , the first dielectric 321 is also re-formed in the space between the field electrode 63 and the epitaxial layer 2 below the surface of the field electrode 63 without further measures. As a result, the field electrode 63 is partially exposed in an upper region facing the substrate surface 20 .

According to the second exemplary embodiment of the method according to the invention, the exposed upper region of the field electrode 63 is now formed back into the surface of the first dielectric layer 32 oriented toward the substrate surface 20 in an additional method step. By associated with this step, reduction of the field electrode 63 in a reduced field electrode 63 'is advantageously a reduction of a capacitance between the field electrode 63' and accompanied by a subsequently formed gate electrode 62nd

In FIGS. 5a to FIG. 5e, a third embodiment of the invention, the characterizing process steps are simplified with reference to a cross section through the region of a trench transistor cell shown schematically.

The arrangement shown in FIG. 5a is produced in the usual way by applying a first dielectric layer 321 to the epitaxial layer 2 structured by trenches 6 . Subsequently, a first auxiliary layer, for example a photoresist layer 46 , is applied to the first dielectric layer 321 , which completely fills the trenches 6 .

In a subsequent method step, the photoresist layer 46 is re-formed, so that remanent sections of the photoresist layer 46 remain only in the lower regions of the trenches 6 , as shown in FIG. 5b.

In Fig. 5b, the trench 6 is FIG. Shown in two different cross-sectional planes 5a. The cross section 6 ″ drawn in the left part represents the trench 6 in the edge region of a transistor arrangement in which the gate electrode arranged in the trench 6 and the field electrode are contacted. The right cross section 6 ′ represents the trench 6 in the active region of the trench Transistor cell.

In the edge region, the upper trench region and the adjacent substrate surface 20 are additionally covered by a second auxiliary layer 47 .

A body height 72 , approximately up to which the trenches 6 are filled with the material of the photoresist layer 46 , corresponds to a transition between a channel and a drift zone in the semiconductor substrate which is formed later in the process. The required fill level can be realized with a material with a lower etching rate with less deviations than with a material with a high etching rate.

In a subsequent method step, the first dielectric layer 321 is at least reduced in its layer thickness in the areas neither covered by the photoresist layer 46 nor by the second auxiliary layer 47 or, as shown in FIG. 5c, completely removed. After the structuring of the first dielectric layer 321 , the remanent sections of the two auxiliary layers 46 , 47 are removed.

The result of this process step is shown in FIG. 5c. The lower region of the trench 6 'in the active cell field is lined with the first dielectric layer 321 in the form of a trough in the lower region which extends to the body height. In the edge region of the trench 6 "shown on the left, the first dielectric layer 321 is pulled out of the trench 6 " in undiminished layer thickness as far as over the substrate surface 20 .

The field polysilicon is subsequently deposited and etched back until the collar of the trough formed by the first dielectric layer 321 in the lower trench region. FIG. 5d, illustrating the result of this process step is to remove portions of the first dielectric layer 321, which protrude beyond the field formed by the electrode 63 surface.

In a variant of this exemplary embodiment of the method according to the invention, a method step is inserted which reforms the first dielectric layer 321 down to at least the surface of the field electrode 63 .

This arrangement results in the arrangement shown in FIG. 5e, in which the field electrode 63 essentially completely fills the trough formed by the first dielectric layer 321 .

In Figs. 6a to Fig. 6e, the inventive method is schematically illustrated according to a fourth embodiment with reference to a cross section through the area of a trench transistor cell.

According to FIG. 6 a, a first dielectric layer 321 is first applied in a known manner to the epitaxial layer 2 structured by trenches 6 . The lower regions of the trenches 6 are then masked in a known manner with an auxiliary layer, for example a photoresist layer 46 , as shown in FIG. 6b.

With the photoresist layer 46 as a mask, the dielectric layer 321 is reduced in its layer thickness. In this case, a second dielectric layer 331 forms on the substrate surface in portions not covered by the photoresist layer 46 and a gate oxide 33 or an auxiliary layer on the inner surfaces of the trench 6 in the upper region. The photoresist layer 46 is then removed. In FIG. 6c of the state of the arrangement is shown according to the preceding process step.

In the following method step, a field polysilicon 631 is deposited onto the arrangement in conformity. The deposition takes place with a layer thickness that is greater than half the width of the trough formed by the first dielectric layer 321 in the lower trench region and smaller than half the collar width of a collar formed by the gate oxide 33 in the upper trench region. With a conformal deposition of the field polysilicon in the layer thickness explained above, the arrangement shown in FIG. 6d results.

In the following process step, the field polysilicon is now etched back by an amount that corresponds to the previously deposited layer thickness, supplemented by a slight overetch. The field polysilicon is essentially regressed until the transition of the first dielectric layer 321 to the gate oxide 33 , as shown in FIG. 6e.

In FIGS. 7a to Fig. 7d the relevant process steps of a fifth embodiment of the inventive method shown by way of a cross section through the region of a trench transistor cell.

As can be seen from FIG. 7 a, a field polysilicon is only re-formed after deposition up to approximately the substrate surface 20 of the epitaxial layer 2 . The field electrode 63 then together with the first dielectric layer 321 partially or almost completely fills the trench 6 as shown here.

The first dielectric layer 321 is subsequently etched back in the regions masked by the field electrode 63 . As can be seen from FIG. 7b, the first dielectric layer 321 is etched back up to a body height 72 and forms sections 32 which correspond to a drift zone / channel zone transition in the semiconductor substrate which is formed in the later process sequence.

A gate oxide 33, which is thin in comparison to the first dielectric layer 32, is applied in the spaces formed in this way between the field electrode 63 and the epitaxial layer 2 . The gate oxide 33 can be applied by deposition or by thermal oxidation. FIG. 7c shows the state of the arrangement after the gate oxide 33 has been applied by thermal oxidation. The layers 322 formed in sections by thermal oxidation on the substrate surface 20 of the epitaxial layer 2 , the gate oxide 33 formed on the inner surfaces of the trenches 6 in the upper region and the second dielectric layer 322 'formed on the surface of the field electrode are shown in FIG. 7c remove.

In a subsequent process step, for example by deposition and etching back, the gate polysilicon is introduced into the troughs now formed with the gate oxide 33 or sections of the second dielectric layer 322 ', which then, as can be seen from FIG. 7d, one of the Forms field electrode 63 in the upper trench region enclosing gate electrode 62 .

In FIGS. 8a to Fig. 8e the relevant method steps for expression of a gate oxide and a dielectric layer on the field electrode can be prepared according to the methods of the invention with reference to a cross section through the region of a trench transistor cell.

The Fig. 8a shows a trench 6 of a trench-transistor cell which is introduced into a process layer 2, in turn, arranged on a base substrate 1. The trench 6 is lined with a first dielectric layer 32 below a body-drain junction 201 at a distance b from a substrate surface 20 . The first dielectric layer 32 insulates a field electrode 63 from a semiconductor substrate 7 formed from the base substrate 1 and the process layer 2 . As a result of etching back the first dielectric layer 32 after the field electrode 63 has been introduced, the first dielectric layer 32 is formed back to below the upper edge of the field electrode 63 .

FIG. 8b shows the arrangement shown in FIG. 8a after a conventional thermal oxidation step. Due to the thermal oxidation, oxide layers are formed on the material of the lightly doped process layer 2 and the field electrode 63 . In sections, a gate oxide 33 is formed on the free sections of the trench wall, a second oxide layer 36 on the free sections of the field electrode 63 and a further oxide layer 322 on the substrate surface 20 . The gate oxide 33 , the oxide layer 36 on the field electrode 63 and the further oxide layer 322 on the substrate surface 20 have approximately the same layer thickness. In a thermal oxidation process with a conventional guide 63 Oxiddünnstellen A, B form at transitions between the first dielectric layer 32 and the gate oxide 33 as well as between the first dielectric layer 32 and the oxide layer 36 on the field electrode. Another oxide thin point C results in the oxide layer 36 on the field electrode 63 at the exposed edges of the field electrode 63 .

FIG. 8c shows the conditions after wet oxidation of the arrangement shown in FIG. 8a. The oxide layer 36 is produced on the field electrode 63 with a significantly higher layer thickness than the gate oxide 33 . The thinnings of the oxide thin points A, B, C are significantly lower than after a conventional thermal oxidation.

In Fig. 8d is the state of the Fig. 8c shown trench transistor cell of a subsequent a wet oxidation dry oxidation at about 1100 degrees Celsius and a subsequent introduction of a gate electrode 62 in the trench 6 to about the upper edge of the trench 6 shown schematically. The thinning of the oxide thin points A, B, C was markedly reduced by the higher oxidation rates present there.

FIG. 8e shows the state of an arrangement according to FIG. 8a after an oxide layer 36 has been produced on the field electrode 63 by an HDP process. The HDP oxide formed can be deposited to different extents. In the example shown, the HDP oxide extends beyond a lower edge of the gate oxide 33 . In this embodiment, a higher breakdown security of the oxide layer 36 on the field electrode 63 is ensured than the breakdown security of the gate oxide 33 .

Examples

In all of the following examples, the order can be a few steps, for example the implantation processes, vary. The gate electrode can consist of several layers or in sections with a highly conductive material be reinforced. The gate electrode can be in the area of the trench also protrude beyond the silicon surface. Also p-channel Transistors and IGBTs are possible. The process sequence can be in an IC process are used in which the drain zone over an n-sinker is led onto the substrate surface.

Example A

• a) Providing a highly doped n ⁺ substrate as a starting material.
• b) depositing an n-epitaxial layer with a dopant concentration of 1 × 10 ¹⁴ cm ^-3 to 1 × 10 ¹⁸ cm ^-3 .
• c) etching the trenches with a structured trench mask (Oxide, TEOS 400 nm, photoresist). Removing the Trench mask. Form the trench as a strip or as Grid for a cell structure.
• d) applying an insulation layer from a few nm to a few µm thick. The insulation layer can also a multilayer system (thermal oxide, deposited Oxide, nitride).
• e) depositing a field electrode, the material of the Field electrode doped polysilicon, silicides (Tungsten silicide) and other conductive materials can. A polysilicon is used with a layer thickness deposited that are at least half the trench width, reduced by the thickness of the insulation layer.
• f) Masked or unmasked etching back of the field electrode to well below the substrate surface of the epitaxial layer.
• g) optionally masking a part of the insulation layer, for example through photoresist.
• h) Partial or complete removal of the Insulation layer in not from the field electrode or photoresist covered areas. Growing the gate oxide in one Thickness from a few nm to over 100 nm corresponding to the Requirements for a threshold voltage.
• i) depositing the gate electrode (doped polysilicon, Silicide, tungsten silicide).
• j) Masked or unmasked etching back of the material the gate electrode to below the substrate surface (Silicon top edge).
• k) Optional application of a highly conductive layer (Silicide layer, tungsten silicide) on the material of the Gate electrode to increase its conductivity.
• l) Optional sealing of the gate material with a Oxide layer (deposited oxide, nitride, multi-layer system) to avoid doping diffusion.
• m) implantation, unmasked or by field oxide or a masked own photo technique, and subsequent Diffusion of the canal zone.
• n) implantation of the source zone unmasked or by Masked field oxide or your own photo technology and Activation or diffusion.
• o) depositing a dielectric for the isolation of gate and source metallization.
• p) etching the contact holes. The etching on the Stop substrate surface or alternatively the Fully or almost completely etch through the source zone.
• q) Masked implantation of the p ⁺⁺ body contact either in each cell or, if the cells are strip-like, only piece by piece. In the case of a subsequent metal deposition, both the source zone and the body contact area in each cell or in each strip are connected. If the contact hole is etched into the silicon, the implantation is optionally carried out unmasked, provided that the source zone on the trench walls is not redoped.
• r) depositing and structuring the metallization.
• s) Optional separation and structuring of the passivation.

Example B

Like example A, but after etching back the Field electrode and a partial or complete removal the first dielectric layer, the field electrode etched back again to increase the gate-source capacitance to reduce. A nitride layer is optionally part of the first dielectric layer. The nitride layer is structured and after the etching back of the field electrode as Etching mask used for etching the first dielectric layer.

Example C

• a) Provision of a highly doped n ⁺ base substrate.
• b) depositing an n-epitaxial layer with a dopant concentration of 1 × 10 ¹⁴ cm ^-3 to 1 × 10 ¹⁸ cm ^-3
• c) etching the trenches using a structured Trench mask (oxide, e.g. TEOS 400 nm, photoresist). Remove the trench mask. The trenches striped or as a grid for a cell structure executed.
• d) applying a first dielectric layer of a few nm to a few µm thickness. The first dielectric Layer can also be a multi-layer system.
• e) Optional application of an adhesion promoter (for example Nitrides).
• f) Optional application of an auxiliary layer over the Silicon edge and etch back to the area the lower edge of the channel zone (p-tub). Is this Material of the auxiliary layer is a photoresist, so a Postback.
• g) Optional additional masking of an edge construction.
• h) Optional etching of the oxide.
• i) Optional removal of the auxiliary layer.
• j) Optional growth of an auxiliary oxide.
• k) Optional removal of the adhesion promoter.
• l) depositing and masking back the material of the Field electrode.
• m) Optional removal of not through the field electrode masked portions of the first dielectric layer and growing the gate oxide to a thickness of a few nm to over 100 nm according to the threshold voltage.
• n) depositing and doping the material of the gate Electrode.
• o) Masked or unmasked etching back of the material the gate electrode to below the top edge of silicon.
• p) Optional sealing of the gate electrode with a Diffusion barrier (deposited oxide, nitride, Multilayer system) to avoid diffusion of Dopants.
• q) implantation and diffusion or healing of the canal and source zone, each unmasked or by field oxide, Masked polysilicon or your own photo technology.
• r) depositing a dielectric for the isolation of gate and source metallization.
• s) etching the contact holes.
• t) depositing and structuring the metallization.
• u) Optional separation and structuring of the passivation.

Example D

• a) Providing an n ⁺ base substrate
• b) depositing an n-epitaxial layer with a dopant concentration of 1 × 10 ¹⁴ cm ^-3 to 1 × 10 ¹⁸ cm ^-3 .
• c) etching the trenches with a structured trench mask (Oxide, for example TEOS 400 nm, photoresist), remove the trench mask. Execution of the trenches as strips or as a grid of a cell structure.
• d) applying a first dielectric layer of a few nm to a few µm thickness. The first dielectric Layer can also be a multi-layer system.
• e) application of an auxiliary layer (for example photoresist) to over the silicon edge and etch it back to under the lower edge of the channel zone (p-tub); is this Material of the auxiliary layer is a photoresist, so a Postback.
• f) Optional additional masking of an edge construction.
• g) Partial or complete etching of the first dielectric layer.
• h) removing the auxiliary layer.
• i) Optional growth of an auxiliary oxide or Auxiliary layer.
• j) conformal deposition of the field electrode (polysilicon, Silicide), the layer thickness of the deposition being thicker is as (trench width / 2 - thickness of the first dielectric Layer in the lower part) and thinner than (trench width / 2 - Thickness of the first dielectric layer in the upper part). Masked isotropic etching back, the material of the Field electrode by isotropic etching back from the the upper part is removed and remains in the lower part.
• k) Optional removal of not through the field electrode masked first dielectric layer and growth of the gate oxide according to the threshold voltage of a few nm up to over 100 nm.
• l) depositing and doping the material of the gate electrode (typically polysilicon).
• m) Masked or unmasked etching back of the material the gate electrode to below the top edge of silicon.
• n) Optional sealing of the gate material with a Diffusion barrier (deposited oxide, nitride, Multilayer system).
• o) implantation and diffusion or healing of the Channel zone and the source zone, each unmasked or through Field oxide, polysilicon or your own photo technology masked.
• p) depositing a dielectric for the isolation of gate and source metallization.
• q) etching the contact holes.
• r) depositing and structuring the metallizations.
• s) Optional switching off and structuring of the passivation.

Example E

Like embodiment 1, but the field electrode only little etched back into the trench. The subsequent isotropic Oxide removal significantly undercuts the oxide. Growing one Oxides in the space between the field electrode and epitaxial layer. Filling the material of the gate electrode. The gate electrode is in sections next to the Field electrode arranged.

Example F

• a) Abscheidung des Materials der Feldelektrode (Phosphordotiertes Polysilizium)
• b) Rückätzen des Materials der Feldelektrode in den Graben hinein bis etwa zu einer Bodyhöhe.
• c) Feuchtchemisches Ätzen der ersten dielektrischen Schicht (Feldplatte).
• d) Reinigung (HF-B, Standard clean).
• e) Oxidation von Gateoxid und Oxidschicht auf der Feldelektrode.
• f) Abscheidung des Materials der Gate-Elektrode in den Graben.
• g) Rückätzen des Materials der Gate-Elektrode (Polysilizium) bis unter die Grabenkante.

Bezugszeichenliste 1 Grundsubstrat
10 Drainzone
2 Prozessschicht (epitaktische Schicht)
20 Substratoberfläche (Siliziumkante)
201 Body-Drainübergang
21 Driftzone
22 Kanalzone
221 Kanal
23 Sourcezone
24 Bodyverstärkungszone
30 Hartmaske
301 Oxidschicht
302 Oxidationsbarriere
32 strukturierte erste dielektrische Schicht
321 erste dielektrische Schicht
322, 322' zweite dielektrische Schicht
323 dritte dielektrische Schicht
33 Gateoxid
331 Gate-Dielektrikumsschicht
34 Feldoxid
35 Zwischenoxid
36 Oxidschicht auf der Feldelektrode
41 Hochleitfähige Schicht
42 Diffusionsbarriere
43 erste Photolackschicht
44 zweite Photolackschicht
45 dritte Photolackschicht
46 erste Hilfsschicht (Photolack)
47 zweite Hilfsschicht (Photolack)
51 Drain-Anschlussmetallisierung
52 Gate-Anschlussmetallisierung
53 Source-Anschlussmetallisierung
521 Kontaktloch
531 Kontaktloch
532 Kontaktloch
6, 6', 6" Graben (Trench)
60 Trench-Transistorzelle
61 Öffnung
62 Gate-Elektrode
621 abgeschiedenes Gate-Polysilizium
622 Gate-Randstruktur
63 Feldelektrode
63' reduzierte Feldelektrode
631 abgeschiedenes Feld-Polysilizium
632 Feld-Randstruktur
7 Halbleitersubstrat
71 Übergang Kanalzone/Driftzone
72 Bodyhöhe
b Abstand
Partial step for filling a trench and forming a dielectric layer (oxide layer) on the field electrode with simultaneous formation of a gate oxide.

• a) deposition of the material of the field electrode (phosphorus-doped polysilicon)
• b) etching back the material of the field electrode into the trench up to a body height.
• c) Wet chemical etching of the first dielectric layer (field plate).
• d) Cleaning (HF-B, standard clean).
• e) oxidation of gate oxide and oxide layer on the field electrode.
• f) deposition of the material of the gate electrode in the trench.
• g) etching back the material of the gate electrode (polysilicon) to below the edge of the trench.

REFERENCE SIGNS LIST 1 basic substrate
10 drain zone
2 process layer (epitaxial layer)
20 substrate surface (silicon edge)
201 body-drain junction
21 drift zone
22 channel zone
221 channel
23 source zone
24 body reinforcement zone
30 hard mask
301 oxide layer
302 oxidation barrier
32 structured first dielectric layer
321 first dielectric layer
322 , 322 'second dielectric layer
323 third dielectric layer
33 gate oxide
331 gate dielectric layer
34 field oxide
35 intermediate oxide
36 oxide layer on the field electrode
41 Highly conductive layer
42 diffusion barrier
43 first photoresist layer
44 second photoresist layer
45 third photoresist layer
46 first auxiliary layer (photoresist)
47 second auxiliary layer (photoresist)
51 Drain connection metallization
52 Gate connection metallization
53 Source connection metallization
521 contact hole
531 contact hole
532 contact hole
6 , 6 ', 6 "trench
60 trench transistor cell
61 opening
62 gate electrode
621 deposited gate polysilicon
622 gate edge structure
63 field electrode
63 'reduced field electrode
631 deposited field polysilicon
632 field edge structure
7 semiconductor substrate
71 Transition channel zone / drift zone
72 body height
b distance

Claims (25)

1. A method for producing a transistor arrangement with at least one trench transistor cell, in which
at least one trench ( 6 ) is introduced into a process layer ( 2 ) of a semiconductor substrate ( 7 ),
A field electrode ( 63 ) and a gate electrode ( 62 ) are provided in the trench ( 6 ) in each case electrically insulated from one another and from the process layer ( 2 ) and
at least one drift zone ( 21 ), one channel zone ( 22 ) and one source zone ( 23 ) are formed in the process layer ( 2 ),
characterized in that
at least either the source zone ( 23 ) or the channel zone ( 22 ) are formed after the trench ( 6 ) has been introduced into the semiconductor substrate ( 7 ). 2. The method according to claim 1, characterized in that after introducing the trench ( 6 ) with a width d _T into the process layer ( 2 ) the trench ( 6 ) is lined at least in sections with a first dielectric layer ( 321 ) and through it first dielectric layer ( 321 ) lined sections of the trench ( 6 ) the field electrode ( 63 ) is arranged. 3. The method according to claim 2, characterized in that after the production of the field electrode ( 63 ) a gate dielectric layer ( 33 ) on sections of the trench wall and a second dielectric layer ( 322 ) are arranged at least on the field electrode ( 63 ) and in the trench ( 6 ) the gate electrode ( 62 ) is provided on the second dielectric layer ( 322 ). 4. The method according to claim 3, characterized in that the second dielectric layer ( 322 ) on the field electrode ( 63 ) and the gate dielectric layer ( 33 ) are each provided as oxide layers and the arrangement of the oxide layer ( 322 ) on the field electrode ( 63 ) and the gate oxide ( 33 ) includes at least one process step in which the oxide layer ( 322 ) on the field electrode ( 63 ) is formed at its thinnest point at least as thick as the gate oxide ( 33 ) at its thinnest point. 5. The method according to claim 4, characterized in that the process step is carried out at least as an HDP process, in the course of which on the field electrode ( 63 ) or on the field electrode ( 63 ) and on the field electrode ( 63 ) surrounding free sections the first dielectric layer ( 321 ) the oxide layer ( 322 ) is deposited, which is formed at its thinnest point by at least 5% stronger than the gate oxide ( 33 ) at its thinnest point. 6. The method according to claim 4, characterized in that the process step as a diffusion-limited deposition of silicon oxide using tetraethyl orthosilane is, with the silicon oxide on the trench walls on average is applied in a thinner layer thickness than on the Field electrode. 7. The method according to any one of claims 4 or 5, characterized in that the process step is carried out as a wet oxidation in the presence of oxygen and hydrogen and the material of the field electrode ( 63 ) is oxidized at a higher rate than the material of the trench wall. 8. The method according to any one of claims 5 to 7, characterized in that a dry oxidation process after the process step followed. 9. The method according to any one of claims 1 to 8, characterized in that both the channel zone ( 22 ) and the source zone ( 23 ) are formed after implantation of the trench ( 6 ) by implantation, activation and / or diffusion. 10. The method according to any one of claims 1 to 9, characterized in that the channel zone ( 22 ) and / or the source zone ( 23 ) are formed after arranging the gate electrode ( 62 ). 11. The method according to any one of claims 1 to 10, characterized in that
after the trench ( 6 ) has been introduced, the trench ( 6 ) is almost completely filled with the material of the field electrode ( 63 ),
the first dielectric layer (321) by an etching step of not covered by the field electrode (63) portions of the trench wall as well as a formed by the field electrode (63) and the semiconductor substrate (7) intermediate space to a body height (72) of the trench (6 ) is removed, the body height ( 72 ) corresponding to a transition channel zone / drift zone ( 71 ) in the semiconductor substrate ( 7 ),
a second dielectric layer ( 322 ) is applied at least to the exposed trench wall and the field electrode ( 63 ) and
then the trench ( 6 ) is filled with the material of the gate electrode ( 62 ), whereby
the gate electrode ( 62 ) is pronounced at the level of the channel zone ( 22 ) next to sections of the field electrode ( 63 ). 12. The method according to any one of claims 1 to 10, characterized in that
lining the trench ( 6 ) in sections with a first dielectric layer ( 321 ) comprises the following steps: - Applying the first dielectric layer ( 321 ) at least in sections on the substrate surface ( 20 ) structured by the trenches ( 6 ), Applying a first auxiliary layer ( 46 ) to the first dielectric layer ( 321 ), the trench ( 6 ) being completely filled with the material of the first auxiliary layer ( 46 ), Removing sections of the first auxiliary layer ( 46 ), the trench ( 6 ) remaining filled up to body height ( 72 ) by remanent sections of the first auxiliary layer ( 46 ), - At least reducing a layer thickness d _{dS of} the first dielectric layer ( 321 ) in the sections and not covered by the remanent sections of the first auxiliary layer ( 46 ) - Removing the remanent sections of the first auxiliary layer ( 46 ). 13. The method according to any one of claims 1 to 10, characterized in that
after removal of sections of the first auxiliary layer ( 46 ) from the trench ( 6 ) in the trench ( 6 ) above the body height ( 72 ), a second, structured auxiliary layer ( 47 ) for contacting the gate and field electrodes ( 62 , 63 ) provided sections of the trench ( 6 ) and on adjoining areas of the substrate surface ( 20 ),
the first dielectric layer ( 321 ) is reduced or removed in its layer thickness in the portions neither covered by the remanent sections of the auxiliary layer ( 46 ) nor by the second auxiliary layer ( 47 ) and
then the remanent sections of the auxiliary layer ( 46 ) and the second auxiliary layer ( 47 ) are removed. 14. The method according to any one of claims 12 or 13, characterized in that after removal of the remanent portions of the first auxiliary layer ( 46 ), the trenches ( 6 ) are completely lined with the first dielectric layer ( 321 ), which in an upper, itself between the body height ( 72 ) and the substrate surface ( 20 ) extending region of the trench ( 6 ) has a layer thickness d _o and in a lower region of the trench ( 6 ) a layer thickness d _u , where d _u > d _o , and the introduction the field electrode ( 63 ) comprises the following steps: 1. conformal deposition of the material of the field electrode ( 63 ) in a layer thickness d _A for which the following applies: d _A > (d _T / 2 - d _u ) and d _A <(d _T / 2 - d _o ) (d _T = trench width ) and - Isotropic etching back of the material of the field electrode ( 63 ), the material being at least just completely removed from the upper region of the trench ( 6 ). 15. The method according to any one of claims 12 to 14, characterized in that the material of the first auxiliary layer ( 46 ) is a photoresist, which is subjected to a postbake process before the section-wise removal of the first dielectric layer ( 321 ). 16. The method according to any one of claims 12 to 15, characterized in that an adhesion promoter is applied before the application of the first auxiliary layer ( 46 ) and the adhesion promoter is removed before the field electrode ( 63 ) is introduced. 17. The method according to any one of claims 1 to 16, characterized in that
forming a gate dielectric layer ( 33 ) on portions of the trench wall
reducing the layer thickness d _{DS of} the first dielectric layer ( 321 ) to a layer thickness d _{GD of} the gate dielectric layer ( 33 ) in portions of the trench wall and neither covered by the first auxiliary layer ( 46 ) nor by the field electrode ( 63 )
the second dielectric layer ( 322 ) is arranged exclusively on the field electrode ( 63 ), wherein
the gate dielectric layer ( 33 ) is formed exclusively by portions of the first dielectric layer ( 321 ) which are reduced in layer thickness. 18. The method according to any one of claims 1 to 16, characterized in that
forming a gate dielectric layer ( 33 ) on portions of the trench wall
reducing the layer thickness d _{ds of} the first dielectric layer ( 321 ) to a reduced layer thickness in sections of the trench wall and neither covered by an auxiliary layer ( 46 , 47 ) nor by the field electrode ( 63 )
the second dielectric layer ( 322 ) is arranged on the field electrode ( 63 ) and at least in sections of the trench wall not covered by the field electrode ( 63 ), wherein
the gate dielectric ( 33 ) is formed by sections of a double layer consisting of the first and the second dielectric layer ( 321 , 322 ). 19. The method according to claim 18, characterized in that the first dielectric layer ( 321 ) is completely removed in sections of the trench wall covered by neither an auxiliary layer ( 46 , 47 ) nor by the field electrode ( 63 ) and the gate dielectric layer ( 33 ) only is formed by portions of the second dielectric layer ( 322 ). 20. The method according to any one of claims 1 to 19, characterized in that the first and / or the second dielectric layer ( 321 , 322 ) are each provided at least in sections as thermal oxide, deposited oxide, nitride, oxynitride or as a multilayer structure. 21. The method according to any one of claims 1 to 20, characterized in that after reducing the layer thickness d _dS or removing the first dielectric layer ( 321 ) in areas not covered by the field electrode ( 63 ) projecting areas of the field electrode ( 63 ), which protrude in the trench ( 6 ) beyond a collar formed by the first dielectric layer ( 321 ). 22. The method according to any one of claims 1 to 21, characterized in that the material of the field electrode ( 63 ) and / or the gate electrode ( 62 ) is provided at least in sections with a highly conductive component. 23. The method according to claim 22, characterized in that a silicide is provided as a highly conductive component. 24. Trench transistor cell in a semiconductor substrate, wherein
A drain zone ( 10 ), a drift zone ( 21 ), a channel zone ( 22 ) and a source zone ( 23 ) are formed in the semiconductor substrate ( 7 ) one after the other and essentially horizontally layered,
a trench ( 6 ) is provided in the semiconductor substrate ( 7 ),
the trench ( 6 ) to a body height ( 72 ), which is opposite a transition between drift zone and channel zone in the semiconductor substrate ( 7 ), with a first dielectric layer ( 32 ) and between the body height ( 72 ) and the substrate surface ( 20 ) is lined with a gate oxide ( 33 ) and
in the trench (6) has a substantially up to the top of the first dielectric layer (32) reaching from the grave bottom field electrode (63) is between about the body height (72) and the substrate surface (20) a gate electrode (63) and between the gate The electrode ( 62 ) and the field electrode ( 63 ) are arranged with a second oxide layer ( 322 ),
characterized in that
the second oxide layer ( 322 ) is at least as thick as the thinnest point of the gate oxide ( 33 ) at every point between the field electrode ( 63 ) and the gate electrode ( 62 ) 25. transistor arrangement, marked by at least one trench transistor cell according to claim 24.