DE102005041322B4 - Trench transistor structure with field electrode assembly and manufacturing method thereof - Google Patents

Abstract

Trench transistor structure with - in a semiconductor body (2) from a surface (3) and extending from each other by a Mesagebiet (5) spaced trenches (4) of a transistor array (1); - A formed in Mesagebiet (5) for receiving a reverse voltage drift zone (8) of a first conductivity type; A body region (6) formed above the drift zone (8) of a second conductivity type opposite to the first conductivity type with source regions (7) of the first conductivity type adjoining the trenches (4); - A formed below the drift zone (8) drain region (9) of the first conductivity type; - a gate electrode (10) formed in the trenches (4) and spaced from the mesa region (5) by a gate insulation structure (11) for controlling the conductivity of between the source regions (7) and the drift zone (8) and to the trenches (4) adjacent channel areas (12); - a field electrode arrangement (13) arranged in the trenches (4) with at least one electrically conductive field electrode (14a, 14b, 14c) spaced apart by an insulation structure (15) from the mesa region (5) and the gate electrode (10), - the field electrode arrangement ( 13) comprising a semiconductor zone arrangement (17) which is formed from at least one semiconductor zone (18a, 18b, 18c) of the second conductivity type reaching the surface (3) and outside of the transistor array (1) in a semiconductor region adjoining the drift zone (8) (16) of the first conductivity type, is electrically connected, and between a semiconductor zone (18a, 18b, 18c) of the semiconductor zone arrangement (17) and either one in the direction of the transistor array (1) adjacent semiconductor zone (18a, 18b, 18c) of the semiconductor zone arrangement (17) or the body region (6) of the transistor array (1) to the surface (3) of the semiconductor body (2) reaching auxiliary zone (19) from the second Leitf Ability type is formed; A dopant concentration of the auxiliary zone (19) is smaller compared to the dopant concentration of the semiconductor zones (18a, 18b, 18c).

Description

The invention relates to a trench transistor structure having the features of the preamble of claim 1 and to a method for the production thereof.

The development of trench transistors such as MOSFETs (metal oxide semiconductor field effect transistors) is driven by the minimization of the surface specific resistance R _on · A essential.

In a MOS trench transistor structure, trenches spaced by mesa regions define a cell array of trench transistors. In the trench transistors, a source region is usually embedded in a body region of the opposite conductivity type, wherein the body region is formed above a drain region and drift region of the trench transistor. For controlling the conductivity in a channel region adjoining the trench in the body region, a gate electrode which is insulated in relation to semiconductor regions in the trench serves.

Decisive for the dielectric strength of a trench transistor, d. H. the maximum voltage that can be applied between source and drain before the occurrence of voltage breakdown is, in particular, a dopant concentration and a vertical extent of the drift region. The drift region in such devices in the blocking state, d. H. the reverse-biased junction between the body and drift regions, the majority of the blocking voltage applied between source and drain. A lowering of the dopant concentration in the drift region on the one hand favors the dielectric strength, but on the other hand leads to an increase in the surface-specific on-resistance due to the resulting lower conductivity.

The provision of a field electrode which is insulated in the trench from the drift region and which is at a defined potential causes a compensation of charge carriers in the drift region. Because of this compensation effect, it is possible to increase the drift region of the trench transistor compared to trench transistors without such a field electrode with constant dielectric strength in its dopant concentration, which in turn leads to a reduction of the on-resistance.

Field plate trench transistor structures are known which superimpose a plurality of field plates one on top of the other in order to reduce the thickness of a blocking voltage-absorbing field oxide in the trench, which are held at different potentials.

Sun strikes DE 103 39 455 B3 a vertical semiconductor device having a field electrode having drift zone. The field electrode is connected to a floating p-region buried in silicon. When a blocking voltage is applied, the space charge zone propagates from the body region, and when the floating p region is reached, its potential and thus the potential of the field plate is frozen at the corresponding potential predetermined by the space charge zone. If further field plates are integrated into the depth of the body region, these are also frozen successively as the blocking voltage is increased to a corresponding potential. This structure brings the disadvantage of a very high production costs. For each of these p-regions, a plurality of individual processes is necessary, the realization of which is questionable in the current state of the art, since, for example, a crystal-defect-free epitaxial overgrowth of insulators or electrodes would be required for this purpose.

DE 103 39 488 B3 describes a lateral field plate transistor with multiple field plates whose potentials are determined by floating p-type regions.

It has also been proposed to tap the potentials of the field plates from a voltage divider, such as a Zener diode chain with a series resistance. However, such a concept has the disadvantage that when a reverse voltage is raised, a uniform voltage drop across the individual Zener diodes is caused. However, since the space charge zone propagates successively from the body region into the drift zone, it would be desirable to place the field plates in succession at a corresponding potential.

DE 100 14 660 C2 describes a semiconductor device having a trench electrode separated by a cavity from a drift path. In this case, the semiconductor device has at least two rigid electrodes, which are electrically separated from each other by an insulating device of at least one insulating or holding layer and / or a pn junction, wherein the insulating device additionally contains at least one cavity, characterized in that at least one of Electrodes is a trench electrode introduced to reduce the on resistance of the semiconductor device between body regions, which is electrically connected to an active region of the semiconductor device and separated from a drift path of the semiconductor device through the cavity.

JP 2003 243 655 A describes an IGBT and a method for its production. Here, a substrate having an n ⁺ -type drain region, an n-type drift region and a number of body regions and source regions are provided for forming a number of FET cells. Trenches are provided in the substrate for separating the FET cells. In each trench are introduced conductive layers which are separated from each other by an insulating layer.

EP 1 170 803 A2 describes a trench gate MOSFET and a method for its production. In a trench MOSFET, a conductive shield gate is formed near the trench bottom. The shield gate is isolated from the overlying gate and connected to a constant voltage such as ground, depending on the use of the MOSFET. The shield gate reduces the capacitance between the active gate and the drain, thereby improving the capability of the MOSFET in high frequency operation, be it in its linear region or as a switching device.

The invention has for its object to provide a trench transistor structure with field plate arrangement, which provides potentials for the field plates available and can be produced in a simple and cost-effective manner.

The object is achieved by a trench transistor structure having the features of independent claim 1. A process for their preparation is defined in claim 12. Preferred developments of the invention can be taken from the dependent claims and will be explained in the further description.

According to the invention, a trench transistor structure is provided with trenches of a transistor field reaching into a semiconductor body from a surface and spaced from each other by a mesa region, a drift zone of a first conductivity type formed in the mesa region for receiving a reverse voltage, a body region formed above the drift zone of a first conductivity type second conductivity type having first conductivity type source regions adjacent the trenches, a first conductivity type drain region formed below the drift region, a gate electrode formed in the trenches and spaced from the mesa region by a gate isolation structure to control conductivity of the source regions and the drift region Trenches adjacent channel areas and arranged in the trenches field electrode arrangement with at least one by an Isolatio The field electrode arrangement is formed with a semiconductor zone arrangement which is formed from at least one second conductivity type semiconductor zone reaching the surface and outside the transistor field in a first conductivity type semiconductor region adjoining the drift zone. electrically connected.

The transistor field defined above is not assigned an edge termination of the trench transistor structure. The semiconductor body may, for example, consist of a semiconductor wafer, in particular a silicon wafer, and may have an applied epitaxial layer, for example. In the case of a silicon wafer with applied epitaxial layer, the trenches protrude from the surface into the epitaxial layer. The arrangement of trenches and Mesagebieten may for example be strip-shaped, so that the transistor array is constructed of stripes. Alternatively, however, further geometries of the arrangement of trenches and Mesagebieten are possible. An electrical connection between the semiconductor zone arrangement, i. H. the at least one semiconductor zone reaching the surface, with which at least one field electrode of the field electrode arrangement can be effected, for example, via a metallization plane, wherein the at least one field electrode can be contacted via the surface in a region adjacent to the semiconductor zone arrangement and thus conductively connected to the metallization plane. The semiconductor region adjacent to the drift region outside the transistor field is of the same conductivity type as the drift zone; in particular, these regions can be formed by the same semiconductor layer. Thus, the potential in the adjacent semiconductor region couples to a voltage applied between the source regions and the drain region.

The first conductivity type may be n-type and the second conductivity type may be p-type. It is also conceivable to form the first conductivity type as p-type and the second conductivity type as n-type.

In an advantageous embodiment, the field electrode arrangement has a plurality of vertically arranged below each other and spaced apart by the insulation structure field electrodes, the semiconductor zone array has a plurality of the plurality of field electrodes corresponding plurality of adjacent to each other and the transistor array differently spaced semiconductor zones of the second conductivity type, wherein the semiconductor zones with increasing lateral distance from the transistor field are each connected to an increasingly deeper arranged in the semiconductor body field electrode.

Since the semiconductor regions of the second conductivity type in the adjacent semiconductor region of lie first conductivity type and are not connected to any external potential, they are designed floating. A freezing of the potential of a semiconductor zone is achieved in that when increasing a blocking voltage between the drain and source in the transistor field of the adjacent semiconductor region is laterally cleared from the drift region of freely movable charge carriers such as electrons and holes and the resulting space charge zone when hitting the semiconductor zone Potential and thus the potential of the connected to the semiconductor zone field electrode fixed. Since a lower-lying field electrode is conductively connected to a respective semiconductor zone further apart from the transistor array, a successive increase of a blocking voltage between drain and source initially fixes the potential of an uppermost field electrode as soon as the space charge zone reaches the next adjacent semiconductor zone to the transistor array. If the space charge zone expands further by further increasing the blocking voltage and if it reaches the semiconductor zone next to the semiconductor zone closest to the outside, the field electrode located below the uppermost field electrode is fixed in its potential. Thus, the potential of the uppermost field electrode is closest to the potential of the source regions of the trench transistor, and the potential of the lowermost field electrode is closest to the potential of the drain of the transistor array. As this reduces a voltage drop between the field electrodes and the laterally adjacent region of the drift zone, this allows a reduction in the thickness of the isolation structure, for example a field oxide of appropriate thickness.

In an advantageous embodiment, an auxiliary zone of the second conductivity type extending to the surface of the semiconductor body is formed between a semiconductor zone and either a semiconductor zone adjacent to the transistor array or the body region of the transistor array and a dopant concentration of the auxiliary zone is smaller compared to the dopant concentration of the semiconductor zones. When a blocking voltage between drain and source is applied, these auxiliary zones are successively cleared outward from the transistor field, ie. H. depleted at freely movable charge carriers, so that they provide in the blocking mode no conductive connection between the semiconductor zones or between the transistor field next adjacent semiconductor zone and the body region. In contrast, when the trench transistor structure is switched on again, these auxiliary zones lead to the field plates being discharged since, in this operating state of the trench transistor structure, they are not depleted on freely movable charge carriers and thus conductively connect the floating semiconductor zones to the source regions.

According to the invention, a semiconductor zone arranged closer to the transistor field forms a drain of two adjacent semiconductor zones and the other of the two adjacent semiconductor zones a source of an auxiliary transistor having a second conductivity type channel conductivity, wherein a gate electrode of the auxiliary transistor is connected to the drain and a semiconductor zone next to the transistor field is a source of an additional auxiliary transistor whose drain is formed in the transistor array and whose drain potential is determined by the potential of the body region in the transistor array. Thus, the transistor zone next adjacent semiconductor zone on the one hand, the source of an auxiliary transistor whose drain forms the body region in the transistor field, on the other hand, this semiconductor zone also represents the drain of a transistor, the source of which is by the transistor field from outwardly nearest adjacent semiconductor zone. In the same way, this semiconductor zone, which is nearest to the outside, represents the drain of an additional auxiliary transistor in the presence of further outward semiconductor zones. Thus, it is a series connection of auxiliary transistors, wherein the semiconductor zones both as a source of a further inwardly formed auxiliary transistor and as a drain a further outwardly formed auxiliary transistor act. If a blocking voltage is applied to the trench transistor, a space charge zone in the adjacent semiconductor region arises in the region of the auxiliary transistors. Such a space charge zone leads to a substrate control effect and thus to a substantial increase in the threshold voltage of the auxiliary transistors. Once the potential difference between the drain and source of one of these auxiliary transistors, i. H. between adjacent semiconductor zones, reaches the threshold voltage of the auxiliary transistor, a recharging current flows to the field electrode connected to the source of the corresponding auxiliary transistor. Thus, the semiconductor zones arranged one behind the other from the transistor array are retained on their own from the successive accumulation of the threshold voltages. The potential of the transistor zone next adjacent semiconductor zone in blocking mode is thus removed by a threshold voltage from the source potential in the cell array. An adjacent to the transistor field adjacent semiconductor zone is thus in the blocking mode by two threshold voltages away from the source potential in the transistor field.

The auxiliary transistors are preferably designed as planar transistors or as trench transistors. In the formation of the auxiliary transistors as trench transistors, the channel region is formed, for example, in the adjacent semiconductor region in the region of the side walls of the trenches.

In an advantageous embodiment, a channel region of the first conductivity type lying between the source and the drain of the auxiliary transistor has a higher dopant concentration than the semiconductor region adjoining the drift zone. In this case, the dopant concentration in the channel region is increased, for example, by ion implantation to increase the threshold voltage.

In a further advantageous embodiment, the field electrode arrangement is conductively connected to a further semiconductor zone arrangement having at least one further semiconductor zone of the second conductivity type formed in the semiconductor region adjacent to the drift zone. In this case, it is possible for the semiconductor zone arrangement as well as the further semiconductor zone arrangement to be formed together and to merge into one another in the semiconductor region adjoining the drift zone.

In an advantageous manner, the further semiconductor zone arrangement has a plurality of further semiconductor zones which are adjacent to each other and are differently spaced from the transistor array, the further semiconductor zones being conductively connected to an increasingly lower field electrode with increasing lateral distance from the transistor field. Thus, a field electrode is connected to both an auxiliary transistor forming semiconductor zone and to another semiconductor zone. The further semiconductor zone arrangement serves, in particular, for discharging the field plates when the trench transistor structure is switched on again. The semiconductor zone and further semiconductor zone connected in each case to a same field electrode may overlap one another such that the corresponding semiconductor zone and the further semiconductor zone form a common semiconductor zone, ie. H. these may be formed, for example, immediately adjacent to each other.

In a further advantageous embodiment, a further auxiliary zone of the second conductivity type extending to the surface of the semiconductor body is formed between one of the further semiconductor zones and either another semiconductor zone adjacent to the transistor array or the body region of the transistor array, and a dopant concentration of the second auxiliary zone is smaller compared to FIG Dopant concentration of the other semiconductor zone. When a blocking voltage is applied between drain and source, these further auxiliary zones are successively cleared outwards from the transistor field, ie. H. depleted at freely movable charge carriers, so that they provide in blocking operation no conductive connection between the other semiconductor zones or between the transistor field next adjacent further semiconductor zone and the body region. In contrast, when the trench transistor structure is switched on again, these auxiliary zones lead to the field plates being discharged since, in this operating state of the trench transistor structure, they are not depleted on freely movable charge carriers and thus conductively connect the floating semiconductor zones to the source regions.

Advantageously, a further semiconductor zone arranged closer to the transistor array is a source of two adjacent further semiconductor zones, and the other of the two further semiconductor zones is a drain of a further auxiliary transistor having a second conductivity type channel conductivity, wherein a gate electrode of the further auxiliary transistor is connected to the drain and one the transistor field next adjacent further semiconductor zone forms the drain of an additional additional auxiliary transistor whose source is formed in the transistor field and whose source potential is determined by the potential of the body region in the transistor field. These additional auxiliary transistors show a lower threshold voltage when the trench transistor is switched on than the auxiliary transistors defined by the semiconductor zones due to the attributable substrate control effect. Thus, the further auxiliary transistors are suitable for discharging the field electrodes when the trench transistor structure is switched on again and prevent the field electrodes from being led to negative potential when the trench transistor structure is switched on again.

In an advantageous embodiment, the semiconductor region adjoining the drift zone forms an edge termination of the transistor field. Thus, upon application of a reverse voltage between the drain region and the source regions, the space charge zone expands into the edge termination.

In an advantageous embodiment, the semiconductor zones and / or the further semiconductor zones are arranged in further mesa regions, wherein the width of the further mesa regions essentially corresponds to the width of the mesa regions in the transistor field. This embodiment is particularly advantageous if a dopant concentration in the drift zone is equal to or less than the dopant concentration in the adjacent semiconductor region.

A method according to the invention for producing a field electrode arrangement of a trench transistor structure comprises the steps of providing the semiconductor substrate with the trenches formed therein and an insulation structure adjoining the trenches and the further steps filling the trenches with a conductive material, applying an etching mask which extends from the transistor array into adjacent to the drift zone Covering semiconductor region reaching portions of the trenches and exposing lying in the transistor field portions of the trenches, forming a field electrode by back etching a portion of the conductive material in the transistor field formed in the parts of the trenches and forming an insulating structure on the field electrode. Subsequent to these further steps, an optional formation of one or more further field plates can be carried out by successively repeating the further steps, after which a completion of the transistor field including formation of the semiconductor zone arrangement in the adjacent semiconductor region as well as connection of the semiconductor zones takes place respectively with a field electrode. Thus, the field electrodes are each guided to the surface of the semiconductor body in the adjacent semiconductor region, from where they can be connected for example via contact holes with a metallization and from here to the semiconductor zones and the other semiconductor zones. It is likewise possible, for example, for the top field electrode, ie the field electrode next to the gate electrode, to be set to source potential. The termination of the transistor array may include, but is not limited to, forming the gate electrode, doped regions such as the source regions or the body region, optional channel implantations for adjusting the threshold voltage, intermediate oxides, as well as metallization levels.

It is advantageous to form the insulation structure as a thermal oxide.

In a preferred embodiment, polysilicon is used as the conductive material. The conductivity of the polysilicon can be adjusted in a simple manner, for example, by adding dopants of the p or n conductivity type, for example boron or phosphorus. It should be noted, however, that in addition to polysilicon, a large number of other conductive materials, such as doped semiconductor layers or even metallic layers may be suitable. The selection of a suitable conductive material is essentially determined by the process integration.

Advantageously, the etching mask is formed as a structured photoresist. For this purpose, for example, first photoresist is applied over the entire surface and then lithographically structured, so that the photoresist in the transistor field is removed and the field electrode in the adjacent to the drift region semiconductor region despite etching back in the transistor field continues to reach the surface.

The invention will be explained in more detail in exemplary embodiments with reference to figures.

1 shows in part a) a schematic cross-sectional view of a section of a transistor cell array with field electrode arrangement and in part figure b) is a schematic cross-sectional view of a first embodiment of a semiconductor zone arrangement in a adjacent to a drift zone semiconductor region,

2 shows a schematic plan view of an embodiment of in 1a represented transistor field and the in 1b illustrated semiconductor zone arrangement,

3 shows a schematic cross-sectional view through a part of a trench in the adjacent semiconductor region with a guided to a surface of a semiconductor body field electrode assembly according to an embodiment,

4 shows in the sub-figures a) and b) views successive process stages during the formation of the field electrode assembly according to an embodiment,

5 shows an embodiment of a semiconductor zone arrangement with planar transistors in the adjacent semiconductor region,

6 shows a further embodiment of a further semiconductor zone arrangement in the adjacent semiconductor region for discharging the field plates when the trench transistor structure is switched on again in the transistor field,

7 shows a schematic cross-sectional view of another embodiment of the other semiconductor zone arrangement in the adjacent semiconductor region for discharging the field plates when the trench transistor structure in the transistor field.

In 1a is a schematic cross-sectional view of a section of a transistor array 1 shown. In a semiconductor body 2 , preferably of silicon, extend from a surface 3 from trenches 4 into it. The trenches 4 are through a mesa area 5 spaced apart. In the Mesagebiet 5 is a body area 6 formed, which to the surface 3 of the semiconductor body 2 enough. In the body area 6 embedded and also to the surface 3 trained as well as the trenches 4 adjacent are source areas 7 of the n ⁺ conductivity type.

In order to indicate a gradation in conductivity of various semiconductor regions in the figures, n ^{+ is used} to designate a n-type semiconductor region of high conductivity, n denotes a n-type semiconductor region of moderate conductivity, and n ^- denotes a semiconductor region used of the n-conductivity type with low conductivity. The attributes large, moderate and low conductivity are to be interpreted relative to each other.

Below the body area 6 is a drift zone 8th formed of n ^- conductivity type. The drift zone 8th is used in particular for receiving voltage when applying a blocking voltage to the trench transistor structure. Below the drift zone 8th is a drainage area 9 which is, for example, a n ⁺ -type metal-bonded semiconductor region. The drainage area 9 For example, it may have a silicon wafer with n ⁺ conductivity.

Inside the trenches 4 is in each case essentially at the level of the body area 6 a gate electrode 10 formed, which has a gate insulation structure 11 from the body area 6 spaced and electrically isolated. Thus, over a potential of the gate electrode 10 a conductivity in a channel area 12 between the source areas 7 and the drift zone 8th to be controlled. Below the gate electrode 10 is a field electrode arrangement 13 educated. The field electrode arrangement 13 has three electrically conductive field electrodes positioned one below the other 14a . 14b and 14c on which from each other and from the gate electrode 10 spaced apart by an insulating structure and electrically insulated. The field electrodes 14a . 14b and 14c as well as the gate electrode 10 are preferably formed of doped, ie conductive, polysilicon.

In 1b is a schematic cross-sectional view of one of the drift zone 8th adjacent semiconductor region 16 shown. In the adjacent semiconductor region acting as edge termination 16 The n ^- type conductivity type is a semiconductor zone device consisting of a first semiconductor region 18a , a second semiconductor zone 18b and a third semiconductor zone 18c formed of the p-type conductivity. The semiconductor zones 18a . 18b and 18c reach to the surface 3 of the semiconductor body 2 and are each with one of the field electrodes 14a . 14b and 14c in the transistor field 1 conductively connected. Here is the transistor field 1 next adjacent first semiconductor zone 18a with one immediately below the gate electrode 10 arranged first field electrode 14a conductively connected. Likewise, one below the first field electrode 14a positioned second field electrode 14b with the first semiconductor zone 18a outwards, ie from the transistor field 1 further away, positioned second semiconductor zone 18b conductively connected. A corresponding conductive connection also lies between a third field electrode 14c and the third semiconductor zone 18c in front.

Between the adjacent semiconductor zones as well as between the first semiconductor zone 18a and the body area 6 In each case, an auxiliary zone of the p ^- conductivity type is formed. When applying a blocking voltage between the source regions 7 and the drain 9 becomes the adjacent semiconductor region 16 laterally by forming one in the form of equipotential lines 20a . 20b and 20c marked space charge zone cleared of freely movable charge carriers. Here are also the auxiliary zones 19 cleared out and impoverished on freely movable charge carriers. The space charge zone initially spreads from the transistor field 1 to the first semiconductor zone 18a out. When they reach their potential and thus the potential on the first field electrode 14a fixed. As the blocking voltage is further increased, the second and the third field electrodes are successively fixed to correspondingly higher potentials.

If the trench transistor structure is switched on again from the blocking operation, the auxiliary zones set 19 a conductive connection between the semiconductor zones 18a . 18b . 18c as well as the body area 6 ready, causing the field plates 14a . 14b . 14c can discharge. This is due to the fact that the auxiliary zones 19 when the trench transistor structure is switched on again, the semiconductor zones 18a . 18b and 18c conducting with the body area 6 connect.

2 shows a schematic plan view of the transistor array 1 with adjacent semiconductor region 16 , In the extension of the Mesagebiets 5 in the adjacent semiconductor area 16 are the semiconductor zones 18a . 18b . 18c represented as well as the intermediate auxiliary zones 19 , In the 1a) schematically illustrated cross-sectional view in the transistor field 1 is taken from a line marked AA '. In the 1b illustrated schematic cross-sectional view of the adjacent semiconductor region 16 is in 2 indicated as section line BB '.

In 3 is a schematic cross-sectional view in the adjacent semiconductor region 16 in the trench 4 shown. The cross-sectional view is in 2 characterized by a section line CC '. The upper part of 3 shows in perspective the supervision of the Mesagebiet 5 , The first field electrode 14a is here in the area of the first semiconductor zone 18a to the surface 3 of the semiconductor body. An electrically conductive connection between the first field electrode 14a and the first semiconductor zone 18a is schematically indicated by a line-shaped connection. The second field electrode 14b is in the range of the second semiconductor zone 18b led to the surface and connected with this also electrically conductive. The same applies to the third field electrode 14c and the third semiconductor zone 18c , The field electrodes 14a . 14b . 14c are among each other and to the gate electrode 10 through the insulation structure 15 isolated. Likewise, the isolation structure isolates 15 the electrodes within the trench 4 to the neighboring mesa area 5 by which a section line BB ' is placed in the 2 illustrated section line BB 'corresponds. The simplified line illustrated electrically conductive connection between, for example, the first field electrode 14a and the first semiconductor zone 18a can be realized for example via contact openings and metallization levels.

In 4 In the partial illustrations a) and b) schematic cross-sectional views along the section lines AA '(left partial image) and CC' (right partial image) during successive process stages in the production of the field electrode arrangement are shown schematically. 4a shows a schematic cross-sectional view in the transistor field after filling the trenches 4 with a conductive material 21 for the lowest field electrode. The conductive material 21 the lowest field electrode is from the mesa area 5 through the insulation structure 15 spaced. In the right part of the figure is a schematic cross-sectional view along the section line CC 'from 2 shown. The conductive material 21 for the lowest field electrode is within the trenches 4 and trained beyond. An etching mask 22 covers an edge region of the adjacent semiconductor region and serves as an etch stop for the subsequent etching of the conductive material to form the lowermost field electrode. This etching mask makes it possible to bring the lowermost field electrode to the surface in the edge region of the adjacent semiconductor region 3 respectively.

In 4b is the schematic cross-sectional view in the transistor field along the section line AA 'in the left partial image 2 after re-etching of the conductive material 21 the lowest field electrode 21 ' shown. This etch back leaves the bottom field electrode 21 ' deep in the trench 4 back. Above the lowest field electrode 21 ' is the isolation structure 15 re-educated. In the right part of the figure is a schematic cross-sectional view along the section line CC 'from 2 shown. The etching back of the conductive material 21 the lowest field electrode 21 ' is only lateral to the previously formed etch stop layer 22 performed, which is why the bottom field electrode 21 ' in this area to the surface 3 enough. Thus, the lowest field electrode 21 ' be electrically connected via the surface with a semiconductor zone arrangement. A successive repetition of the in the 4a and 4b shown method steps allows stacking a plurality of field electrodes.

In 5 is a schematic cross-sectional view of another embodiment of a semiconductor zone arrangement in the adjacent semiconductor region 16 shown. Next to the body area 6 in the transistor field 1 lies the first semiconductor zone 18a the semiconductor zone arrangement in the adjacent semiconductor region 16 , Outward, ie further from the transistor field 1 removed, lies the second semiconductor zone 18b followed by the third semiconductor zone 18c , The first semiconductor zone 18a serves in this embodiment, on the one hand as a source of an auxiliary transistor 23 whose drain is the body area 6 in the transistor field 1 in blocking operation of the transistor structure represents. At the same time serves the first semiconductor zone 18a as a drain of an additional auxiliary transistor 23 whose source is the second semiconductor zone 18b is. A gate electrode of the auxiliary transistor 24 is connected to the drain. Likewise, the second semiconductor zone serves as a drain of an auxiliary transistor 23 whose source is the third semiconductor zone 18c is. The gate electrode 24 also this auxiliary transistor 23 is connected to its drain. In this way, depending on the number of field electrodes or semiconductor zones now auxiliary transistors can be successively switched one behind the other. It should be noted at this point again that the first semiconductor zone 18a in particular with the example in 1a shown first field electrode 14a is electrically connected. Accordingly, the second semiconductor zone 18b with the second field electrode 14b and the third semiconductor zone 18c with the third field electrode 14c (please refer 1a ) connected conductively. The gate electrode 24 of the auxiliary transistor 23 that one through the body area 6 has trained drain, is at source potential.

When a blocking voltage is applied between the source regions and the drain region in the transistor field, the space charge zone expands laterally from the transistor field 1 in the adjacent semiconductor area 16 into it. In this case, the adjacent semiconductor region 16 , which has an n ^- -type conductivity, depleted of free charge carriers. Likewise, between the source and the drain of each auxiliary transistor 23 lying channel areas 25 having additionally introduced n-type dopants therein for adjusting the threshold voltage, initially depleted of floating charge carriers. Such a carrier depletion by forming the space charge region acts as a substrate control effect on the auxiliary transistors 23 , This leads to a further increase in their threshold voltage. Reaches between source and drain via an auxiliary transistor 23 decreasing voltage whose threshold voltage, so is the channel region 25 conductive and the source of the auxiliary transistor 23 fixed to a threshold voltage of the auxiliary transistor above the potential of its drain. Thus, the field electrode connected to the source is also at this potential. By further increasing the blocking voltage in the transistor field, the mutually adjacent semiconductor zones are each a threshold voltage of the intermediate auxiliary transistor 23 kept apart. Thus, the field electrodes arranged below one another in the trench are also each at their potential around a threshold voltage of the auxiliary transistor 23 away from each other in potential.

In 6 is a schematic cross-sectional view of another semiconductor zone arrangement in the adjacent semiconductor region 16 shown. The further semiconductor zone arrangement has a first further semiconductor zone 26a , a second further semiconductor zone 26b and a third further semiconductor zone 26c on. These further semiconductor zones can, for example, the same distances to the body area 6 like the first semiconductor zone 18a , second semiconductor zone 18b and third semiconductor zone 18c (see. 5 ) and can be connected to these accordingly conductive. It is equally conceivable that the semiconductor zones 18a . 18b and 18c in the further semiconductor zone 26a . 26b and 26c to go over, ie they are immediately adjacent to each other. The other semiconductor zones 26a . 26b . 26c form like the semiconductor zones 18a . 18b . 18c further auxiliary transistors 27 which, however, differ from the auxiliary transistors 23 in 5 differ in that their gate electrodes 28 are connected in reverse. The first further semiconductor zone 26a When the trench transistor structure is switched on again, it forms a drain of a further auxiliary transistor 27 whose source is the body area 6 in the transistor field 1 given is. The gate electrode 28 this further auxiliary transistor 27 is thus connected to drain, but the source and the drain are compared to the arrangement of the auxiliary transistors in 5 reversed. This is because the trench transistor structure in one case (see 5 ) in the blocking mode and in the other case (see 6 ) are operated in the switched-on state. The other auxiliary transistors 27 serve in particular for discharging the field electrodes 14a . 14b and 14c when the trench transistor structure is switched on again. These further auxiliary transistors 27 When the trench transistors in the transistor array are turned on, they have a low threshold voltage since the substrate control effect is eliminated. This can prevent the field electrodes 14a . 14b and 14c when turning on the trench transistor structure to negative potential. The semiconductor zone arrangement 17 as well as the further semiconductor zone arrangement can lie laterally adjacent to one another, for example, in the region of the edge termination. Thus, the semiconductor zone arrangement serves in particular for defining the potentials of the field electrodes in the case of blocking operation of the trench transistor, and the further semiconductor zone arrangement is used in particular for discharging the field electrode arrangement when the trench transistor structure is switched on again.

7 shows a schematic cross-sectional view of a compared to 6 alternative or supplementary embodiment of a further semiconductor zone arrangement for discharging the field electrodes 14a . 14b and 14c , As in 6 are also in the in 7 the embodiment shown, the first further semiconductor zone 26a , the second further semiconductor zone 26b and the third further semiconductor zone 26c corresponding to the first field electrode 14a , the second field electrode 14b and the third field electrode 14c electrically connected. However, the in. Serve 7 shown further semiconductor zones not as a source or drain of other auxiliary transistors, but a discharge of the field electrodes 14a . 14b and 14c When the trench transistor structure is switched on again, it is activated by means of further auxiliary zones 29 , which between the other semiconductor zones 26a . 26b and 26c as well as between the first further semiconductor zone 26a and the body area 6 lie, reached. When the trench transistor structure is switched on again, the further auxiliary zones which have been depleted in the blocking mode on free charge carriers become 29 again conductive and thus provide a conductive connection between the other semiconductor zones 26a . 26b and 26c and the body area 6 ago, so that the field electrodes 14a . 14b and 14c can discharge.

Claims (15)

Trench transistor structure with - in a semiconductor body ( 2 ) from a surface ( 3 ) from reaching and from each other through a Mesagebiet ( 5 ) spaced trenches ( 4 ) of a transistor field ( 1 ); - one in the mesa area ( 5 ) formed for receiving a reverse voltage drift zone ( 8th ) of a first conductivity type; One above the drift zone ( 8th ) trained body area ( 6 ) of a second conductivity type opposite to the first conductivity type, to the trenches ( 4 ) adjacent source regions ( 7 ) of the first conductivity type; One below the drift zone ( 8th ) trained drainage area ( 9 ) of the first conductivity type; - one in the trenches ( 4 ) trained and from the Mesagebiet ( 5 ) by a gate insulation structure ( 11 ) spaced gate electrode ( 10 ) for controlling the conductivity of between the source regions ( 7 ) and the drift zone ( 8th ) and the trenches ( 4 ) adjacent canal areas ( 12 ); - one in the trenches ( 4 ) arranged field electrode arrangement ( 13 ) with at least one by an isolation structure ( 15 ) of the mesa area ( 5 ) and the gate electrode ( 10 ) spaced and electrically conductive field electrode ( 14a . 14b . 14c ), - the field electrode arrangement ( 13 ) with a semiconductor zone arrangement ( 17 ), which consists of at least one surface ( 3 ) semiconductor zone ( 18a . 18b . 18c ) is formed by the second conductivity type and outside the transistor field ( 1 ) in one to the drift zone ( 8th ) adjacent semiconductor region ( 16 ) is formed of the first conductivity type, is electrically connected, and between a semiconductor zone ( 18a . 18b . 18c ) of the Semiconductor zone arrangement ( 17 ) and either one towards the transistor field ( 1 ) adjacent semiconductor zone ( 18a . 18b . 18c ) of the semiconductor zone arrangement ( 17 ) or the body area ( 6 ) of the transistor field ( 1 ) one to the surface ( 3 ) of the semiconductor body ( 2 ) reaching auxiliary zone ( 19 ) of the second conductivity type is formed; A dopant concentration of the auxiliary zone ( 19 ) is smaller compared to the dopant concentration of the semiconductor zones ( 18a . 18b . 18c ). Trench transistor structure with - in a semiconductor body ( 2 ) from a surface ( 3 ) from reaching and from each other through a Mesagebiet ( 5 ) spaced trenches ( 4 ) of a transistor field ( 1 ); - one in the mesa area ( 5 ) formed for receiving a reverse voltage drift zone ( 8th ) of a first conductivity type; One above the drift zone ( 8th ) trained body area ( 6 ) of a second conductivity type opposite to the first conductivity type, to the trenches ( 4 ) adjacent source regions ( 7 ) of the first conductivity type; One below the drift zone ( 8th ) trained drainage area ( 9 ) of the first conductivity type; - one in the trenches ( 4 ) trained and from the Mesagebiet ( 5 ) by a gate insulation structure ( 11 ) spaced gate electrode ( 10 ) for controlling the conductivity of between the source regions ( 7 ) and the drift zone ( 8th ) and the trenches ( 4 ) adjacent canal areas ( 12 ); - one in the trenches ( 4 ) arranged field electrode arrangement ( 13 ) with at least one by an isolation structure ( 15 ) of the mesa area ( 5 ) and the gate electrode ( 10 ) spaced and electrically conductive field electrode ( 14a . 14b . 14c ), - the field electrode arrangement ( 13 ) with a semiconductor zone arrangement ( 17 ), which consists of at least one surface ( 3 ) semiconductor zone ( 18a . 18b . 18c ) is formed by the second conductivity type and outside the transistor field ( 1 ) in one to the drift zone ( 8th ) adjacent semiconductor region ( 16 ) of the first conductivity type is electrically connected; - of two adjacent semiconductor zones ( 18a . 18b ) those closer to the transistor field ( 1 ), one drain and the other of the two adjacent semiconductor regions ( 18b ) a source of an auxiliary transistor ( 23 ) with a channel conductivity of the second conductivity type; A gate electrode isolated from the source and channel and from the source to the drain ( 24 ) of the auxiliary transistor is connected to the drain of the auxiliary transistor; wherein - a transistor zone next adjacent semiconductor zone ( 18a ) a source of an additional auxiliary transistor ( 23 ) whose drain is in the transistor field ( 1 ) and its drain potential is determined by the potential of the body region ( 6 ) in the transistor field ( 1 ). Trench transistor structure according to claim 1 or 2, characterized in that - the field electrode arrangement ( 13 ) a plurality of vertically arranged one below the other and through the isolation structure ( 15 ) spaced apart field electrodes ( 14a . 14b . 14c ) having; The semiconductor zone arrangement ( 17 ) one of the plurality of field electrodes ( 14a . 14b . 14c ) corresponding plurality of mutually adjacent and of the transistor field ( 1 ) differently spaced semiconductor zones ( 18a . 18b . 18c ) of the second conductivity type; wherein - the semiconductor zones ( 18a . 18b . 18c ) with increasing lateral distance from the transistor field ( 1 ) each with an increasingly deeper in the semiconductor body ( 2 ) arranged field electrode ( 14a . 14b . 14c ) are electrically connected. Trench transistor structure according to claim 2, characterized in that - the auxiliary transistors ( 23 ) are designed as planar transistors or as trench transistors. Trench transistor structure according to claim 2 or 4, characterized in that a between the source and the drain of the auxiliary transistor ( 23 ) channel region ( 25 ) of the second conductivity type has a higher dopant concentration than that of the drift zone ( 8th ) adjacent semiconductor region ( 16 ). Trench transistor structure according to one of the preceding claims, characterized in that the field electrode arrangement ( 13 ) with a further semiconductor zone arrangement with at least one im to the drift zone ( 8th ) adjacent semiconductor region ( 16 ) formed further semiconductor zone ( 26a . 26b . 26c ) of the second conductivity type is conductively connected. Trench transistor structure according to claim 6, characterized in that - the further semiconductor zone arrangement has a plurality of the plurality of field electrodes corresponding plurality of mutually adjacent and of the transistor array ( 1 ) differently spaced further semiconductor zones ( 26a . 26b . 26c ) having; wherein - the other semiconductor zones ( 26a . 26b . 26c ) with increasing lateral distance from the transistor field ( 1 ) each with an increasingly lower field electrode ( 14a . 14b . 14c ) are electrically connected. Trench transistor structure according to claim 7, characterized in that Between one of the further semiconductor zones ( 26a . 26b . 26c ) and either one towards the transistor field ( 1 ) adjacent further semiconductor zone ( 26a . 26b ) or the body area ( 6 ) one to the surface ( 3 ) of the semiconductor body ( 2 ) reaching additional auxiliary zone ( 29 ) of the second conductivity type is formed; and - a dopant concentration of the further auxiliary zone ( 29 ) is smaller compared to the dopant concentration of the other semiconductor zones ( 26a . 26b . 26c ). Trench transistor structure according to claim 8, characterized in that - of two adjacent further semiconductor zones ( 26a . 26b ) those closer to the transistor field ( 1 ), one source and the other of the two further semiconductor zones ( 26b ), a drain of another auxiliary transistor ( 27 ) is formed with a channel conductivity of the second conductivity type; A gate electrode ( 28 ) of the further auxiliary transistor ( 27 ) is connected to the drain; wherein - a transistor field ( 1 ) next adjacent further semiconductor zone ( 26a ) the drain of an additional additional auxiliary transistor ( 27 ) whose source is in the transistor field ( 1 ) and its source potential by the potential of the body region ( 6 ) in the transistor field ( 1 ). Trench transistor structure according to one of Claims 1 to 9, characterized in that the voltage applied to the drift zone ( 8th ) adjacent semiconductor region ( 16 ) an edge termination of the transistor field ( 1 ). Trench transistor structure according to one of the preceding claims, characterized in that the semiconductor zones ( 18a . 18b . 18 ) and / or the further semiconductor zones ( 26a . 26b . 26c ) are arranged in further Mesagebieten, wherein the width of the further Mesagebiete substantially the width of Mesagebiete ( 5 ) in the transistor field ( 1 ) corresponds. Method for producing a field electrode arrangement of a trench transistor structure according to one of Claims 1 to 11, characterized by the steps: - provision of the semiconductor body ( 2 ) with the trenches formed therein ( 4 ) and one to the trenches ( 4 ) adjacent isolation structure ( 15 ); and the further steps: - filling the trenches ( 4 ) with a conductive material ( 21 ); - Applying an etching mask ( 22 ) from the transistor field ( 1 ) from those parts of the trenches ( 4 covered in the drift zone ( 8th ) adjacent semiconductor region ( 16 ) and in the transistor field ( 1 ) lying parts of the trenches ( 4 ) uncovered; - Forming a field electrode ( 21 ' ) by re-etching a portion of the conductive material ( 21 ) in the in the transistor field ( 1 ) formed parts of the trenches ( 4 ); - forming an insulation structure ( 15 ) on the field electrode ( 21 ' ); and optionally forming one or more further field electrodes by successively repeating the further steps; and - forming the semiconductor zone arrangement ( 17 ) and connecting the semiconductor zones ( 18a . 18b . 18c ) with corresponding field electrodes ( 14a . 14b . 14c ). Method according to claim 12, characterized in that the isolation structure ( 15 ) is formed as a thermal oxide. Method according to claim 12 or 13, characterized in that as a conductive material ( 21 ) Polysilicon is used. Method according to claim 12 to 14, characterized in that the etching mask ( 22 ) is formed as a structured photoresist.

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