DE102006055151B4 - Semiconductor device with a semiconductor zone and method for its production - Google Patents

Semiconductor device with a semiconductor zone and method for its production

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DE102006055151B4
DE102006055151B4 DE200610055151 DE102006055151A DE102006055151B4 DE 102006055151 B4 DE102006055151 B4 DE 102006055151B4 DE 200610055151 DE200610055151 DE 200610055151 DE 102006055151 A DE102006055151 A DE 102006055151A DE 102006055151 B4 DE102006055151 B4 DE 102006055151B4
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semiconductor
region
semiconductor region
zone
conductivity type
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DE102006055151A1 (en
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Elmar Dr. Falk
Franz Dr. Hirler
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/8611Planar PN junction diodes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402Field plates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816Lateral DMOS transistors, i.e. LDMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692Surface layout
    • H01L29/0696Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs

Abstract

Semiconductor device comprising:
- A semiconductor substrate (8) of the first conductivity type, wherein the semiconductor substrate (8) has a first surface (10);
- At least a first semiconductor region (1) of the first conductivity type complementary second conductivity type, which is arranged in the semiconductor substrate (8);
- At least a second semiconductor region (2) of the second conductivity type disposed in the semiconductor substrate (8) and spaced from the first semiconductor region (1), wherein the first and second semiconductor region (1, 2) respectively on the first surface (10) is arranged ; and
- A removable semiconductor zone (6) of the second conductivity type, which extends at least from the first to the second semiconductor region (1, 2), wherein the semiconductor zone (6) is a buried semiconductor zone, and wherein the first and second semiconductor region (1, 2) can not be completely cleared out.

Description

  • BACKGROUND
  • In order to mitigate the risk of electrical breakdowns in high-blocking components such as power diodes or power semiconductors, solution approaches have been developed for planar pn junctions with inhomogeneous edge regions in order to reduce the electric field as uniformly as possible within the edge region. In such arrangements, therefore, one speaks of an "edge termination" or an "edge structure".
  • One of these approaches provides so-called "field rings". Additional field rings lead to a voltage distribution over the edge region and therefore to an increased dielectric strength of the component.
  • Other approaches include: field plates, junction termination (JTE, VLD, variation of lateral doping), the RESURF (Reduced Surface Field), floating metal rings over the semiconductor, and various types of passivation layers, such as α-Si. SIPOS (Semi-Insulating Polysilicon) and DLC (Diamond Like Carbon).
  • Frequently floating field rings are used for high-blocking components, contacted with single or multi-stage field plates. However, such edge statements have a high space requirement. In addition, at the corners of the pn junction, for example at the edge of a p-well, and at each field ring electric field peaks remain. These occur even with static blocking load and sometimes amplify dramatically during dynamic shutdown of the device. Multilevel field plates can be used to attenuate field peaks in the semiconductor substrate to a certain extent. However, stray fields occur at the field plate edges, which can lead to additional field peaks even in dielectric layers on the semiconductor substrate as well as in the semiconductor itself. In order to achieve the desired properties, the length and spacing of the respective field plates must be dimensioned correctly, which is relatively complicated. Even with optimum dimensioning, the full volume breakdown voltage can not be achieved with this type of edge termination. Volumetric breakdown voltage means the breakdown voltage of the device in the interior, where the pn junction is flat.
  • In the post-published DE 10 2005 041 322 A1 For example, an edge terminated semiconductor device having a plurality of field rings interconnected by a lightly doped region is described.
  • The DE 102 26 664 A1 describes a compensation construction with buried p-compensation columns in an n-drift zone. The compensation columns are interconnected by weakly doped p-regions. The doping of the compensation columns is chosen in comparison to the drift zone so that they cancel each other out in the blocking case.
  • Out DE 197 41 167 A1 is a semiconductor device with a VLD edge termination is known, which has a decreasing dopant concentration in the lateral direction.
  • The DE 101 00 802 C1 also describes a compensation component with p-compensation columns, which are arranged both in the cell field and in the edge region of the component.
  • SUMMARY
  • In one embodiment, a semiconductor device is provided. The semiconductor device has a semiconductor substrate of the first conductivity type, wherein the semiconductor substrate ( 8th ) a first surface ( 10 ) having; at least a first semiconductor region of the first conductivity type complementary second conductivity type, which is arranged in the semiconductor substrate; at least one second semiconductor region of the second conductivity type arranged in the semiconductor substrate and spaced from the first semiconductor region, wherein the first and second semiconductor regions ( 1 . 2 ) each at the first surface ( 10 ) are arranged; and a removable semiconductor zone of the second conductivity type, which extends at least from the first to the second semiconductor region, wherein the semiconductor zone ( 6 ) is a buried semiconductor zone, and wherein the first and second semiconductor regions ( 1 . 2 ) are not completely cleared out.
  • The expandable semiconductor zone effectively attenuates field peaks at the first and second semiconductor regions. Furthermore, in the case of rapid switch-on processes, charge carriers can flow away from the second semiconductor region via the semiconductor region which can be emptied, so that substantially less free charge carriers remain in the second semiconductor region and therefore can not contribute to field peaks there. In addition, the semiconductor device allows the use of comparatively simple structured field plates, so that consuming dimensioned field plates or even on field plates altogether can be dispensed with. This considerably simplifies the process management for producing the semiconductor component, which can save costs.
  • BRIEF DESCRIPTION OF THE FIGURES
  • In the following the invention will be described with reference to exemplary embodiments shown in the attached figures, from which further advantages and modifications result. However, the invention is not limited to the specific embodiments described, but may be suitably modified and modified. It is within the scope of the invention to combine individual features and feature combination of an embodiment with features and feature combinations of another embodiment.
  • 1 shows an embodiment with a first and a second semiconductor region and a removable semiconductor zone.
  • 2 shows an exemplary embodiment with a first and a second semiconductor region, a buried expandable semiconductor zone and a fourth semiconductor region, which forms a channel stopper.
  • 3 shows an illustrative example with a first, second and third semiconductor region and a semiconductor erodable zone at the surface of a semiconductor substrate.
  • 4 shows an embodiment of a lateral semiconductor device having a first, second, third and fourth semiconductor region and a removable semiconductor zone, which connects the first, second and third semiconductor region with each other.
  • 5 shows a plan view of the surface of in 4 shown embodiment.
  • 6 1 shows the mode of action of the expandable semiconductor zone on the basis of an exemplary embodiment having a first, second and third semiconductor region and a dischargeable semiconductor zone which connects the first, second and third semiconductor substrate to one another.
  • 7 shows a three-dimensional view of a model structure of a lateral semiconductor device that has been used for simulations.
  • 8th shows a simulation of the potential distribution of the model structure with a removable semiconductor zone on the surface of the semiconductor substrate.
  • 9 shows a simulation of the potential distribution of the model structure with a buried emptying semiconductor zone.
  • 10 shows a schematic representation of the field distribution over a planar pn junction.
  • 11 shows the extent of the depletion zone in the edge region of a planar pn junction.
  • 12A to 12C show individual process steps for the production of a semiconductor device.
  • DETAILED DESCRIPTION
  • Below, some embodiments will be explained. In this case, the same structural features in the figures are identified by the same reference numerals.
  • In order to improve the barrier properties of pn junctions and in particular to improve the breakdown properties of power semiconductors in the edge region of planar pn junctions, a removable semiconductor zone is provided. For better understanding, first up 1 referenced, which is a border area 20 a semiconductor substrate 8th shows. The semiconductor substrate 8th has an edge 16 on, which is the outer edge of the semiconductor substrate 8th forms. The semiconductor substrate 8th extends laterally and has a significantly greater extent in the lateral direction than in the vertical direction (thickness direction). For example, the semiconductor substrate 8th a thin crystal disk cut out of a semiconductor wafer by suitable separation techniques.
  • An interior area 18 is from the edge 16 spaced. Between the interior 18 and the edge 16 extends the edge area 20 , The extent of the interior area 18 will be roughly through to the edge 20 pointing edge 38 a first semiconductor region 1 Are defined. In the first semiconductor region 1 For example, this is a main or load transition of a power semiconductor. This main or load transition has one compared to the edge area 20 significantly larger lateral extent. In 1 is for better understanding, only an outer partial section of the semiconductor substrate 8th shown. The semiconductor substrate 8th and thus also the first semiconductor region 1 extend into 1 still further to the left.
  • The first semiconductor area 1 forms together with the semiconductor substrate 8th at least in a subsection a vertical pn junction. The vertical pn junction, ie the interface between the first semiconductor region 1 and semiconductor substrate 8th . extends substantially parallel to the lateral extent of the semiconductor substrate. At the edge of the first semiconductor region 1 on the other hand, is the interface between the first semiconductor region 1 and semiconductor substrate 8th curved. The pn junction is no longer vertical there, but its orientation changes locally.
  • In the semiconductor substrate 8th is a semiconductor zone 6 arranged, extending from the first semiconductor region 1 at least up to a second semiconductor region 2 extends. For clarity, is the semiconductor zone 6 shown in dashed lines. The first and second semiconductor regions 1 . 2 are laterally spaced from each other, ie they do not contact each other and extend from a first surface 10 of the semiconductor substrate 8th from in the vertical direction in the semiconductor substrate 8th to a certain depth. The first and second semiconductor substrates 1 . 2 are therefore in the semiconductor substrate 8th at its first surface 10 arranged. The first surface 10 opposite, the semiconductor substrate 8th a second surface 22 on. The first surface 10 is often used as the main surface of the semiconductor substrate 8th referred to as the semiconductor device is essentially built on this surface. The first and second surface 10 . 22 of the semiconductor substrate 8th lie parallel to its lateral extent. The first semiconductor area 1 has along a line in the lateral extent of the semiconductor substrate 8th runs, a greater extent than the second semiconductor region 2 , The lateral extent of the second semiconductor region 2 is about between 3 microns and 50 microns. This extent also depends on the manner of production. By contrast, the lateral extent of the first semiconductor region can be up to several centimeters in the case of power semiconductors. The lateral extent is also dependent on the current to be switched, since high currents require correspondingly larger areas.
  • The second semiconductor region 2 forms in the present embodiment, for example, a field ring or a field zone, for example, in plan view of the first surface 10 of the semiconductor substrate 8th around the first semiconductor region 1 runs. The second semiconductor region 2 then forms a closed ring around the first semiconductor region 1 , Between edge 16 and first semiconductor region 1 is therefore circumferential around the first semiconductor region 1 the second semiconductor region 2 arranged. This is also the interior 18 completely from the edge area 20 surround. The second semiconductor region 2 has the function of the electrical conditions at the outer edge of the first semiconductor region 1 to improve.
  • Typically, the first and second semiconductor regions 1 . 2 highly doped regions compared to the rather weakly doped semiconductor substrate 8th , The first and second semiconductor regions 1 . 2 may for example have a mean impurity concentration of about 10 16 / cm 3 . This impurity concentration is reached at the surface of the semiconductor substrate and decreases with the depth. Typically, the impurity concentration of the first and second semiconductor regions is 1 . 2 at the surface approximately between 10 15 / cm 3 and 10 19 / cm 3 . In contrast, the semiconductor substrate is 8th weakly doped and has an impurity concentration of about 10 12 / cm 3 to about 10 15 / cm 3 . The semiconductor substrate 8th is of the first conductivity type, whereas the first and second semiconductor regions are 1 . 2 of the second conductivity type complementary to the first conductivity type.
  • The semiconductor zone 6 , which is of the second conductivity type, on the other hand, has a low impurity concentration, so that the semiconductor region 6 is eliminated when the pn load transition between the first semiconductor region 1 and semiconductor substrate 8th is operated in the reverse direction. By removable semiconductor zone is meant a semiconductor region having a charge carrier amount of impurity (impurity charge) substantially equal to or smaller than the breakdown charge. The charge carrier quantity and the breakdown charge are given as a dose, ie they have the unit charge / area. The breakdown charge is linked via the Poisson equation with the critical breakdown field strength, which has a typical value for each semiconductor material, which additionally depends on the impurity concentration. Specifically, this is related to 10 explained.
  • Typically, the semiconductor zone 6 an impurity concentration (unit per unit volume) smaller than the impurity concentration of the first or second semiconductor region by a factor equal to or greater than 10 2 , equal to or greater than 10 3, or even equal to or greater than 10 4 1 . 2 , It is favorable if the semiconductor zone 6 a lower by a factor of 10 3 to 10 4 lower impurity concentration than the first and second semiconductor region 1 . 2 Has. The semiconductor zone 6 is then weaker by this factor. This is intended to ensure that the semiconductor zone 6 completely cleared when operating the pn junction in the reverse direction. In contrast, the first and second semiconductor regions become 1 and 2 not completely cleared. In addition, their impurity concentration is too high. Furthermore, the semiconductor zone has 6 in the vertical direction typically only a small extent. The vertical extent of the semiconductor zone is preferred 6 less than the vertical extent of the first and second semiconductor regions 1 . 2 , For example, the vertical extent of the semiconductor zone 6 be about 5 microns. A preferred range for the vertical extension of the semiconductor zone 6 is between 2 μm and 10 μm. The first and second semiconductor regions 1 . 2 extend from the first surface 10 depending on the application, to a depth of approx. 3-50 μm. At higher voltage classes, the semiconductor regions extend deeper in the semiconductor substrate than in smaller voltage classes. The vertical extent of semiconductor regions 1 . 2 and semiconductor zone 6 is determined, for example, on the one hand by the implantation conditions and on the other hand by the subsequent temperature step.
  • In the embodiment according to 1 is the semiconductor zone 6 buried, ie it is from the first surface 10 of the semiconductor substrate 8th spaced. Thus remains between the semiconductor zone 6 and the first surface 10 a region of the semiconductor substrate 8th of the first conductivity type. The maximum of the impurity concentration of the semiconductor zone 6 can be approximately at the level of the vertical pn junction of the first semiconductor region 1 lie, ie for example at a depth of about 5 microns.
  • As in 2 shown on the first surface 10 of the semiconductor substrate 8th above the first and second semiconductor regions 1 . 2 one optional field plate each 12 . 14 be arranged with the respective semiconductor region 1 . 2 is electrically connected. The field plates 12 . 14 serve the additional attenuation of electrical field elevations in the semiconductor substrate.
  • The field plates 12 . 14 can be single or multi-level. The field plate 12 is with the first semiconductor region 1 electrically connected and is therefore at the electrical potential that is applied to the first semiconductor region 1 is externally created. In contrast, the second semiconductor region becomes 2 is not subjected to a fixed external potential. The second semiconductor region 2 is for example a floating field ring. Therefore, the one with the semiconductor region also floats (is not at fixed electrical potential) 2 electrically conductive field plate 14 ,
  • Field elevations at the first and second semiconductor region 1 . 2 can also be weakened by multi-level field plates. However, it is only possible with field plates to a limited extent, electrical field peaks at the edge of the first and second semiconductor region 1 . 2 uniformly avoid, which occur at static blocking load and sometimes even amplify dramatically during dynamic shutdown of the semiconductor device. The effectiveness of field plates depends essentially on their geometric configuration and in particular their distance from the surface of the semiconductor substrate. The closer the field plate is to the surface, the more effectively the field maximum at the corners of the semiconductor regions (main region and field rings) is attenuated, but the field peak in the semiconductor under the edge at the end of the field plate increases. Therefore, the length and distance of the respective field plate must be properly dimensioned.
  • Furthermore, in 2 a fourth semiconductor region 4 shown, that of the second semiconductor region 2 is spaced. The fourth semiconductor area 4 is in the semiconductor substrate 8th from the first semiconductor region 1 from behind the second semiconductor region 2 arranged. The fourth semiconductor area 4 is in this embodiment of the first conductivity type and extends from the surface 10 of the semiconductor substrate 8th in the vertical direction to a certain depth. In this in 2 the embodiment shown forms the fourth semiconductor region 4 For example, a so-called channel stopper. Such channel stoppers are in the edge area 20 and especially at the edge 16 of semiconductor substrates 8th provided to the extent of the space charge zone against the edge 16 to limit. Typically, the fourth semiconductor region 4 in comparison to the semiconductor substrate 8th highly endowed.
  • Additionally is in 2 a contact layer 24 shown on the second surface 22 of the semiconductor substrate 8th is arranged. By means of the contact layer 24 can the
  • Semiconductor substrate 8th be contacted. For example, high-blocking diodes forms the contact layer 24 the cathode, while as the anode also a contact layer is applied, with the field plate 12 and the first semiconductor region 1 (Main area) is electrically conductively connected. A voltage applied between the anode and the cathode then leads, depending on their polarity, to a blocking or transmission of the pn junction between the first semiconductor region 1 and semiconductor substrate 8th ,
  • A significant improvement in the barrier properties of a semiconductor device is achieved by the erodible semiconductor zone 6 reached. In 2 is for better understanding, for example, the doping of the individual structures in the semiconductor substrate 8th shown. Here, "n - " means a lightly doped n-type region, "n + " a heavily doped n-type region, "p + " a heavily doped p-type region, and "p - " a weakly doped p-type region. P-type means that the majority carriers are holes, while in n-type regions these are electrons. The first and second semiconductor regions 1 . 2 are p + doped, the semiconductor zone 6 is p - doped, the semiconductor substrate is n - doped and the fourth semiconductor region 4 (here channel stopper) is n + -doped. Through the semiconductor zone 6 become additional charges and in particular solid impurities in the semiconductor substrate 8th brought in. Thus, more solid impurities are available at which field lines end, which otherwise ends up in the first or second semiconductor region 1 . 2 would be enough and there to local lead electrical field strength peaks. As a result, the dielectric strength in the edge region of the first semiconductor region 1 improved, resulting in a total of the effectively achievable blocking voltage of in 2 shown diode junction significantly increased. For the person skilled in the art, it goes without saying that the exemplary embodiments described here also apply to n-type semiconductor regions embedded in a p-type semiconductor substrate, ie "n" and "p" can be exchanged accordingly.
  • In the case of blocking, the semiconductor zone is 6 cleared at sufficiently high reverse voltage, ie there are no free majority carriers for charge transport available. The semiconductor zone then has a high electrical resistance. Therefore, the first and second semiconductor regions 1 . 2 electrically isolated from each other in the blocking case. As a result, the second semiconductor region 2 opposite to the first semiconductor region located at a fixed potential 1 float.
  • As it turns out, the semiconductor zone has 6 another advantage. When the semiconductor component or the pn junction is switched on rapidly, charges may remain on each field plate since the pn junction of the second semiconductor region 2 When switching on briefly Sperrpolpolt is. As a result, very high electric field peaks, but at the first semiconductor region 1 pointing inside edges 17 the field plates 14 occur. Such field peaks are particularly pronounced in dielectrics (not shown here), which on the first surface 10 of the semiconductor substrate 8th are arranged. In addition, the electric field peaks can also be in the semiconductor substrate 8th occur, which can lead to destruction of the pn junction and thus of the semiconductor device. The negative influence of such field peaks on to the first semiconductor region 1 pointing edges have not been sufficiently considered in conventional semiconductor devices. The semiconductor zone 6 prevents such electric field peaks.
  • In Durchlassfall or when switching from reverse to forward direction fills the semiconductor zone 6 at least partially again with majority charge carriers, so that an at least partially electrically conductive connection between the first and second semiconductor region 1 and 2 will be produced. As a result, charges, for example, in the case of blocking in the second semiconductor region 2 remained and could not flow away from there, to the first semiconductor area 1 flow.
  • In 3 an illustrative example is shown. This example is compared to 2 a third semiconductor region 3 of the second conductivity type laterally to the second semiconductor region 2 spaced so that the second semiconductor region 2 lies between the first and third semiconductor region. The second and third semiconductor regions 2 . 3 form field rings surrounding the first semiconductor region 1 run. In this case, the lateral distance between the second and third semiconductor region 2 . 3 greater than the lateral distance between the first and second semiconductor regions 1 . 2 be. This improves the effect of the field rings. A channel stopper is not shown in this example, but can be added as needed. The excavable semiconductor zone 6 is here for example at the first surface 10 of the semiconductor substrate 10 arranged and connects the first semiconductor region 1 with the second and third semiconductor regions 2 . 3 , As has been shown, this variant also allows to effectively avoid electric field spikes. If appropriate, further field rings, for example 20 to 50 field rings, can be provided.
  • 1 to 3 show vertical semiconductor devices. These are in particular the first semiconductor region 1 with a connection (eg anode) as well as the second surface 22 (Back) with a connection or contact layer 24 (eg, cathode) to electrically contact each of them.
  • In 4 is an embodiment of a lateral semiconductor device, such as a power transistor, shown in which the auseräumbare semiconductor zone 6 , which again is a buried zone here, the first semiconductor area 1 with the second semiconductor region 2 and the optional third semiconductor region 3 combines. Spaced to the second and third semiconductor region 2 . 3 and to the semiconductor zone 6 is a fourth semiconductor area 4 arranged. First, second and optional third semiconductor region 1 to 3 as well as the semiconductor zone 6 are of the second conductivity type as opposed to the semiconductor substrate 8th and the fourth semiconductor region 4 which are of the first conductivity type. Typically, the fourth semiconductor region 4 in contrast to the semiconductor substrate 8th highly doped and in this embodiment provides a connection zone for contacting a drift zone 15 In lateral power transistors forms the fourth semiconductor substrate 4 typically drain. The fourth semiconductor area 4 is here in particular with a connection D (drain connection) for contacting the fourth semiconductor region 4 connected, wherein the terminal D at the surface of the fourth semiconductor region 4 is arranged. Between the fourth semiconductor region 4 facing right edge 38 of the first semiconductor region 1 and the first semiconductor region 1 facing left edge 43 of the fourth semiconductor region 4 extends the drift zone 15 , which in this embodiment represents a lightly doped drain region into which the second and third semiconductor regions 2 . 3 embedded as field rings or field zones. It goes without saying that Depending on the application, more than one field ring or field zone (second semiconductor region), for example two field rings or field zones (second and third semiconductor region) or even more field zones or field rings, in the drift zone 15 can be embedded.
  • A fifth semiconductor area 5 of the first conductivity type is in the first semiconductor region 1 arranged and forms there Source. In particular, here is the fifth semiconductor region 5 with a terminal S (source terminal) for contacting the fifth semiconductor region 5 connected, wherein the terminal S on the surface of the fifth semiconductor region 5 is arranged. The fifth semiconductor area 5 is from the fourth semiconductor area 4 pointing edge 38 of the first semiconductor region 1 at which the drift zone 15 starts, spaced. This is the first semiconductor area 1 a channel area 37 (Body region) between the fifth semiconductor region 5 and the drift zone 15 which is via a gate electrode 27 that are above the channel area 37 of the first semiconductor region 1 is arranged, can be switched. The first semiconductor area 1 has no connection in this embodiment. The drift zone 15 serves to reduce the high voltage between source and drain. Typically, the fifth semiconductor region is compared to the semiconductor substrate 8th and the first semiconductor region 1 highly endowed.
  • The semiconductor substrate 8th points below a first semiconductor region 8a of the first conductivity type, a second semiconductor region 8b of the second conductivity type. The second semiconductor area 8b is to the second surface 22 of the semiconductor substrate 8th turned and serves to reduce the drain voltage in the vertical direction. The first to fifth semiconductor area 1 bi 5 are at the first surface 10 in the first semiconductor area 8a embedded. The semiconductor zone 6 On the other hand, it is preferably completely in the first semiconductor region 8a buried. The second semiconductor area 8b here represents a deeply buried semiconductor region, which is below the semiconductor zone 6 and the semiconductor regions 1 to 5 arranged and spaced therefrom. Semiconductor region 8a is in the present embodiment n- or n - doped and semiconductor region 8b p - doped. Alternatively, the semiconductor region 8b also be n - doped. Semiconductor substrates with vertically stacked complementary semiconductor regions can be produced for example by epitaxy.
  • In the 4 The structure shown thus represents a lateral semiconductor component with a lateral pn junction. In contrast to a vertical semiconductor component, the fourth and fifth semiconductor regions are in the case of lateral semiconductor components 4 . 5 each provided with a connection, the first semiconductor region 1 not.
  • In 4 not shown, merely representative at one point with a dotted line, are field plates which are arranged in trenches. Such trenches shows 5 , which is a plan view of the first surface 10 of the semiconductor substrate 8th represents. To illustrate the spatial arrangement, a reference coordinate system is selected, wherein the first surface 10 here in the XZ plane. This level shows 5 , 4 on the other hand shows a section in XY plane. Perpendicular to the XZ plane, ie in the XY plane, a trench extends 29 in -Y direction. The ditch 29 extends in the X direction almost to the fourth semiconductor substrate 4 (Drain) zoom. In the ditch 29 are field plates 12 and 14 represented parallel to the trench walls in the depth of the semiconductor substrate 8th extend. The field plate 12 is doing with the first semiconductor region 1 and one field plate each 14 with the second or third semiconductor region 2 . 3 connected. The field plates 12 . 14 in the ditch 29 assist the clearing out of the buried semiconductor zone 6 under blocking conditions. The field plate 12 can also be connected directly to the source or gate potential.
  • In the 5 The structure shown is mirror-symmetric with respect to the plane 31 which is parallel to the XY plane here. For better understanding is in 5 in the 4 Plotted section along AA 'drawn.
  • The field plates 12 . 14 are each with a contact structure 45 with the respectively associated semiconductor regions 1 to 3 electrically connected. The contact structures 45 are arranged only in the near-surface area. In contrast, the field plates extend 12 . 14 considerably further into the depth of the trench 29 ,
  • At the in 4 and 5 The embodiment shown are the first semiconductor region 1 p-doped, the second and third semiconductor region 2 . 3 p + - or p-doped, the fourth and fifth semiconductor region 4 and 5 n + -doped, the semiconductor zone 6 p - doped and the first semiconductor region 8a n - doped. The second semiconductor area 8b is p - doped.
  • The mode of action of the expandable semiconductor zone 6 is to be explained without limiting itself, using the example of an edge termination of a vertical pn junction. Serves 6 showing the edge area of a power diode. An anode electrode 28 is on the first surface 10 of the semiconductor substrate 8th in the region of the first, here p + -doped, semiconductor region 1 arranged. Opposite on the second surface 22 of the semiconductor substrate 8th is a cathode 30 with the here n - doped semiconductor substrate 8th connected. Between anode 28 and cathode 30 is a blocking voltage. The second and third semiconductor area 2 . 3 are like the first semiconductor area 1 p + doped. The semiconductor zone 6 is buried here again and in comparison to the semiconductor areas 1 to 3 weakly p-doped. The first semiconductor area 1 again represents a pn load transition, while the second and third semiconductor region 2 . 3 each forms a field ring. The extent of the depletion or space charge zone 32 in the blocking case in the n - semiconductor substrate 8th and in the first, second and third semiconductor regions 1 to 3 is shown dotted. It can be seen that the space charge zone 32 significantly further in the lightly doped semiconductor substrate 8th as in the heavily doped semiconductor regions 1 to 3 expands. The reason is that the charge balance in the space charge zone 32 must always be zero, ie that there must always be just as many positive and negative fixed charges. However, this can only be achieved if the space charge zone 32 deeper into the weaker doped semiconductor substrate 8th expands.
  • As in 6 indicated, is the space charge zone 32 unbalanced with respect to the left edges 41 and the right edges 39 of the second and third semiconductor regions 2 . 3 , This is because on the left edges 41 the pn junction is local in the forward direction and therefore the space charge zone 32 there to the left edge 41 zoom ranges.
  • The electric field lines begin and end at fixed charges, which are provided by the impurities. In the n - semiconductor substrate 8th they are solid positive charges or hulls 34 and in the p-doped semiconductor regions 1 to 3 and the p-type semiconductor region 6 solid negative charges or hulls 36 , Part of the field lines, represented by arrows, ends at fixed negative charges 36 passing through the semiconductor zone 6 to be provided. As a result, the field strength is particularly at edges 38 . 39 the first to third semiconductor regions 1 to 3 diminished and there occurring electrical field overshoots avoided.
  • The electrical potentials of the field rings, ie the second and third semiconductor region 2 and 3 , by themselves adjust to values that are between the potentials of anode 28 and cathode 30 lie. For example, is an anode 28 to 0 V and cathode to 300 V so is the second semiconductor region 2 for example, at about 100 V and the third semiconductor region, for example at 200 V. Electrically with the second and third semiconductor regions 2 and 3 connected optional field plates are then at the same electrical potential as the semiconductor regions connected to them. This results in a uniform voltage drop, especially along the first surface 10 reached. Overall, the probability of the occurrence of electrical breakdowns on edges can be 38 . 39 and significantly reduce in curved areas of the pn junctions and significantly increase the effective breakdown voltage. The result is a significant improvement in the blocking behavior of the components. The achievable breakdown voltages are higher than 75-80% of the volume breakdown voltage and can approach values close to the volume breakdown voltage.
  • The improvement compared to 11 which shows a planar pn junction without edge termination. On edge 38 occurs a strong field overshoot, which leads there to an electrical breakdown well below the volume breakdown voltage.
  • 7 shows a three-dimensional model structure of a lateral pn junction for the simulation of the electrical conditions. This model structure is similar to the one in 4 and 5 shown embodiment. On the left you can see the body area (first semiconductor area) 40 and right drain 50 , In between this is the drain 50 and body area 40 weakly complementary doped semiconductor substrate 42 in which field rings 46 are introduced. The field rings 46 have depressions 48 on, which are filled with an electrically conductive material, such as polysilicon, and the contact with field plates 44 produce. The field plates 44 lie parallel to vertical surfaces of trench walls in the semiconductor substrate 42 which extend into the depth of the semiconductor substrate. The main area 10 of the semiconductor substrate is here again in XZ_Ebene and the trench extends in the -YX direction. In the 7 YX plane shown corresponds approximately to the plane of symmetry 31 in 5 ,
  • The simulation results are based on cutting planes along the plane of symmetry in the 8th and 9 shown. The structure of the simulation is shown above the results showing the course of the electrical potentials. The doping concentrations on which the simulation was based were optimized for maximum breakdown voltage. In 8th is the excavable semiconductor zone 52 on the surface of the semiconductor substrate 42 arranged. In contrast, the salvageable semiconductor zone 52 in 9 buried. The comparison of the simulation results shows that a buried semiconductor zone 52 Compared to a surface mounted semiconductor zone can avoid field strength peaks more effectively. This can be seen in particular when comparing the potential curve in the upper right corner. In the surface of the semiconductor zone arranged 52 the potential lines condense to drain 50 out. In the buried semiconductor zone 52 On the other hand, the potential lines are much less dense and along the surface of the semiconductor substrate 42 rather equidistant. This means that the electric field drops evenly there. Field strength peaks are thus avoided. Through the buried semiconductor zone 52 For example, an improvement in blocking capability from 181 V to 275 V, or 52%, could be achieved. The effect of the erodible semiconductor zone is therefore of great advantage, in particular in the case of power semiconductors, which are designed for high blocking voltages.
  • The term breakthrough charge is intended below with reference to 10 be explained. 10 shows in the upper part of the schematically indicated typical course of the electric field over a flat, abrupt pn junction at the breakdown voltage. In the lower part of the 10 is a pn-transition 54 represented by a heavily p-doped region (p + ) 56 and a weakly n-doped region (n - ) 58 is formed. Due to the different doping has the depletion zone whose edges with 59 are designated, a different extent in the two areas 56 and 58 , With w D the expansion is in the n - region 58 and w A is the extent in the p + region 56 designated. On the other hand, the impurity concentration is N A for the p + region 56 and with N D for the n - region 58 specified. From the Poisson equation follows N A · w A = N D · w D (1)
  • From the Poisson equation follows
    Figure 00170001
    so that the breakdown charge N D · w D to
    Figure 00170002
    where E crit is the critical field strength at which volume breakthrough occurs, ε is the product of absolute and relative dielectric constant, and q is the elementary charge.
  • The critical field strength E crit varies with the impurity concentration (basic doping of the semiconductor substrate) and decreases with decreasing fundamental doping. The basic doping thus determines the voltage class. For example, the basic doping for a voltage class of 1200 V is about 6 × 10 13 / cm 3 . E crit is then about 230 kV / cm. With a voltage class of about 10 kV, the basic doping is correspondingly lower, so that then E crit about 165 kV / cm and the breakdown charge is about 1.1 · 10 12 / cm 2 . With a voltage class of about 100 V, on the other hand, E crit is between about 350 kV / cm and 400 kV / cm and the breakdown charge is about 2.4 · 10 12 / cm 2 . In general, the high-blocking silicon devices E crit about 250 kV / cm or less, so that thus results in an breakdown charge of about 1.6 · 10 12 cm -2 or smaller. For low-voltage components E crit is significantly higher, so that the breakdown charge can be at some 10 12 / cm 2 . Therefore, in silicon semiconductor devices, it is preferable that the breakdown charge in the semiconductor region 6 is less than 5 x 10 12 / cm 2 and especially less than 3 x 10 12 / cm 2 . Other semiconductor materials have other critical field strengths. In order to ensure that the emmeable semiconductor zone can be completely cleared of free charge carriers in the blocking case, a charge carrier concentration of less than the breakdown charge is therefore set in the case of semiconductor devices based on silicon semiconductors. This can easily be adjusted by the implantation dose used for the production of the evacuable semiconductor zone. It goes without saying that the embodiments are not limited to silicon semiconductors but are also applicable to all other semiconductor materials such as germanium, silicon carbide or III-V semiconductors.
  • If the impurity concentration N is spatially inhomogeneous, the breakdown charge results from a one-dimensional integration over N (x).
  • The semiconductor components described above are, in particular, power semiconductor components which can be designed both as vertical and as lateral components.
  • Below is with reference to 12A to 12C a manufacturing method for producing a semiconductor device will be described.
  • In 12A becomes a semiconductor substrate 60 of the first conductivity type, for example a weakly n-doped silicon substrate, with a first surface 61 provided. By means of a first implantation mask 62 Dopants, such as boron, from the second conductivity type complementary to the first conductivity type in the first surface 61 with a first implantation dose 68 for example, about 10 14 / cm 2 introduced. The dopants are implanted to a certain depth. By a subsequent annealing step, a first doping region 64 and a second doped region laterally spaced therefrom 66 created. The annealing step serves to heal crystal lattice damage caused by the implantation and to drive and activate the dopants. The lateral extent of the doping regions 64 and 66 depends, on the one hand, on the structure of the first implantation mask 62 and second, the duration and temperature of the annealing step. Depending on the selected temperature, the dopants may vary widely in the semiconductor substrate 60 diffuse and thereby increase both the lateral and the vertical extent of the doping regions 64 and 66 , Thus, an initial doping region having a lateral extent of about 10-15 μm can be extended by the annealing step to about 20-50 μm.
  • Then follows, as in 12B shown, the implantation of second conductivity type dopants, such as boron, with a second implantation dose 72 using a second implantation mask 70 , This becomes a buried semiconductor zone 74 educated. For this purpose, the implantation energy used is higher than that for forming the first and second semiconductor regions 64 and 66 used implantation energy, so that the dopants deeper into the semiconductor substrate 60 to about the same level as the pn junction between the semiconductor regions 64 . 66 and the semiconductor substrate 60 be implanted. The second implantation dose 72 is significantly lower than the first implantation dose 68 For example, by a factor equal to or greater than 10 2 or equal to or greater than 10 3 . The second implantation dose 72 is below the breakdown charge for silicon substrates, preferably below 10 12 / cm 2 . An annealing step may follow.
  • Finally, as in 12C shown on the first surface 61 field plates 76 formed with the first and second semiconductor region 64 . 66 are electrically connected. Also, on one of the first surface 61 opposite second surface 78 of the semiconductor substrate 60 a contact layer 80 be applied.
  • Notwithstanding the process described above, the buried semiconductor zone can also first 74 and then the first and second semiconductor regions 64 . 66 be formed. In addition, it is possible to provide the first and second semiconductor regions in succession. Likewise, only a single annealing step can be provided, with which the first and second semiconductor region 64 . 66 and the buried semiconductor region 74 be healed. In addition, the first and second semiconductor regions 64 . 66 also by outdiffusion of dopants from one to the first surface 61 deposited highly doped layer are produced.

Claims (29)

  1. Semiconductor device comprising: - a semiconductor substrate ( 8th ) of the first conductivity type, wherein the semiconductor substrate ( 8th ) a first surface ( 10 ) having; At least a first semiconductor region ( 1 ) of the first conductivity type complementary second conductivity type in the semiconductor substrate ( 8th ) is arranged; At least one second semiconductor region ( 2 ) of the second conductivity type, which in the semiconductor substrate ( 8th ) and from the first semiconductor region ( 1 ), wherein the first and second semiconductor regions ( 1 . 2 ) each at the first surface ( 10 ) is arranged; and - a removable semiconductor zone ( 6 ) of the second conductivity type, which extend at least from the first to the second semiconductor region ( 1 . 2 ), wherein the semiconductor zone ( 6 ) is a buried semiconductor zone, and wherein the first and second semiconductor regions ( 1 . 2 ) are not completely cleared out.
  2. Semiconductor component according to Claim 1, in which the semiconductor zone ( 6 ) a lower impurity charge and / or impurity concentration than the first and second semiconductor regions ( 1 . 2 ) having.
  3. Semiconductor device according to claim 2, wherein the impurity concentration in the semiconductor zone ( 6 ) by at least a factor 10 2 and in particular by at least a factor 10 3 smaller than the impurity concentration of the second semiconductor region ( 2 ).
  4. Semiconductor component according to one of the preceding claims, wherein the first semiconductor region ( 1 ) together with the semiconductor substrate ( 8th ) forms a vertical pn junction at least in a subsection which extends substantially parallel to the lateral extent of the semiconductor substrate ( 8th ).
  5. Semiconductor component according to claim 4, wherein the maximum of the impurity concentration of the semiconductor zone ( 6 ) approximately at the level of the vertical pn junction of the first semiconductor region ( 1 ) lies.
  6. Semiconductor component according to one of the preceding claims, wherein along a line extending in the lateral extent of the semiconductor substrate ( 8th ), the first semiconductor region ( 1 ) has a greater extent than the second semiconductor region ( 2 ) Has.
  7. Semiconductor component according to one of the preceding claims, further comprising at least one third semiconductor region ( 3 ) of the second conductivity type, which in the semiconductor substrate ( 8th ) is arranged so that the second semiconductor region ( 2 ) between the first and third semiconductor regions ( 1 . 3 ) and spaced therefrom.
  8. Semiconductor component according to Claim 7, in which the semiconductor zone ( 6 ) at least from the first to the third semiconductor region ( 1 . 3 ).
  9. Semiconductor component according to one of the preceding claims, further comprising at least one fourth semiconductor region ( 4 ) of the first conductivity type, which in the semiconductor substrate ( 8th ) from the first semiconductor region ( 1 ) seen behind the second or third semiconductor region ( 2 respectively. 3 ) and from the second or third semiconductor region ( 2 respectively. 3 ) is spaced.
  10. Semiconductor component according to Claim 9, in which the semiconductor zone ( 6 ) of the fourth semiconductor region ( 4 ) is spaced.
  11. A semiconductor device according to claim 9 or 10, wherein a fifth semiconductor region ( 5 ) of the first conductivity type in the first semiconductor region ( 1 ) is arranged.
  12. Semiconductor component according to one of claims 9 to 11, wherein a drift zone ( 15 ) between the first and fourth semiconductor regions ( 1 . 4 ) in which the second or third semiconductor region ( 2 . 3 ) is arranged or are.
  13. A semiconductor device according to claim 12, wherein said fifth semiconductor region ( 5 ) from the drift zone ( 15 ), so that a channel region ( 37 ) in the first semiconductor region ( 1 ) between the fifth semiconductor region ( 5 ) and drift zone ( 15 ) remains.
  14. Semiconductor component according to claim 13, wherein above the channel region ( 37 ) a gate electrode ( 27 ) is arranged.
  15. Semiconductor component according to one of the preceding claims, wherein on the semiconductor substrate ( 8th ) at least one field plate ( 14 ) arranged with the second semiconductor region ( 2 ) connected is.
  16. Semiconductor component according to one of the preceding claims, wherein the semiconductor zone ( 6 ) has an impurity charge smaller than the breakdown charge for the semiconductor substrate.
  17. Semiconductor component according to one of the preceding claims, wherein the semiconductor substrate ( 8th ) one of the first surface ( 10 ) opposite second surface ( 22 ), on which a contact layer ( 24 ) is arranged.
  18. Semiconductor device comprising: - a semiconductor substrate ( 8th ) of the first conductivity type with an interior area ( 18 ) and a border ( 16 ) as well as between indoor area ( 18 ) and edge ( 16 ) edge area ( 20 ); At least a first semiconductor region ( 1 ) of the first conductivity type complementary second conductivity type in the semiconductor substrate ( 8th ) is arranged and in the direction of the lateral extent of the semiconductor substrate ( 8th ) to the edge area ( 20 ) extends; A second semiconductor region ( 2 ) of the second conductivity type, which is in the edge region ( 20 ) of the semiconductor substrate ( 8th ) and from the first semiconductor region ( 1 ), wherein the semiconductor substrate ( 8th ) a first surface ( 10 ), on which the first and the second semiconductor region ( 1 . 2 ) are arranged; A removable semiconductor zone ( 6 ) of the second conductivity type, which the first and the second semiconductor region ( 1 . 2 ), wherein the semiconductor zone ( 6 ) is a buried semiconductor zone, and wherein the first and second semiconductor regions ( 1 . 2 ) are not completely cleared out.
  19. A semiconductor device according to claim 18, wherein the semiconductor zone ( 6 ) a lower impurity charge and / or impurity concentration than the first and second semiconductor regions ( 1 . 2 ) having.
  20. A semiconductor device according to claim 19, wherein the impurity concentration in the semiconductor region ( 6 ) by at least a factor 10 2 and in particular by at least a factor 10 smaller than the impurity concentration of the first and second semiconductor regions ( 1 . 2 ).
  21. Semiconductor component according to one of Claims 18 to 20, the semiconductor substrate ( 8th ) one of the first surface ( 10 ) opposite second surface ( 22 ), on which a contact layer ( 24 ) is arranged.
  22. Semiconductor device comprising: - a semiconductor substrate ( 8th ) of the first conductivity type; At least a first semiconductor region ( 1 ) of the first conductivity type complementary second conductivity type in the semiconductor substrate ( 8th ) is arranged; At least one fourth semiconductor region ( 4 ) of the first conductivity type, which in the semiconductor substrate ( 8th ) and from the first semiconductor region ( 1 ) is spaced; At least one second semiconductor region ( 2 ) of the second conductivity type, which in the semiconductor substrate ( 8th ) between the first and fourth semiconductor regions ( 1 . 4 ) and spaced therefrom; and - a removable semiconductor zone ( 6 ) of the second conductivity type, which at least from the first semiconductor region ( 1 ) to the second semiconductor region ( 2 ), wherein - the semiconductor zone ( 6 ) of the fourth semiconductor region ( 4 ), so that a semiconductor region ( 15 ) of the first conductivity type between the semiconductor zone ( 6 ) and the fourth semiconductor region ( 4 ) remains.
  23. A semiconductor device according to claim 22, wherein the impurity concentration and / or the impurity charge in the semiconductor region ( 6 ) smaller than the impurity concentration and / or the impurity charge of the first and second semiconductor regions ( 1 . 2 ).
  24. A semiconductor device according to claim 22 or 23, wherein the semiconductor substrate ( 8th ) a first surface ( 10 ), on which the first, second and fourth semiconductor regions ( 1 . 2 . 4 ) are arranged.
  25. Semiconductor component according to claim 24, wherein the semiconductor zone ( 6 ) from the first surface ( 10 ) is arranged so that between the semiconductor zone ( 6 ) and the first surface ( 10 ) at least one semiconductor region of the first conductivity type remains.
  26. Semiconductor component according to one of claims 22 to 25, wherein a fifth semiconductor region ( 5 ) of the first conductivity type in the first semiconductor region ( 1 ) is arranged.
  27. Method for producing a semiconductor component, comprising: providing a semiconductor substrate ( 60 ) of the first conductivity type, wherein the semiconductor substrate ( 60 ) a first surface ( 61 ) Has; Introduction of impurities with a first implantation dose ( 68 ) for forming a first and a second semiconductor region ( 64 . 66 ) of the second conductivity type complementary to the first conductivity type; and - introduction of impurities with a second implantation dose ( 72 ) for forming a semiconductor zone ( 74 ) of the second conductivity type in the semiconductor substrate ( 60 ), the second implantation dose ( 72 ) lower than the first implantation dose ( 68 ), the implantation doses ( 68 . 72 ) are selected so that the semiconductor zone ( 74 ), the first and second semiconductor regions ( 64 . 66 ) are not completely cleared away, wherein - the first and second semiconductor region ( 64 . 66 ) are formed so that they in the semiconductor substrate ( 60 ) at its first surface ( 61 ) are arranged laterally spaced from each other; and the semiconductor zone ( 74 ) is formed so that it is formed as a buried semiconductor region and the first semiconductor region ( 64 ) with the second semiconductor region ( 66 ) connects.
  28. The method of claim 27, wherein the second implantation dose ( 72 ) by a factor of at least 10 2 , preferably by a factor of at least 10 3 smaller than the first implantation dose ( 68 ).
  29. The method of claim 27 or 28, wherein the second implantation dose ( 72 ) is one as the breakdown charge for the semiconductor substrate.
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