WO2021134889A1

WO2021134889A1 - Trench gate mosfet power semiconductor device, polycrystalline silicon-filling method therefor, and manurfacturing method therefor

Info

Publication number: WO2021134889A1
Application number: PCT/CN2020/077127
Authority: WO
Inventors: 张邵华; 杨彦涛; 隋晓明; 郭广兴
Original assignee: 杭州士兰微电子股份有限公司
Priority date: 2020-01-02
Filing date: 2020-02-28
Publication date: 2021-07-08
Also published as: CN111403282B; CN111403282A

Abstract

Provided are a trench gate MOSFET power semiconductor device (200), a polycrystalline silicon-filling method therefor, and a manufacturing method therefor. The filling method comprises: forming trenches (220) in an epitaxial layer (202) on a semiconductor substrate (201); forming an insulation layer (221) on a surface of the epitaxial layer (202) and in the trenches (220), the insulation layer (221) surrounding the trenches (220) to form a cavity (251); forming an i-th polycrystalline silicon layer on the surface of the epitaxial layer (202) and in the cavity (251); performing back etching on the i-th polycrystalline silicon layer; forming an (i+1)-th polycrystalline silicon layer on holes or gaps inside the exposed i-th polycrystalline silicon layer; removing the (i+1)-th polycrystalline silicon layer located above the surface of the epitaxial layer (202) and the insulation layer (221) located above the surface of the epitaxial layer (202), wherein the i-th polycrystalline silicon layer to the (i+1)-th polycrystalline silicon layer forms a shielding conductor; forming a plurality of polycrystalline silicon layers in the trenches (220) to eliminate holes or gaps, thereby improving the yield and reliability of the power semiconductor device (200) and extending the service life thereof.

Description

Trench gate MOSFET power semiconductor device and its polysilicon filling method and manufacturing method

This application claims the priority of the Chinese patent application filed on January 2, 2020 with the application number 202010007896.1 and the invention title "Trench-gate MOSFET power semiconductor device and its polysilicon filling method and manufacturing method", and the entire content of it is approved The reference is incorporated in this application.

Technical field

The invention relates to the technical field of power semiconductor device manufacturing, in particular to a trench gate MOSFET power semiconductor device with high withstand voltage and a polysilicon filling method and manufacturing method thereof.

Background technique

A schematic structural diagram of a power semiconductor device in the prior art is shown in FIG. 1. As an example, the power semiconductor device is a trench gate MOSFET power semiconductor device.

As shown in FIG. 1, a trench gate MOSFET power semiconductor device 100 includes a plurality of trenches 120 in an epitaxial layer 102 on a semiconductor substrate 101.

2a to 2h respectively show cross-sectional views of the manufacturing method of the power semiconductor device shown in FIG. 1 at different stages.

As shown in FIG. 2a, a trench 120 with a depth h1 is formed in the epitaxial layer 102 on the semiconductor substrate 101.

For trench gate MOSFET power semiconductor devices of different withstand voltage levels, the depth of the trench 120 is different. Generally, the higher the withstand voltage, the deeper the depth of the trench 120. For example, for a device with a withstand voltage above 120V, the depth of the trench 120 is generally above 5 microns.

As shown in FIG. 2b, an insulating layer 121 is formed on the surface of the epitaxial layer 102 and the trench.

The insulating layer 121 is composed of, for example, oxide. The process for forming the insulating layer 121 includes thermal oxidation or chemical vapor deposition CVD, or a combination of the two processes.

The insulating layer 121 serves as an isolation layer between the shielding conductor and the epitaxial layer in the power semiconductor device. The insulating layer 121 covers the sidewalls and bottom of the trench 120 and extends above the surface of the epitaxial layer 102. The cavity 151 is formed after the insulating layer 121 is filled in the trench 120.

For trench gate power semiconductor devices of different withstand voltage levels, the thickness of the insulating layer 121 is different. Generally, the higher the withstand voltage, the thicker the thickness of the insulating layer 121. For example, for a device with a withstand voltage of 120V or more, the thickness of the insulating layer 121 is 0.6 micrometer or more.

As shown in FIG. 2c, a shielding conductor 122 is deposited on the surface of the epitaxial layer 102 and the insulating layer 121 in the trench.

The shield conductor 122 is not only formed in the trench 120 to fill the cavity 151 but also extends over the surface of the epitaxial layer 102. In an ideal power semiconductor device, the shielding conductor 122 should be densely filled in the cavity 151 without defects such as voids or gaps.

For devices with a withstand voltage of 120V or less, the depth of the trench 120 is, for example, less than 5 μm, and the thickness of the insulating layer 121 is, for example, less than 0.6 μm. Due to the shallow trench depth and the thin insulating layer thickness, without affecting the parameters and performance, the opening of the trench 120 can be chamfered to enlarge the opening width of the cavity after the insulating layer is formed, thereby facilitating the shielding of the conductor 122 Of filling.

For devices with a withstand voltage of 120V or higher, the depth of the trench 120 is, for example, greater than 5 μm, and the thickness of the insulating layer 121 is, for example, greater than 0.6 μm. Due to the deep trench depth and the thicker insulating layer thickness, even if the opening of the trench 120 is chamfered to enlarge the opening width of the cavity after the insulating layer is formed, defects such as voids or gaps in the shielding conductor 122 will still be caused.

2d to 2h show the gate dielectric 125, the gate conductor 106, the body region 107, the source region 108, the interlayer dielectric layer 110, the contact regions 111 to 113, and the conductive channel 131 in the power semiconductor device shown in FIG. The formation process of the source electrode 141, the gate electrode 142, the shield electrode 143, and the drain electrode 144 to 133, since this part of the content is a conventional process, it will not be repeated here.

3a and 3b respectively show a cross-sectional view and a partial enlarged view of the power semiconductor device shown in FIG. 1 after the polysilicon layer is formed, which show the voids or gaps in the polysilicon layer, and an insulating layer 121 is formed in the trench 120 to insulate The opening width a of the cavity surrounded by the layer 121 is smaller than the inner width b of the cavity. The reason for this phenomenon is that when the thermal oxidation scheme is adopted, the oxidation growth rate at the interface close to the epitaxial layer is slightly higher, and the thickness will be thicker. When the chemical vapor deposition CVD scheme is adopted, the deposited oxide layer at the notch of the trench will also be thicker. For the trench after the oxide layer is deposited, the opening width of the cavity is smaller than the width of the cavity. In the subsequent shielding conductor deposition and filling process, due to the shielding conductor chemical vapor deposition CVD Shape retention. When the shielding conductor 122 is further filled, even when the cavity is not filled, the shielding conductor 122 will close the cavity opening, resulting in defects such as voids or gaps 153 in the shielding conductor 122, which will eventually lead to In the power semiconductor device 100, leakage and withstand voltage are reduced, and reliability is deteriorated.

The voids or gap defects in the shielded conductor cause breakdowns or short circuits in the power semiconductor device, which adversely affects the yield, reliability, and life of the power semiconductor device.

Summary of the invention

In view of the above problems, the purpose of the present invention is to provide a trench gate MOSFET power semiconductor device and its polysilicon filling method and manufacturing method, by etching back the i-th polysilicon layer with voids or gaps in the trench, and then using the i-th polysilicon layer The +1 polysilicon layer fills the voids or gaps to form a shielded conductor, which solves the problem of defects such as voids or gaps in the shielded conductor of the trench in the trench gate MOSFET power device.

According to one aspect of the present invention, there is provided a polysilicon filling method for trench gate MOSFET power semiconductor devices, which is characterized in that it comprises: a) forming an epitaxial layer on a semiconductor substrate, and forming a trench in the epitaxial layer B) forming an insulating layer on the surface of the epitaxial layer and in the trench, the insulating layer surrounds the trench to form a cavity; c) forming an i-th polysilicon layer on the surface of the epitaxial layer and in the cavity, the The i-th polysilicon layer fills the cavity, i=1; d) the i-th polysilicon layer is etched back, and a part of the i-th polysilicon layer is removed to expose the voids or gaps inside the i-th polysilicon layer E) forming an i+1th polysilicon layer on the exposed cavity or gap inside the i-th polysilicon layer, and the i+1th polysilicon layer fills the cavity or gap inside the i-th polysilicon layer; f) removing The (i+1)th polysilicon layer located above the surface of the epitaxial layer and the insulating layer located above the surface of the epitaxial layer.

Preferably, it further includes: after step e) and before step f), set i=i+1, and repeat steps d) to e) at least once.

Preferably, it further includes: after step e) and before step f), judging whether the void or gap of the i+1th polysilicon layer is filled, wherein if the void or gap of the i+1th polysilicon layer is If it is not filled, set i=i+1, and repeat steps d) to e) at least once.

Preferably, the first polysilicon layer to the (i+1)th polysilicon layer form a shielding conductor.

Preferably, the width of the groove is 1 to 5 microns, and the depth of the groove is 5 to 12 microns.

Preferably, the width of the groove is 1 to 3 microns, and the depth of the groove is 7 to 12 microns.

Preferably, the thickness of the insulating layer is 0.1 to 2 microns.

Preferably, the thickness of the insulating layer is 0.6 to 1.5 microns.

Preferably, the thickness of the insulating layer formed in step b) at the opening of the trench is greater than the thickness of the insulating layer inside the trench.

Preferably, the width between the sidewalls of the insulating layer at the opening of the trench formed in the step b) is smaller than the maximum width between the sidewalls of the insulating layer inside the trench.

Preferably, the maximum width between the sidewalls of the insulating layer inside the trench minus the width between the sidewalls of the insulating layer at the opening of the trench is greater than or equal to 30 nanometers.

Preferably, the opening width of the cavity formed in step b) is smaller than the inner width of the cavity.

Preferably, the value of the internal width of the cavity formed in step b) minus the opening width of the cavity is greater than or equal to 30 nanometers.

Preferably, the etch-back of the i-th polysilicon layer adopts dry etching or wet etching.

Preferably, the etching depth for etching back the i-th polysilicon layer is determined by the position of the cavity or the gap defect, and the etching depth ranges from 0.5 to 11 microns.

Preferably, in step d), the i-th polysilicon layer is etched back to expose the voids or gaps in the i-th polysilicon layer while exposing the insulating layer on the surface of the epitaxial layer and part of the insulating layer in the trench.

Preferably, in step e), while filling the i+1th polysilicon layer on the cavities or gaps in the exposed i-th polysilicon layer, while exposing the insulating layer on the surface of the epitaxial layer and part of the insulating layer in the trench Fill the i+1th polysilicon layer.

Preferably, in step d), the i-th polysilicon layer is etched back, and the remaining i-th polysilicon layer after the etch-back is in the shape of an opening, and the remaining i-th polysilicon layer gradually decreases from the top of the opening downwards.

Preferably, the (i+1)th polysilicon layer filled in step e) covers the remaining i-th polysilicon layer after the etch-back and the voids or gaps surrounded by the remaining i-th polysilicon layer after the etch-back.

Preferably, the distance between the cavity or gap generated by the filled (i+1)th polysilicon layer and the opening of the cavity is smaller than the distance between the cavity or gap generated by the (i+1)th polysilicon layer and the opening of the cavity.

According to another aspect of the present invention, there is provided a method for manufacturing a trench gate MOSFET power semiconductor device, including: a) forming an epitaxial layer on a semiconductor substrate, and forming a trench in the epitaxial layer; b) forming a trench in the epitaxial layer; An insulating layer is formed on the surface of the epitaxial layer and in the trench, and the insulating layer surrounds the trench to form a cavity; c) an i-th polysilicon layer is formed on the surface of the epitaxial layer and in the cavity, and the i-th polysilicon layer is filled with The cavity, i=1; d) etch back the i-th polysilicon layer, and remove a part of the i-th polysilicon layer to expose the voids or gaps inside the i-th polysilicon layer; e) after exposing The i+1th polysilicon layer is formed on the cavity or gap inside the i-th polysilicon layer, and the i+1th polysilicon layer fills the cavity or gap inside the i-th polysilicon layer; f) removing the epitaxial layer The i+1th polysilicon layer above the surface and the insulating layer above the epitaxial layer surface, the first polysilicon layer to the i+1th polysilicon layer form a shielding conductor; g) The insulating layer in the trench is etched back to form an upper cavity, thereby exposing the upper side wall of the trench and the shield conductor; h) on the upper side wall of the trench and the shield conductor Forming a gate dielectric; i) forming a gate conductor between the gate dielectrics; j) forming a body region of the second doping type in the region where the epitaxial layer is adjacent to the trench, and the semiconductor liner The bottom is a first doping type and serves as a drain region, the epitaxial layer is a first doping type, and the second doping type is opposite to the first doping type; k) forming all the layers in the body region The source region of the first doping type; and 1) forming an electrical connection structure of the gate conductor, the shield conductor, the source region, and the drain region.

Preferably, the thickness of the insulating layer is 0.1 to 2 microns.

Preferably, the thickness of the insulating layer is 0.6 to 1.5 microns.

Preferably, the thickness of the insulating layer at the opening of the trench is greater than the thickness of the insulating layer inside the trench.

Preferably, the width between the sidewalls of the insulating layer at the opening of the trench is smaller than the maximum width between the sidewalls of the insulating layer inside the trench.

Preferably, the opening width of the cavity is smaller than the inner width of the cavity.

Preferably, the value of the internal width of the cavity minus the opening width of the cavity is greater than or equal to 30 nanometers.

Preferably, the withstand voltage of the trench gate MOSFET power semiconductor device is 120V to 300V.

Preferably, in step e), while filling the i+1th polysilicon layer on the cavities or gaps in the exposed i-th polysilicon layer, the insulating layer exposing the epitaxial layer and the part of the insulating layer in the trench are filled at the same time The i+1th polysilicon layer.

Preferably, in step d), the i-th polysilicon layer is etched back for the i-th time, and the remaining i-th polysilicon layer after the etch-back is in the shape of an opening, and the remaining i-th polysilicon layer gradually decreases from the top of the opening downward.

Preferably, the depth of the body region is not less than the depth of the gate dielectric and the gate conductor.

According to another aspect of the present invention, there is provided a trench gate MOSFET power semiconductor device, which is formed by the above-mentioned manufacturing method, and includes: a semiconductor substrate, the semiconductor substrate serving as a drain region; An epitaxial layer; a trench located in the epitaxial layer; an insulating layer located in the trench, the insulating layer surrounding the cavity formed by the trench; and a shield conductor formed by filling the cavity with polysilicon; The gate dielectric and the gate conductor located on the upper part of the insulating layer in the trench, the gate dielectric is located on the upper sidewalls of the trench and the shield conductor, and the gate conductor is located on the gate dielectric Between; the body region and the source region in the region where the epitaxial layer is adjacent to the trench, the doping types of the body region and the source region are opposite; and the gate conductor, the shielding conductor, the The electrical connection structure of the source region and the drain region.

Preferably, the thickness of the insulating layer is 0.1 to 2 microns.

Preferably, the thickness of the insulating layer is 0.6 to 1.5 microns.

Preferably, the electrical connection structure includes a plurality of electrodes respectively connected to the gate conductor, the shield conductor, the source region and the drain region.

Preferably, the electrical connection structure further includes a plurality of conductive channels, the gate conductor, the shielding conductor, and the source region are connected to the corresponding electrodes via the corresponding conductive channels, and the drain region is in contact with the corresponding electrodes.

According to the manufacturing method of the trench gate MOSFET power semiconductor device of the embodiment of the present invention, the i-th polysilicon layer with a cavity or gap in the trench is etched back, and then the i+1-th polysilicon layer is used to fill the cavity or gap, thereby forming a shield The conductor method solves the problem that the trench gate MOSFET power semiconductor device has a high withstand voltage, a deeper trench depth, a narrow trench width, and a thick insulating layer. When the device is making a shielded conductor, the trench width is narrow due to the narrow trench width. After being covered by a thicker insulating layer, the formed cavity is small, which ultimately leads to the problem of voids or gap defects in the shielded conductor.

In a preferred embodiment, the i-th polysilicon layer (i is a positive integer greater than or equal to 1) is etched back, and the remaining i-th polysilicon layer after the etch-back is formed into an opening, and the remaining i-th polysilicon layer gradually moves downward from the opening Reduce to expose the voids or gaps in the i-th polysilicon layer, and then fill the i+1-th polysilicon layer with the holes or gaps in the i-th polysilicon layer after the etch-back; the filled i+1-th polysilicon layer fills the i-th polysilicon layer The voids or gaps in the polysilicon layer, so the voids or gaps in the i-th polysilicon layer are eliminated. If the filled i+1th polysilicon layer has no voids or gap defects, a dense shielding conductor is formed, such as the filled i+1th polysilicon layer There are still voids or gaps, repeat the etch back to the i+1th polysilicon layer and fill the i+1th polysilicon layer after the etchback to eliminate the voids or gaps in the i+1th polysilicon layer, the i+1th polysilicon layer The voids or gaps formed by the layer have moved up to the device notch direction compared to the voids or gaps of the i-th polysilicon layer. Repeat the above steps until the shielding conductor voids or gap defects are eliminated or the voids or gaps in the shielding conductor reach the stated power The acceptable range of semiconductor devices.

By adopting the technology of the present invention, defects such as voids or gaps in the device shielding conductor can be reduced, thereby improving the yield, reliability and life span of the power semiconductor device. The present invention can be applied to trench gate MOSFET power devices with a withstand voltage of 120V or less, the width of the trench is 1 to 5 microns, the depth of the trench is 5 to 12 microns, and the thickness of the insulating layer is 0.1 to 2 microns. It is suitable for trench gate MOSFET power devices with a withstand voltage of 120V or more, such as 120V to 300V, the width of the trench is 1 to 3 microns, the depth of the trench is 7 to 12 microns, and the thickness of the insulating layer is 0.6 to 1.5 microns.

Description of the drawings

Through the following description of the embodiments of the present invention with reference to the accompanying drawings, the above and other objectives, features and advantages of the present invention will be clearer. In the accompanying drawings:

Fig. 1 shows a schematic structural diagram of a power semiconductor device according to the prior art.

3a and 3b respectively show a cross-sectional view and a partial enlarged view of the power semiconductor device shown in FIG. 1 after a polysilicon layer is formed, which show voids or gaps in the polysilicon layer.

FIG. 4 shows a flowchart of a method of manufacturing a power semiconductor device according to the first embodiment of the present invention.

5a to 5l respectively show cross-sectional views at different stages of the manufacturing method of the power semiconductor device according to the first embodiment of the present invention.

6a and 6b respectively show a cross-sectional view and a partially enlarged view of a power semiconductor device according to a second embodiment of the present invention after a shielded conductor is formed.

Detailed ways

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are denoted by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of brevity, the semiconductor structure obtained after several steps can be described in one figure.

It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "above" another layer or another region, it can mean directly on the other layer or another region, or It also includes other layers or regions between it and another layer or another region. Moreover, if the device is turned over, the layer or area will be "below" or "below" the other layer or area.

In order to describe the situation of being directly on another layer and another area, this article will adopt the expression "A directly on B" or "A on and adjacent to B". In this application, "A is directly located in B" means that A is located in B, and A and B are adjacent to each other, instead of A being located in the doped region formed in B.

In the present application, the term "semiconductor structure" refers to a general term for the entire semiconductor structure formed in each step of manufacturing a semiconductor device, including all layers or regions that have been formed.

In the following, many specific details of the present invention are described, such as the structure, material, size, processing technology and technology of the device, in order to understand the present invention more clearly. However, as those skilled in the art can understand, the present invention may not be implemented according to these specific details.

Unless otherwise specified in the following, each part of the semiconductor device may be composed of materials known to those skilled in the art. The semiconductor material includes, for example, III-V semiconductors such as GaAs, InP, GaN, and SiC, and IV semiconductors such as Si and Ge.

3a and 3b respectively show a cross-sectional view and a partial enlarged view of the power semiconductor device shown in FIG. 1 after the polysilicon layer is formed, which show the voids or gaps in the polysilicon layer.

In the above method of forming the power semiconductor device 100, the epitaxial layer 102 is formed on the semiconductor substrate 101, the trench 120 is formed in the epitaxial layer 102, the insulating layer 121 is formed in the trench 120, and the cavity 151 surrounded by the insulating layer 121 is formed. , And the cavity 151 is filled with a polysilicon layer 122. The opening width of the cavity 151 surrounded by the insulating layer 121 formed in the trench 120 is smaller than the inner width. This is caused by the uneven thickness of the insulating layer 121 on the sidewall of the trench 120.

When the thermal oxidation scheme is adopted, the oxidation growth rate at the interface close to the surface of the epitaxial layer 102 is slightly higher, and the thickness of the insulating layer 121 at the opening of the trench 120 is greater than the thickness inside the trench 120. When polycrystalline is deposited by chemical vapor deposition, the deposition rate near the surface of the epitaxial layer 102 is slightly higher, and the thickness of the insulating layer 121 at the opening of the trench 120 is still greater than the thickness inside the trench 120.

For the case where the opening width of the cavity surrounded by the insulating layer 121 is smaller than the inner width of the cavity, if chemical vapor deposition is used to form the polysilicon layer 122, the conformality of the polycrystal easily causes defects of voids or gaps 152 in the polysilicon layer.

For a device with a withstand voltage of 120V or less, the depth of the trench 120 is, for example, less than 5 μm, and the thickness of the insulating layer 121 is, for example, less than 0.6 μm. Due to the shallow trench depth and the thin insulating layer thickness, without affecting the parameters and performance, the opening of the trench 120 can be chamfered to enlarge the cavity opening width after the insulating layer is formed, which is beneficial to the polysilicon layer 122 Of filling.

For devices with a withstand voltage of 120V or higher, the depth of the trench 120 is, for example, greater than 5 μm, and the thickness of the insulating layer 121 is, for example, greater than 0.6 μm. Due to the deep trench depth and the thick insulating layer, even if the opening of the trench 120 is chamfered to enlarge the opening width of the cavity after the insulating layer is formed, defects such as voids or gaps in the polysilicon layer 122 will still be caused.

As shown in FIGS. 3a and 3b, an insulating layer 121 is formed in the trench 120, and the opening width a of the cavity surrounded by the insulating layer 121 is smaller than the inner width b of the cavity. When the polysilicon layer 122 is further formed, even when the cavity is not filled, the polysilicon layer 122 will close the cavity opening, so that the material of the polysilicon layer 122 cannot continue to enter the cavity, thereby appearing in the polysilicon layer 122 Defects such as voids or gaps 152 may cause leakage, reduced withstand voltage, and poor reliability in the final power semiconductor device 100.

The defects in the polysilicon layer cause breakdowns or short circuits in the power semiconductor device, which adversely affects the yield, reliability, and life of the power semiconductor device.

In step S01, a trench 220 with a width w1 and a depth h3 is formed in the epitaxial layer 202 on the semiconductor substrate 201, as shown in FIG. 5a.

The semiconductor substrate 201 also serves as the drain region of the final device. The material is, for example, a single crystal silicon substrate doped into an N-type. An epitaxial layer 202 is also formed on the semiconductor substrate 201, and the trench 220 is located in the epitaxial layer 202. The process for forming the trench 220 is, for example, a patterning process including photolithography and etching. For example, a resist mask including an opening pattern of the trench 220 is formed by photolithography, and a portion of the epitaxial layer 202 exposed through the opening is selectively removed by etching.

For trench gate power semiconductor devices of different withstand voltage levels, the depth of the trench 220 is different. Generally, the higher the withstand voltage, the deeper the depth of the trench 220. For example, for a device with a withstand voltage above 120V, the depth of the trench 220 is generally above 5 microns. In this embodiment, the width w1 of the trench 220 is, for example, 1 to 5 microns, and the depth is, for example, 5 to 12 microns, or the width w1 of the trench 220 is, for example, 1 to 3 microns, and the depth is, for example, 7 to 12 microns.

In step S02, an insulating layer 221 is formed on the surface of the epitaxial layer 202 and the trench 220, as shown in FIG. 5b.

The insulating layer 221 is composed of, for example, oxide. The process for forming this insulating layer 221 includes thermal oxidation or chemical vapor deposition CVD, or a combination of the two processes. Thermal oxidation includes hydrothermal oxidation HTO or selective reactive oxidation (SRO). Chemical vapor deposition CVD includes low pressure chemical vapor deposition LPCVD or sub-atmospheric chemical vapor deposition SACVD.

The insulating layer 221 serves as an isolation layer between the shielding conductor and the epitaxial layer 202 in the power semiconductor device. The insulating layer 221 covers the sidewalls and bottom of the trench 220 and extends above the surface of the epitaxial layer 202, and forms a cavity 251 after filling the insulating layer 221 inside the trench 220.

For trench gate power semiconductor devices of different withstand voltage levels, the thickness of the insulating layer 221 is different. Generally, the higher the withstand voltage, the thicker the thickness of the insulating layer 221 is. For example, for a device with a withstand voltage of 120V or more, the thickness of the insulating layer 221 needs to be 0.6 micrometers or more. In this embodiment, the thickness t1 of the insulating layer 221 is 0.1 to 2 microns, and the thickness t1 of the insulating layer 221 can also be 0.6 to 1.5 microns. The opening width w2 of the cavity 251 surrounded by the insulating layer 221 is smaller than the inner width w3, that is, w2<w3.

If the value of the inner width w3 of the cavity 251 surrounded by the insulating layer 221 minus the opening width w2 of the cavity 251 is greater than or equal to 30 nanometers, defects such as voids or gaps are likely to occur in the subsequent shielding conductor.

The present invention is adapted to the situation that the opening width w2 of the cavity 251 surrounded by the insulating layer 221 is smaller than the inner width w3 to reach a predetermined difference, but there is no restriction on the shape of the cavity 251. For example, the shape of the cavity 251 is a shape with a small opening and a bottom width and a large middle width, or a shape with a small opening width and a large middle and bottom width. The cavity 251 may have any shape, and may even be an irregular shape.

In step S03 to step S05, an i-th polysilicon layer and an i+1-th polysilicon layer are formed in the cavity 251 surrounded by the insulating layer 221, as shown in FIGS. 5c to 5e.

The shielding conductor is composed of, for example, multiple in-situ doped polysilicon layers, the deposition temperature is, for example, 500 to 580 degrees, the sheet resistance is 3 to 20 ohms, and the thickness is 50 to 2000 nanometers.

The multiple sub-steps of step S03 will be described in detail below with reference to FIGS. 5c to 5e.

In step S03, an i-th polysilicon layer 222 is formed on the surface of the epitaxial layer 202 and the insulating layer 221 in the trench, as shown in FIG. 5c. In this embodiment, i=1, that is, the first polysilicon layer 222 is formed.

In this sub-step, the first polysilicon layer 222 fills the cavity 251 surrounded by the insulating layer 221 and extends over the surface of the epitaxial layer 202.

In an ideal power semiconductor device, the first polysilicon layer 222 should be densely filled in the trench 220 without defects such as voids or gaps.

For devices with a withstand voltage of 120V or less, the depth of the trench 220 is, for example, less than 5 μm, and the thickness of the insulating layer 221 is, for example, less than 0.6 μm. Due to the shallow trench depth and the thinner insulating layer thickness, without affecting the parameters and performance, the opening of the trench 220 can be chamfered to expand the cavity opening width after the insulating layer is formed, which is beneficial to the first Filling of the crystalline silicon layer 222.

For devices with a withstand voltage of 120V to 300V, the depth of the trench 220 is, for example, greater than 5 microns, and the thickness of the insulating layer 221 is, for example, greater than 0.6 microns. Due to the deep trench depth and the thick insulating layer, even if the opening of the trench 220 is chamfered to expand the opening width of the cavity after the insulating layer is formed, there will still be voids or gaps in the first polysilicon layer 222 And other defects.

Since the opening width w2 of the cavity 251 surrounded by the insulating layer 221 is smaller than the internal width w3 of the cavity 251, the reason for this phenomenon is that when the thermal oxidation scheme is adopted, the oxidation growth rate at the interface close to the epitaxial layer 202 is slightly higher, and the thickness will be thicker. some. When the chemical vapor deposition CVD scheme is adopted, the deposited oxide layer at the opening of the cavity 251 will also be thicker. For the trench topography of the cavity 251 after the oxide layer is deposited, the opening width is smaller than that in the cavity 251. In the subsequent polysilicon layer deposition and filling process, due to the conformability of the polysilicon layer chemical vapor deposition CVD When the first polysilicon layer 222 is further filled, even when the cavity 251 is not filled, the first polysilicon layer 222 will close the opening of the cavity 251, so that the first polysilicon layer 222 Defects such as voids or gaps 252 are present.

In step S04, as shown in FIG. 5d, for example, chemical mechanical planarization (CMP) is used to remove the portion of the i-th polysilicon layer 222 above the surface of the epitaxial layer 202, and for example, selective wet etching is used to perform The i-th polysilicon layer 222 is etched back to expose defects such as voids or gaps in the i-th polysilicon layer 222.

In this sub-step, the i-th polysilicon layer 222 is, for example, the first polysilicon layer, and the first polysilicon layer 222 with a certain depth h4 in the trench is removed until the remaining first polysilicon layer 222 in the trench is Defects such as voids or gaps have been removed or exposed to an opening shape, so that a cavity 253 surrounded by the remaining first polysilicon layer 222 and a part of the insulating layer 221 is formed in the trench 220. The etching depth of the first polysilicon layer 222 is mainly determined by the position of the defect, and h4 ranges from 2 to 11 microns. The opening-shaped voids or gaps surrounded by the remaining first polysilicon layer 222 gradually increase from the bottom of the trench to the top of the trench.

In step S05, as shown in FIG. 5e, an (i+1)th polysilicon layer 223 is formed on the surface of the epitaxial layer 202 and the cavity 253.

In this sub-step, the (i+1)th polysilicon layer is, for example, the second polysilicon layer, and the second polysilicon layer 223 fills the cavity 253 surrounded by the remaining first polysilicon layer 222 and part of the insulating layer 221, and The epitaxial layer 202 extends above the surface. The second polysilicon layer 223 fills the opening-shaped voids or gaps of the first polysilicon layer 222 in the trench 220. Since the opening width w2 of the cavity surrounded by the insulating layer 221 is smaller than the inner width w3 of the cavity, even when the cavity 253 is not filled, the second polysilicon layer 223 will close the cavity opening. Defects such as new closed voids or gaps 254 appear in the second polysilicon layer 223.

In step S06, it is determined whether the void or gap of the i+1th polysilicon layer is filled, if not, step S08 is executed and then step S04 is returned, and if it is filled, step S07 is executed.

In step S07, the voids or gaps in the shielding conductor formed by the multi-layer polysilicon layer are filled, and other parts of the device are continued to be formed.

In step S08, let i=i+1, that is, the i-th polysilicon layer is specifically the second polysilicon layer, and the above steps S04 to S06 are repeated.

Specifically, as shown in FIG. 5f, for example, chemical mechanical planarization (CMP) is used to remove the part of the second polysilicon layer 223 above the surface of the epitaxial layer 202, and for example, selective wet etching is used to The second polysilicon layer 223 is etched back to expose the voids or gaps 254 defects.

In this sub-step, the second polysilicon layer 223 with a certain depth h5 in the trench is removed until defects such as cavities or gaps in the remaining second polysilicon layer 223 in the trench have been removed or exposed to an opening. Thus, a cavity 255 surrounded by the remaining second polysilicon layer 223 and part of the insulating layer 221 is formed in the trench 220. The etching depth of the second polysilicon layer 223 is mainly determined by the position of the defect, and h5 ranges from 0.5 to 10 microns. Preferably, the opening-shaped cavity or gap of the second polysilicon layer 223 gradually increases from the bottom of the trench to the top of the trench.

As shown in FIG. 5g, a third polysilicon layer 224 is formed on the surface of the epitaxial layer 202 and in the trench.

In this sub-step, the third polysilicon layer 224 fills the cavity 255 surrounded by the remaining second polysilicon layer 223 and part of the insulating layer 221, and extends over the surface of the epitaxial layer 202. The third polysilicon layer 224 fills the opening-shaped voids or gaps of the second polysilicon layer 223 in the trench 220. Further, since the opening-shaped cavity or gap of the second polysilicon layer 223 is close to the opening of the cavity surrounded by the insulating layer 221, the width of the opening of the cavity 255 surrounded by the insulating layer 221 is the same as the inside of the cavity 255 surrounded by the insulating layer 221 The width is approximately the same. Therefore, the third polysilicon layer 224 closes the opening after filling the cavity 255. Therefore, there are no defects such as closed voids or gaps in the third polysilicon layer 224.

In the above multiple sub-steps from step S03 to step S08, the third polysilicon layer 224, the second polysilicon layer 223, and the first polysilicon layer 222 are connected to each other to form a shielding conductor without defects such as voids or gaps. Taking the third polysilicon deposition to form a shielding conductor without defects such as voids or gaps as an example, the third polysilicon layer 224, the second polysilicon layer 223, and the first polysilicon layer 222 form an integral shielding conductor.

If defects such as voids or gaps still occur in the polysilicon layers 222 to 224, then additional etch-back and deposition sub-steps of the polysilicon layer can be continued to remove the defects, that is, the deposition of a total of i+1 polysilicon layers and the previous i The filled polysilicon is etched back, where i is a natural number. In the etch-back of the i-th polysilicon layer on the lower level, all the cavities or gaps in the i-th polysilicon layer on the lower level are exposed, and the i+1th polysilicon layer on the upper level is used to fill the cavities or gaps, thereby eliminating the cavities or gaps on the lower level. The voids or gaps in the i-th polysilicon layer until there are no defects such as voids or gaps in all the polysilicon layers. Under normal circumstances, when i=1 to 4, it can solve the problem of filling defects such as voids or gaps in the shielding conductor when the opening width of the trench 220 after the insulating layer is formed in the power semiconductor device is smaller than the internal width. The problem is that if the position of the cavity or the gap is in the upper part of the trench 220, or when the cavity or gap is small, only i=1 is required, a total of 2 polysilicon layers are deposited and the first filled polysilicon layer is etched back.

In and after step S07, other steps of forming a power semiconductor device are also included. Further, for example, chemical mechanical planarization (CMP) is used to remove the part of the third polysilicon layer 224 and the insulating layer 221 above the surface of the epitaxial layer 202, as shown in FIG. 5h.

In this step, the part of the third polysilicon layer 224 and the insulating layer 221 in the trench 220 remains, and the top end is flush with the surface of the epitaxial layer 202.

Further, for example, selective wet etching is used to etch back the insulating layer 221 in the trench 220 to form an upper cavity, as shown in FIG. 5i.

In this step, the portion of the insulating layer 221 located in the upper part of the trench 220 is removed, that is, the etching depth h6 shown in the figure, and the upper cavity 256 is formed. The upper sidewall of the trench 220 and the upper sidewall of the shield conductor are exposed in the upper cavity 256. The etching depth h6 of the insulating layer 221 ranges from 0.4 to 2 microns according to product threshold and capacitance requirements.

Further, a gate dielectric 225 and a gate conductor 206 are formed in the upper cavity 256 of the trench 220, as shown in FIG. 5j.

In this step, an oxide layer is grown on the surface of the epitaxial layer 202, the upper sidewall of the trench 220, and the upper sidewall of the shielding conductor, for example, using thermal oxidation to form the gate dielectric 225. Next, the gate conductor 206 is deposited. The gate conductor 206 not only fills the upper cavity 256 of the trench 220 but also extends over the surface of the epitaxial layer 202. For example, chemical mechanical planarization is used to remove the part of the gate conductor 206 and the gate dielectric 225 above the surface of the epitaxial layer 202, so that the surface of the epitaxial layer 202 is exposed again, and the top of the gate conductor 206 and the gate dielectric 225 are connected to the epitaxial layer 202. The surface of layer 202 is flush.

Further, a P-type body region 207 is formed in the epitaxial layer 202, and an N-type source region 208 is formed in the body region 207, as shown in FIG. 5k.

The process for forming the body region 207 and the source region 208 is, for example, multiple ion implantation. Different types of doped regions are formed by selecting appropriate dopants, and then thermal annealing is performed to activate the impurities. In ion implantation, the shield conductor and the gate conductor 206 are used as hard masks, and the lateral positions of the body region 207 and the source region 208 can be defined, so that the photoresist mask can be omitted.

Further, an electrical connection structure of the gate conductor 206, the shielding conductor, the source region 208 and the drain region is formed, thereby forming a power semiconductor device 200, as shown in FIG. 51.

In this step, a contact region 211 adjacent to the source region 208 is formed, a contact region 212 is formed in the gate conductor 206, and a contact region 213 is formed in the shield conductor. The interlayer dielectric layer 210 is located on the surface of the epitaxial layer 202. Further, conductive channels 231 to 233 penetrating through the interlayer dielectric layer 210 are formed. The conductive channel 231 extends downward through the source region 208 to reach the contact region 211, the conductive channel 232 extends downward into the gate conductor 206 to reach the contact region 212, and the conductive channel 233 extends downward into the shield conductor to reach the contact region 213. Further, a source electrode 241, a gate electrode 242, and a shield electrode 243 are respectively formed on the surface of the interlayer dielectric layer 210 at positions corresponding to the conductive channels 231 to 233, so as to provide access to the source region 208, the gate conductor 206, and the shield conductor respectively. The electrical connection path to complete the front structure of the power semiconductor device 200.

After the front structure of the power semiconductor device 200 is completed, a drain 244 contacting the drain region needs to be formed on the back of the power semiconductor device 200. Since the semiconductor substrate 201 serves as the drain region, the drain 244 is in direct contact with the semiconductor substrate 201 , No need for conductive channels.

The complete structure of the power semiconductor device is completed through a series of subsequent processes such as thinning the back surface, forming the source electrode 241, the gate electrode 242, the shield electrode 243 and the drain electrode 244 on the front and the back respectively, and dicing.

In the power semiconductor device 200 according to the embodiment of the present invention, at least a part of the body region 207 is adjacent to the upper portion of the trench 220. The first part of the gate dielectric 225 is located on the upper sidewall of the trench 220, the second part is located between the gate conductor 206 and the shielding conductor, the insulating layer 221 is located on the lower sidewall of the trench 220, and the second part of the gate dielectric 225 A part is adjacent to the insulating layer 221. The gate conductor 206 is located in the upper part of the trench 220 and is separated from the body region 207 in the epitaxial layer 202 by the gate dielectric 225. The shielding conductor includes a plurality of polysilicon layers 222 to 224, extending from the upper part to the lower part of the trench 220, and is separated from the gate conductor 206 by the second part of the gate dielectric 125, and is insulated from the epitaxial layer 202. The layers 221 are separated from each other.

As shown in FIGS. 6a and 6b, an insulating layer 221 is formed in the trench 220, and the opening width a of the cavity surrounded by the insulating layer 221 is smaller than the inner width b of the cavity. When the polysilicon layers 222 to 224 are successively formed by further forming multiple etchbacks, etchback is used to expose defects such as voids or gaps in the previous polysilicon layer, and then the latter polysilicon layer is used to fill the voids or gaps to remove the defects, thereby forming The shielded conductor without defects such as voids or gaps prevents leakage, improves withstand voltage, and improves reliability in the final power semiconductor device 200. Elimination of voids or gap defects in the shielded conductor to prevent breakdowns or short circuits of power semiconductor devices, so that the yield, reliability and life of the power semiconductor devices are significantly improved.

In the above-mentioned embodiment, it is described that the shield conductor of the split-gate power semiconductor device is formed of a plurality of polysilicon layers. However, the present invention is not limited to this, but can be applied to any type of trench-type power semiconductor device. For example, in a trench-type power semiconductor device, multiple polysilicon layers and insulating layers form gate conductors and gate dielectrics, respectively. After forming multiple polysilicon layers, it further includes: forming a second layer in the region where the epitaxial layer is adjacent to the trench. A body region of two doping types; forming a source region of the first doping type in the body region, and the second doping type is opposite to the first doping type; and forming an electrical connection structure between the gate conductor and the source region. The gate conductor extends from the upper part of the trench to the lower part of the trench, and is separated from the body region by a gate dielectric.

In the above-mentioned embodiment, it is described that the shield conductor in the power semiconductor device is composed of a plurality of doped polysilicon layers. However, the present invention is not limited to this, but can be applied to trench-type power semiconductor devices that use any conductor as a gate conductor or shield conductor, where the thickness of the insulating layer on the sidewall of the trench is uneven, resulting in The opening width of the cavity surrounded by the insulating layer is smaller than the inner width.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply one of these entities or operations. There is any such actual relationship or order between. Moreover, the terms "include", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes those that are not explicitly listed Other elements of, or also include elements inherent to this process, method, article or equipment. If there are no more restrictions, the element defined by the sentence "including a..." does not exclude the existence of other identical elements in the process, method, article, or equipment that includes the element.

According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the present invention to only specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and make modifications based on the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

A polysilicon filling method for trench gate MOSFET power semiconductor devices, which is characterized in that it comprises:

a) forming an epitaxial layer on the semiconductor substrate, and forming a trench in the epitaxial layer;

b) An insulating layer is formed on the surface of the epitaxial layer and in the trench, and the insulating layer surrounds the trench to form a cavity;

c) forming an i-th polysilicon layer on the surface of the epitaxial layer and the cavity, and the i-th polysilicon layer fills the cavity, i=1;

d) performing an etch back on the i-th polysilicon layer to remove a part of the i-th polysilicon layer to expose the voids or gaps inside the i-th polysilicon layer;

e) forming an i+1th polysilicon layer on the exposed cavity or gap inside the i-th polysilicon layer, and the i+1th polysilicon layer fills the cavity or gap inside the i-th polysilicon layer;

f) removing the (i+1)th polysilicon layer located above the surface of the epitaxial layer and the insulating layer located above the surface of the epitaxial layer.
The polysilicon filling method according to claim 1, further comprising:

After performing step e) and before step f), set i=i+1, and repeat steps d) to e) at least once.
The polysilicon filling method according to claim 1, further comprising:

After performing step e) and before step f), determine whether the void or gap of the i+1th polysilicon layer is filled,

Wherein, if the void or gap of the i+1th polysilicon layer is not filled, set i=i+1, and repeat steps d) to e) at least once.
The polysilicon filling method according to any one of claims 1 to 3, wherein the first polysilicon layer to the (i+1)th polysilicon layer form a shield conductor.
The polysilicon filling method according to any one of claims 1 to 3, wherein the width of the trench is 1 to 5 microns, and the depth of the trench is 5 to 12 microns.
The polysilicon filling method according to any one of claims 1 to 3, wherein the width of the trench is 1 to 3 microns, and the depth of the trench is 7 to 12 microns.
The polysilicon filling method according to any one of claims 1 to 3, wherein the thickness of the insulating layer is 0.1 to 2 microns.
The polysilicon filling method according to any one of claims 1 to 3, wherein the thickness of the insulating layer is 0.6 to 1.5 microns.
The polysilicon filling method according to any one of claims 1 to 3, wherein the thickness of the insulating layer formed in step b) at the opening of the trench is greater than the thickness of the insulating layer inside the trench thickness.
The polysilicon filling method according to any one of claims 1 to 3, wherein the width between the sidewalls of the insulating layer at the opening of the trench formed in step b) is smaller than that of the insulating layer inside the trench. The maximum width between the sidewalls of the layer.
The polysilicon filling method according to any one of claims 1 to 3, wherein the maximum width between the sidewalls of the insulating layer inside the trench minus the sidewalls of the insulating layer at the opening of the trench The width of the space is greater than or equal to 30 nanometers.
The polysilicon filling method according to claim 1, wherein the opening width of the cavity formed in step b) is smaller than the inner width of the cavity.
12. The polysilicon filling method according to claim 12, wherein the value of the inner width of the cavity formed in step b) minus the opening width of the cavity is greater than or equal to 30 nanometers.
The polysilicon filling method according to any one of claims 1 to 3, wherein the etch-back of the i-th polysilicon layer is performed by dry etching or wet etching.
The polysilicon filling method according to any one of claims 1 to 3, wherein the etching depth of the ith polysilicon layer is etched back by the position of the cavity or the gap defect, and the etching depth ranges from 0.5 to 11. Micrometers.
The polysilicon filling method according to any one of claims 1 to 3, wherein in step d), the i-th polysilicon layer is etched back, exposing the cavities or gaps in the i-th polysilicon layer while exposing the epitaxial layer The insulating layer on the surface of the layer and part of the insulating layer in the trench.
The polysilicon filling method according to any one of claims 1 to 3, wherein, in step e), the i+1th polysilicon layer is filled in the cavities or gaps in the exposed i-th polysilicon layer while exposing the i+1th polysilicon layer. The insulating layer on the surface of the epitaxial layer and part of the insulating layer in the trench are filled with an i+1th polysilicon layer.
The polysilicon filling method according to any one of claims 1 to 3, wherein in step d), the i-th polysilicon layer is etched back, and the remaining i-th polysilicon layer after the etch-back is open, and the remaining i-th polysilicon layer is open. The polysilicon layer gradually decreases from the top of the opening downward.
The polysilicon filling method according to any one of claims 1 to 3, wherein the i+1th polysilicon layer filled in step e) covers the remaining i-th polysilicon layer after etching back and the remaining first polysilicon layer after etching back i A void or gap surrounded by a polysilicon layer.
The polysilicon filling method according to any one of claims 1 to 3, wherein the distance between the void or gap generated by the filled (i+1)th polysilicon layer and the opening of the cavity is smaller than the void or gap generated by the (i+1)th polysilicon layer. The distance between the gap and the opening of the cavity.
A manufacturing method of trench gate MOSFET power semiconductor device includes:

a) forming an epitaxial layer on the semiconductor substrate, and forming a trench in the epitaxial layer;

b) An insulating layer is formed on the surface of the epitaxial layer and in the trench, and the insulating layer surrounds the trench to form a cavity;

c) forming an i-th polysilicon layer on the surface of the epitaxial layer and the cavity, and the i-th polysilicon layer fills the cavity, i=1;

d) performing an etch back on the i-th polysilicon layer to remove a part of the i-th polysilicon layer to expose the voids or gaps inside the i-th polysilicon layer;

e) forming an i+1th polysilicon layer on the exposed cavity or gap inside the i-th polysilicon layer, and the i+1th polysilicon layer fills the cavity or gap inside the i-th polysilicon layer;

f) removing the i+1th polysilicon layer above the surface of the epitaxial layer and the insulating layer above the surface of the epitaxial layer, from the first polysilicon layer to the i+1th polysilicon layer Form a shielded conductor;

g) etching back the insulating layer in the trench to form an upper cavity, thereby exposing the upper sidewall of the trench and the shield conductor;

h) forming a gate dielectric on the upper sidewall of the trench and the shield conductor;

i) forming a gate conductor between the gate dielectrics;

j) A body region of the second doping type is formed in the region where the epitaxial layer is adjacent to the trench, the semiconductor substrate is of the first doping type and used as a drain region, and the epitaxial layer is of the first doping Type, the second doping type is opposite to the first doping type;

k) forming a source region of the first doping type in the body region; and

1) forming an electrical connection structure of the gate conductor, the shielding conductor, the source region and the drain region.
The manufacturing method according to claim 21, further comprising:

After performing step e) and before step f), set i=i+1, and repeat steps d) to e) at least once.
The manufacturing method according to claim 21, further comprising:

After performing step e) and before step f), determine whether the void or gap of the i+1th polysilicon layer is filled,

Wherein, if the void or gap of the i+1th polysilicon layer is not filled, set i=i+1, and repeat steps d) to e) at least once.
The manufacturing method according to any one of claims 21 to 23, wherein the width of the trench is 1 to 5 microns, and the depth of the trench is 5 to 12 microns.
The manufacturing method according to any one of claims 21 to 23, wherein the width of the trench is 1 to 3 microns, and the depth of the trench is 7 to 12 microns.
The manufacturing method according to any one of claims 21 to 23, wherein the thickness of the insulating layer is 0.1 to 2 microns.
The manufacturing method according to any one of claims 21 to 23, wherein the thickness of the insulating layer is 0.6 to 1.5 micrometers.
The manufacturing method according to any one of claims 21 to 23, wherein the thickness of the insulating layer at the opening of the trench is greater than the thickness of the insulating layer inside the trench.
The manufacturing method according to any one of claims 21 to 23, wherein the width between the sidewalls of the insulating layer at the opening of the trench is smaller than the maximum width between the sidewalls of the insulating layer inside the trench. width.
The manufacturing method according to any one of claims 21 to 23, wherein the maximum width between the sidewalls of the insulating layer inside the trench minus the gap between the sidewalls of the insulating layer at the opening of the trench The width is greater than or equal to 30 nanometers.
The manufacturing method according to any one of claims 21 to 23, wherein the opening width of the cavity is smaller than the inner width of the cavity.
The manufacturing method according to any one of claims 21 to 23, wherein the value of the internal width of the cavity minus the opening width of the cavity is greater than or equal to 30 nanometers.
The manufacturing method according to any one of claims 21 to 23, wherein the withstand voltage of the trench gate MOSFET power semiconductor device is 120V to 300V.
22. The manufacturing method according to any one of claims 21 to 23, wherein the etch-back of the i-th polysilicon layer adopts dry etching or wet etching.
22. The manufacturing method according to any one of claims 21 to 23, wherein the etching depth of the i-th polysilicon layer is etched back by the position of the cavity or the gap defect, and the etching depth ranges from 0.5 to 11 microns .
The manufacturing method according to any one of claims 21 to 23, wherein in step d) the ith polysilicon layer is etched back to expose the voids or gaps in the ith polysilicon layer while exposing the surface of the epitaxial layer The insulating layer and part of the insulating layer in the trench.
22. The manufacturing method according to any one of claims 21 to 23, wherein in step e), the cavities or gaps in the i-th polysilicon layer are exposed while filling the (i+1)th polysilicon layer while exposing the epitaxial layer. The insulating layer of the layer and part of the insulating layer in the trench are filled with an i+1th polysilicon layer.
The manufacturing method according to any one of claims 21 to 23, wherein in step d), the i-th polysilicon layer is etched back for the i-th time, and the remaining i-th polysilicon layer after the etch-back is open, and the remaining i-th polysilicon layer is open. The polysilicon layer gradually decreases from the top of the opening downward.
The manufacturing method according to any one of claims 21 to 23, wherein the i+1th polysilicon layer filled in step e) covers the remaining i-th polysilicon layer after etch-back and the remaining i-th polysilicon layer after etch-back A void or gap surrounded by a layer.
The manufacturing method according to any one of claims 21 to 23, wherein the distance between the void or gap generated by the filled (i+1)th polysilicon layer and the opening of the cavity is less than the distance between the void or gap generated by the (i+1)th polysilicon layer and the opening of the cavity. The distance of the opening of the cavity.
The manufacturing method according to claim 21, wherein the depth of the body region is not less than the depth of the gate dielectric and the gate conductor.
A trench gate MOSFET power semiconductor device formed by the manufacturing method of any one of claims 21 to 41, comprising:

A semiconductor substrate, the semiconductor substrate serving as a drain region;

An epitaxial layer on the semiconductor substrate;

A trench located in the epitaxial layer;

An insulating layer located in the trench, the insulating layer surrounding the cavity formed by the trench; and,

A shielding conductor formed by filling the cavity with polysilicon;

The gate dielectric and the gate conductor located on the upper part of the insulating layer in the trench, the gate dielectric is located on the upper sidewalls of the trench and the shield conductor, and the gate conductor is located on the gate dielectric between;

The body region and the source region in the region where the epitaxial layer is adjacent to the trench, and the doping types of the body region and the source region are opposite; and

The electrical connection structure of the gate conductor, the shielding conductor, the source region and the drain region.
The trench gate MOSFET power semiconductor device according to claim 42, wherein the width of the trench is 1 to 5 microns, and the depth of the trench is 5 to 12 microns.
The trench gate MOSFET power semiconductor device of claim 42, wherein the width of the trench is 1 to 3 microns, and the depth of the trench is 7 to 12 microns.
The trench gate MOSFET power semiconductor device of claim 42, wherein the thickness of the insulating layer is 0.1 to 2 microns.
The trench gate MOSFET power semiconductor device of claim 42, wherein the thickness of the insulating layer is 0.6 to 1.5 micrometers.
The trench gate MOSFET power semiconductor device according to claim 42, wherein the thickness of the insulating layer at the opening of the trench is greater than the thickness of the insulating layer inside the trench.
The trench gate MOSFET power semiconductor device according to claim 47, wherein the width between the sidewalls of the insulating layer at the opening of the trench is smaller than the maximum width between the sidewalls of the insulating layer inside the trench .
The trench gate MOSFET power semiconductor device according to claim 48, wherein the maximum width between the sidewalls of the insulating layer inside the trench minus the width between the sidewalls of the insulating layer at the opening of the trench The width is greater than or equal to 30 nanometers.
The trench gate MOSFET power semiconductor device of claim 42, wherein the trench gate MOSFET power semiconductor device has a withstand voltage of 120V to 300V.
The trench gate MOSFET power semiconductor device of claim 42, wherein the depth of the body region is not less than the depth of the gate dielectric and the gate conductor.
The trench gate MOSFET power semiconductor device according to claim 42, wherein the electrical connection structure includes a plurality of connections respectively connected to the gate conductor, the shield conductor, the source region, and the drain region. electrode.
The trench gate MOSFET power semiconductor device of claim 52, wherein the electrical connection structure further comprises a plurality of conductive channels, and the gate conductor, the shield conductor, and the source region are connected via corresponding conductive channels To the corresponding electrode, the drain region is in contact with the corresponding electrode.