CN114023812A - Shielded gate trench type MOSFET device and manufacturing method thereof - Google Patents

Shielded gate trench type MOSFET device and manufacturing method thereof Download PDF

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CN114023812A
CN114023812A CN202111224819.2A CN202111224819A CN114023812A CN 114023812 A CN114023812 A CN 114023812A CN 202111224819 A CN202111224819 A CN 202111224819A CN 114023812 A CN114023812 A CN 114023812A
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dielectric layer
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CN114023812B (en
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颜树范
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/66409—Unipolar field-effect transistors
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Abstract

The application discloses a shielded gate trench type MOSFET device and a manufacturing method thereof, and relates to the field of semiconductor manufacturing. The shielding grid groove type MOSFET device comprises a substrate, wherein a groove is arranged in the substrate; the lower part of the trench is filled with a shielding gate dielectric layer and a first polycrystalline silicon layer, and the shielding gate dielectric layer covers the side wall and the bottom of the lower part of the trench; the upper part of the groove is filled with a first dielectric layer, a second polycrystalline silicon layer and a second dielectric layer, and the top of the second polycrystalline silicon layer is lower than the surface of the substrate; the substrate is provided with a well region and a Schottky injection region, and the well region is provided with a source region and a well contact region; the Schottky injection region is positioned at the outer side of the well region, the bottom of the Schottky injection region is higher than the bottom of the well region, the well contact region is positioned on the side wall of the well region and is adjacent to the Schottky injection region, and the surface of the Schottky injection region is lower than the bottom of the well contact region; the problem that the switching speed of the shielded gate trench type MOSFET device is low is solved, and the effect of improving the switching speed is achieved.

Description

Shielded gate trench type MOSFET device and manufacturing method thereof
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to a shielded gate trench type MOSFET device and a manufacturing method thereof.
Background
As the demand for electronic products increases, the demand for power MOSFET devices also increases. The trench MOSFET is widely used in the low-voltage power field due to its high integration level, low on-resistance, and large current capacity.
Based on the improvement of the performance requirements of electronic products, the performance requirements of power MOSFET devices used in the electronic products are higher and higher, and the shielded gate trench MOSFET devices seek faster switching speed.
Disclosure of Invention
In order to solve the problems in the related art, the present application provides a shielded gate trench MOSFET device and a method for manufacturing the same. The technical scheme is as follows:
in a first aspect, an embodiment of the present application provides a shielded gate trench MOSFET device, including:
a substrate having a trench disposed therein;
the lower part of the trench is filled with a shielding gate dielectric layer and a first polycrystalline silicon layer, the shielding gate dielectric layer covers the side wall and the bottom of the lower part of the trench, and the first polycrystalline silicon layer is positioned between the shielding gate dielectric layers;
the upper part of the groove is filled with a first dielectric layer, a second polysilicon layer and a second dielectric layer, the first dielectric layer is positioned above the shielding gate dielectric layer and the first polysilicon layer, the second polysilicon layer is positioned above the first dielectric layer, the second dielectric layer is positioned above the second polysilicon layer, and the top of the second polysilicon layer is lower than the surface of the substrate; the surface of the second dielectric layer is higher than the surface of the well region, or the surface of the second dielectric layer is flush with the surface of the well region;
the substrate is provided with a well region and a Schottky injection region, and the well region is provided with a source region and a well contact region;
well region is located the outside of slot, and the schottky injection region is located the outside of well region, and the bottom in schottky injection region is higher than the bottom in well region, and the well contact zone is located the lateral wall in well region and adjacent with the schottky injection region, and the surface in schottky injection region is less than the bottom in well contact zone, and the source region is located the both sides of slot and is the distribution of type of falling L.
Optionally, the substrate further comprises a front metal layer on the front surface of the substrate, and a back metal layer on the back surface of the substrate
In a second aspect, embodiments of the present application provide a method for manufacturing a shielded gate trench MOSFET device, where the method includes:
forming a hard mask layer on the surface of the substrate, and forming a groove in the substrate through photoetching and etching processes;
forming a shielding gate dielectric layer and a first polycrystalline silicon layer, wherein the shielding gate dielectric layer covers the side wall of the lower part of the groove and the bottom of the groove, and the first polycrystalline silicon layer is positioned between the shielding gate dielectric layers;
forming a first dielectric layer and a second polysilicon layer, wherein the first dielectric layer is positioned above the first polysilicon layer, the second polysilicon layer is positioned above the first dielectric layer, and the surface of the second polysilicon layer is lower than the surface of the substrate;
carrying out transverse etching on the hard mask layer, and forming a well region in the substrate outside the groove;
forming source regions in inverted L-shaped distribution in the well region by an ion implantation process;
forming a second dielectric layer covering the second polysilicon layer and the well region, wherein the second dielectric layer does not cover the hard mask layer;
removing the hard mask layer, and forming a well contact region on the side wall of the well region, wherein the well contact region is far away from the groove;
forming a Schottky injection region on the outer side of the well region, wherein the bottom of the Schottky injection region is higher than the bottom of the well region, and the surface of the Schottky injection region is lower than the bottom of the well contact region;
etching the second dielectric layer to expose the surface of the source region; the surface of the second medium layer after etching is higher than the surface of the well region, or the surface of the second medium layer after etching is flush with the surface of the well region.
Optionally, forming the shield gate dielectric layer and the first polysilicon layer includes:
forming a shielding gate dielectric layer on the side wall and the bottom of the groove;
forming a first polysilicon filling groove;
and carrying out back etching on the first polysilicon to form a first polysilicon layer, wherein the surface of the first polysilicon layer is lower than the surface of the substrate.
Optionally, forming a first dielectric layer and a second polysilicon layer includes:
forming a first dielectric layer above the first polycrystalline silicon layer in the groove, wherein the surface of the first dielectric layer is lower than the surface of the substrate, and the shielding gate dielectric layer above the first dielectric layer in the groove is removed;
and forming a second polycrystalline silicon layer above the first dielectric layer, wherein the surface of the second polycrystalline silicon layer is lower than the surface of the substrate.
Optionally, performing lateral etching on the hard mask layer, and forming a well region in the substrate outside the trench, including:
performing transverse etching on the hard mask layer, and defining a well injection region pattern on the outer side of the groove;
a well region is formed in the substrate outside the trench by an ion implantation process.
Optionally, forming the source region in the inverted L-shaped distribution in the well region by an ion implantation process includes:
and performing angled ion implantation to form source regions on the top of the well region and the side wall of the groove above the second polycrystalline silicon layer, wherein the source regions are distributed in an inverted L shape.
Optionally, forming a second dielectric layer covering the second polysilicon layer and the well region includes:
forming a second dielectric layer, wherein the second dielectric layer covers the hard mask layer, the well region and a second polycrystalline silicon layer in the groove;
and removing the second dielectric layer above the hard mask layer.
Optionally, removing the hard mask layer, and forming a well contact region on a sidewall of the well region, including:
removing the hard mask layer;
taking the second medium layer as a mask, and carrying out first contact hole etching to form a first contact hole;
and injecting doping ions into the bottom of the first contact hole and the side wall of the well region outside the first contact hole by angled ion injection.
Optionally, forming a schottky injection region outside the well region includes:
taking the second dielectric layer as a mask, and performing second contact hole etching to form a second contact hole, wherein the bottom of the second contact hole is lower than that of the well contact area;
and forming a Schottky injection region in the substrate below the second contact hole by an ion injection process, wherein the bottom of the Schottky injection region is higher than that of the well region.
Optionally, after etching the second dielectric layer to expose the surface of the source region, the method further includes:
forming a front metal layer on the front surface of the substrate;
and forming a back metal layer on the back of the substrate.
The technical scheme at least comprises the following advantages:
the groove shielding gate is manufactured in the substrate, the well contact area is formed on the side wall of the well area, the Schottky injection area is formed at the position, which is lower than the well contact area, of the outer side of the well area, the Schottky injection area is in Schottky contact with the epitaxial layer, the problem that the switching speed of the existing shielding gate groove type MOSFET device is low is solved, the forward conduction voltage of a body diode is reduced, and the switching speed is improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a shielded gate trench MOSFET device according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a shielded gate trench MOSFET device according to another embodiment of the present application;
fig. 3 is a schematic structural diagram of a shielded gate trench MOSFET device according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a shielded gate trench MOSFET device according to another embodiment of the present application;
fig. 5 is a flowchart of a method for manufacturing a shielded gate trench MOSFET device according to an embodiment of the present application;
fig. 6 is a schematic diagram of a device in a process of manufacturing a shielded gate trench MOSFET device according to an embodiment of the present application;
fig. 7 is a schematic diagram of a device in a process of manufacturing a shielded gate trench MOSFET device according to an embodiment of the present application;
fig. 8 is a schematic diagram of a device in a process of manufacturing a shielded gate trench MOSFET device according to an embodiment of the present application;
fig. 9 is a schematic diagram of a device in a process of manufacturing a shielded gate trench MOSFET device according to an embodiment of the present application;
fig. 10 is a schematic diagram of a device in a process of manufacturing a shielded gate trench MOSFET device according to an embodiment of the present application;
fig. 11 is a schematic diagram of a device in a process of manufacturing a shielded gate trench MOSFET device according to an embodiment of the present application;
fig. 12 is a schematic diagram of a device in a process of manufacturing a shielded gate trench MOSFET device according to an embodiment of the present application;
fig. 13 is a schematic diagram of a device in a process of manufacturing a shielded gate trench MOSFET device according to an embodiment of the present application;
fig. 14 is a schematic diagram of a device in a process of manufacturing a shielded gate trench MOSFET device according to an embodiment of the present application;
fig. 15 is a schematic diagram of a device in a process of manufacturing a shielded gate trench MOSFET device according to an embodiment of the present application;
fig. 16 is a schematic diagram of a device in the process of manufacturing a shielded gate trench MOSFET device according to an embodiment of the present application;
fig. 17 is a schematic diagram of a device in the process of manufacturing a shielded gate trench MOSFET device according to an embodiment of the present application;
fig. 18 is a schematic diagram of another device in the process of manufacturing a shielded gate trench MOSFET device according to an embodiment of the present application;
fig. 19 is a schematic diagram of another device in the process of manufacturing a shielded gate trench MOSFET device according to an embodiment of the present application;
110, a substrate; 111, shielding a gate dielectric layer; 112, a first polysilicon layer; 113, a first dielectric layer; 114. a second polysilicon layer; 115. a second dielectric layer; 116, a well region; 117, schottky implant region; 118, a source region; 119, a well contact region; 120, a front metal layer; 121, a back metal layer; 210, a hard mask layer; 211, a trench; 212, a first contact hole; 213, a second contact hole.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Please refer to fig. 1 and fig. 2, which illustrate schematic structural diagrams of a shielded gate trench MOSFET device according to an embodiment of the present application. The shielded gate trench type MOSFET device includes:
a substrate 110, the substrate 110 having a trench disposed therein.
Optionally, the substrate is composed of a silicon substrate and an epitaxial layer over the silicon substrate.
The space in the groove is divided into an upper portion and a lower portion.
The lower portion of the trench is filled with a shield gate dielectric layer 111 and a first polysilicon layer 112, the shield gate dielectric layer 111 covers the sidewall of the lower portion of the trench and the bottom of the trench, and the first polysilicon layer 112 is located between the shield gate dielectric layers 111.
The upper part of the trench is filled with a first dielectric layer 113, a second polysilicon layer 114 and a second dielectric layer 115, the first dielectric layer 113 is located above the shield gate dielectric layer 111 and the first polysilicon layer 112, the second polysilicon layer 114 is located above the first dielectric layer 113, the second dielectric layer 115 is located above the second polysilicon layer 114, and the top of the second polysilicon layer 115 is lower than the surface of the substrate 110.
A well region 116 and a schottky implant region 117 are disposed in the substrate 110, and a source region 118 and a well contact region 119 are disposed in the well region 116.
Well region 116 is located outside the trench, schottky implant region 117 is located outside well region 116, the bottom of schottky implant region 117 is higher than the bottom of well region 116, and the surface of schottky implant region 117 is lower than the surface of well region 116.
Well contact regions 119 are located on the sidewalls of the well region and adjacent to schottky implant regions 117.
The surface of the schottky implant region 117 is below the bottom of the well contact region 119.
The source regions 118 are located on both sides of the trench and have an inverted L-shaped distribution.
In one example, in a shielded gate trench MOSFET device, the surface of second dielectric layer 115 is higher than the surface of well region 116, as shown in fig. 1.
In another example, in a shielded gate trench MOSFET device, the surface of second dielectric layer 115 is flush with the surface of well region 116, as shown in fig. 2.
The shielded gate trench type MOSFET device further includes a front metal layer on the front side of the substrate and a back metal layer on the back side of the substrate.
As shown in fig. 3, the surface of the second dielectric layer 115 is higher than the surface of the well region 116, the front surface of the substrate 110 is provided with a front metal layer 120, the back surface of the substrate 110 is provided with a back metal layer 121, and the front metal layer 120 is connected to the well contact region 119, the source region 118, and the schottky injection region 117.
As shown in fig. 4, the surface of the second dielectric layer 115 is flush with the surface of the well region 116, the front surface of the substrate 110 is provided with a front metal layer 120, the back surface of the substrate 110 is provided with a back metal layer 121, and the front metal layer 120 is connected to the well contact region 119, the source region 118, and the schottky injection region 117.
The utility model provides a shield gate trench type MOSFET device, the source region that is the distribution of type of falling L in well region formation, lateral wall at well region forms the well contact zone, form the schottky injection region that is less than the well contact zone in the well contact zone outside, positive metal level and source region surface, well contact zone side and schottky injection region surface contact, the regional epitaxy of schottky injection at contact hole bottom forms the schottky contact, body diode forward conduction voltage has been reduced, can promote slew velocity.
Referring to fig. 5, a flow chart of a method for manufacturing a shielded gate trench MOSFET device according to an embodiment of the present application is shown, the method at least includes the following steps:
step 501, forming a hard mask layer on the surface of a substrate, and forming a trench in the substrate through photoetching and etching processes.
Optionally, the substrate is composed of a silicon substrate and an epitaxial layer over the silicon substrate.
Step 502, forming a shielding gate dielectric layer and a first polysilicon layer, wherein the shielding gate dielectric layer covers the side wall of the lower part of the trench and the bottom of the trench, and the first polysilicon layer is positioned between the shielding gate dielectric layers.
The space in the groove is divided into an upper space and a lower space.
Step 503, forming a first dielectric layer and a second polysilicon layer.
The first dielectric layer is positioned above the first polycrystalline silicon layer, the second polycrystalline silicon layer is positioned above the first dielectric layer, and the surface of the second polycrystalline silicon layer is lower than the surface of the substrate.
The first polysilicon layer is completely surrounded by the first dielectric layer and the shield gate dielectric layer.
Step 504, the hard mask layer is laterally etched, and a well region is formed in the substrate outside the trench.
Transversely etching the hard mask layers on two sides of the groove to expose part of the surface of the substrate; a well region is formed beneath the exposed substrate surface by an ion implantation process.
In step 505, source regions are formed in the well region in an inverted L-shaped distribution by an ion implantation process.
Step 506 forms a second dielectric layer overlying the second polysilicon layer and the well region.
The second dielectric layer does not cover the hard mask layer.
In step 507, the hard mask layer is removed, and a well contact region is formed on the side wall of the well region.
The well contact region is remote from the trench.
Removing the hard mask layer outside the well region, and etching the substrate outside the well region to make the surface of the substrate outside the well region lower than the surface of the well region; and forming a well contact region on the side wall of the well region by an ion implantation process.
And step 508, forming a schottky injection region outside the well region, wherein the bottom of the schottky injection region is higher than the bottom of the well region, and the surface of the schottky injection region is lower than the surface of the well contact region.
Because the well contact region is positioned on the side wall of the well region, when the Schottky injection region is formed, the substrate outside the well region needs to be continuously etched until the surface of the substrate is lower than the surface of the well contact region, and then the Schottky injection region is formed through an ion injection process.
The Schottky injection region and the silicon surface form Schottky contact, which is beneficial to reducing the forward conduction voltage of the body diode and can improve the conversion speed.
Step 509, the second dielectric layer is etched to expose the surface of the source region.
In one example, the surface of the second dielectric layer after etching is higher than the surface of the well region.
In another example, the surface of the second dielectric layer after etching is flush with the surface of the well region.
In summary, the method for manufacturing the trench type MOSFET device of the shield gate according to the embodiment of the present application manufactures the trench shield gate in the substrate, forms the well contact region on the sidewall of the well region, and forms the schottky injection region at a position outside the well region and lower than the well contact region, so that the schottky injection region and the epitaxial layer form the schottky contact.
Another embodiment of the present application provides a method for manufacturing a shielded gate trench MOSFET device, including the steps of:
step 601, forming a hard mask layer on the surface of the substrate, and forming a groove in the substrate through photoetching and etching processes.
Optionally, several hard mask layers are formed on the surface of the substrate. For example, three hard mask layers are formed on the substrate surface.
Defining a groove pattern on the surface of the hard mask layer through a photoetching process, etching the hard mask layer, copying the groove pattern into the hard mask layer, and removing the photoresist on the surface of the hard mask layer; and etching the substrate by taking the etched hard mask layer as a mask to form a groove in the substrate.
As shown in fig. 6, a hard mask layer 210 is formed on the surface of the substrate 110, and a trench 211 is formed in the substrate 110.
Step 602, a shield gate dielectric layer is formed on the sidewall and the bottom of the trench.
A shield gate dielectric layer is grown, and as shown in fig. 7, a shield gate dielectric layer 111 is formed on the sidewall and bottom of the trench 211.
Step 603, forming a first polysilicon filled trench.
As shown in fig. 8, a first polysilicon 112 is deposited to fill the trench.
Step 604, performing a back etching on the first polysilicon layer to form a first polysilicon layer, wherein the surface of the first polysilicon layer is lower than the surface of the substrate.
The space in the trench is divided into an upper space and a lower space, and a first polysilicon layer 112 formed by etching back the first polysilicon is located at the lower part of the trench, as shown in fig. 9.
Step 605, a first dielectric layer is formed above the first polysilicon layer in the trench, and the surface of the first dielectric layer is lower than the surface of the substrate.
Optionally, growing a first dielectric layer to fill the trench, performing back etching on the substrate, retaining the first dielectric layer with a predetermined thickness, and removing the shield gate dielectric layer above the first dielectric layer.
As shown in fig. 10, the surface of the first dielectric layer 113 is lower than the surface of the substrate 110, the first dielectric layer 113 covers the first polysilicon layer 112, and the first polysilicon layer 112 is surrounded by the first dielectric layer 113 and the shield gate dielectric layer 111.
Step 606, a second polysilicon layer is formed over the first dielectric layer, the surface of the second polysilicon layer being lower than the substrate surface.
And depositing second polysilicon to fill the groove, and performing back etching on the second polysilicon to form a second polysilicon layer. The second polysilicon layer is in the trench, and the surface of the second polysilicon layer is lower than the surface of the substrate.
As shown in fig. 11, the surface of the second polysilicon layer 114 is lower than the surface of the substrate 110.
Step 607, the hard mask layer is laterally etched to define the well implantation region pattern outside the trench.
And transversely etching the hard mask layers on two sides of the groove to expose part of the surface of the substrate and form a well injection region pattern.
At 608, a well region is formed in the substrate outside the trench by an ion implantation process.
And performing well region ion implantation on the substrate corresponding to the well implantation region pattern by using the etched hard mask layer 210 as a mask, and performing well drive, as shown in fig. 12, to form a well region 116 in the substrate 110 outside the trench.
And step 609, performing angled ion implantation, and forming a source region on the top of the well region and the side wall of the groove above the second polysilicon layer, wherein the source region is distributed in an inverted L shape.
As shown in fig. 13, a source region 118 is formed on the sidewall of the trench and the top of the well region above the second polysilicon layer 114, and the source region 118 has an inverted L shape.
Step 610, a second dielectric layer is formed, and the second dielectric layer covers the hard mask layer, the well region and the second polysilicon layer in the groove.
As shown in fig. 14, a second dielectric layer 115 is deposited on the substrate 110, the second dielectric layer 115 fills the remaining space in the trench, and the second dielectric layer 115 covers the hard mask layer 122, the well region 116, and the second polysilicon layer 114 in the trench.
Step 611, the second dielectric layer above the hard mask layer is removed.
The second dielectric layer 115 is etched back or CMP processed to reduce the thickness of the second dielectric layer 115 such that the top of the second dielectric layer 115 is flush with the hard mask layer 210, as shown in fig. 15.
Step 612, the hard mask layer is removed.
As shown in fig. 16, the hard mask layer outside the second dielectric layer 115 is removed.
Step 613, using the second dielectric layer as a mask, performing a first contact hole etching to form a first contact hole.
And etching the substrate 110 by using the second dielectric layer 115 as a mask to form a first contact hole, wherein the bottom of the first contact hole is lower than the surface of the substrate.
And 614, injecting doping ions into the bottom of the first contact hole and the side wall of the well region outside the first contact hole through angled ion injection.
As shown in fig. 17, a well contact region 119 is formed at the bottom of the first contact hole 212 and the sidewall of the well region outside the first contact hole by angled ion implantation.
And 615, taking the second dielectric layer as a mask, and performing second contact hole etching to form a second contact hole, wherein the bottom of the second contact hole is lower than the bottom of the well contact area.
And (3) taking the second dielectric layer 115 as a mask, performing second contact hole etching to cut through the well contact region at the bottom of the first contact hole to form a second contact hole 213, wherein the bottom of the second contact hole 213 is lower than the bottom of the well contact region 119 located on the side wall of the well region 116, as shown in fig. 18.
And 616, forming a schottky injection region in the substrate below the second contact hole through an ion injection process, wherein the bottom of the schottky injection region is higher than the bottom of the well region.
As shown in fig. 19, dopant ions are implanted into the bottom of the second contact hole 213 to form a schottky injection region 117, and the bottom of the schottky injection region 117 is higher than the bottom of the well 116.
The schottky injection region 117 forms schottky contact with the epitaxy, so that the forward conduction voltage of the body diode is reduced, and the switching speed is favorably improved.
Step 617, the second dielectric layer is etched to expose the source region.
As shown in fig. 19, the surface of source region 118 is covered by second dielectric layer 115. And etching the second dielectric layer to expose the surface of the source region.
In one example, as shown in fig. 1, the surface of etched second dielectric layer 115 is higher than the surface of well region 116.
In another example, as shown in fig. 2, the surface of second dielectric layer 115 after etching is flush with the surface of well region 116.
At step 618, a front metal layer is formed on the front surface of the substrate.
A front metal layer is formed on the front surface of the substrate 110, and the front metal layer is connected to the surface of the schottky implant region 117, the surface of the source region 118, and the side surface of the well contact region 119.
Step 619, a backside metal layer is formed on the backside of the substrate.
Optionally, the back surface of the substrate is thinned, and metal is deposited on the back surface of the substrate to form a back metal layer.
As shown in fig. 3 or 4, the front surface of the substrate 110 forms a front metal layer 120, and the back surface of the substrate 110 forms a back metal layer 121.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims (11)

1. A shielded gate trench MOSFET device comprising:
a substrate having a trench disposed therein;
the lower part of the groove is filled with a shielding gate dielectric layer and a first polycrystalline silicon layer, the shielding gate dielectric layer covers the side wall and the bottom of the lower part of the groove, and the first polycrystalline silicon layer is positioned between the shielding gate dielectric layers;
the upper part of the groove is filled with a first dielectric layer, a second polycrystalline silicon layer and a second dielectric layer, the first dielectric layer is positioned above the shielding grid dielectric layer and the first polycrystalline silicon layer, the second polycrystalline silicon layer is positioned above the first dielectric layer, the second dielectric layer is positioned above the second polycrystalline silicon layer, and the top of the second polycrystalline silicon layer is lower than the surface of the substrate; the surface of the second dielectric layer is higher than the surface of the well region, or the surface of the second dielectric layer is flush with the surface of the well region;
the substrate is provided with a well region and a Schottky injection region, and the well region is provided with a source region and a well contact region;
the Schottky injection region is arranged on the outer side of the groove, the Schottky injection region is arranged on the outer side of the well region, the bottom of the Schottky injection region is higher than the bottom of the well region, the well contact region is arranged on the side wall of the well region and is adjacent to the Schottky injection region, the surface of the Schottky injection region is lower than the bottom of the well contact region, and the source regions are arranged on two sides of the groove and are distributed in an inverted L shape.
2. The shielded gate trench MOSFET device of claim 1 further comprising a front side metal layer on the front side of the substrate and a back side metal layer on the back side of the substrate.
3. A method for manufacturing a shielded gate trench MOSFET device, the method comprising:
forming a hard mask layer on the surface of a substrate, and forming a groove in the substrate through photoetching and etching processes;
forming a shielding grid dielectric layer and a first polycrystalline silicon layer, wherein the shielding grid dielectric layer covers the side wall of the lower part of the groove and the bottom of the groove, and the first polycrystalline silicon layer is positioned between the shielding grid dielectric layers;
forming a first dielectric layer and a second polysilicon layer, wherein the first dielectric layer is positioned above the first polysilicon layer, the second polysilicon layer is positioned above the first dielectric layer, and the surface of the second polysilicon layer is lower than the surface of the substrate;
carrying out transverse etching on the hard mask layer, and forming a well region in the substrate outside the groove;
forming source regions in inverted L-shaped distribution in the well region by an ion implantation process;
forming a second dielectric layer covering the second polysilicon layer and the well region, wherein the second dielectric layer does not cover the hard mask layer;
removing the hard mask layer, and forming a well contact region on the side wall of the well region, wherein the well contact region is far away from the groove;
forming a Schottky injection region outside the well region, wherein the bottom of the Schottky injection region is higher than the bottom of the well region, and the surface of the Schottky injection region is lower than the bottom of the well contact region;
etching the second dielectric layer to expose the surface of the source region; the surface of the second medium layer after etching is higher than the surface of the well region, or the surface of the second medium layer after etching is flush with the surface of the well region.
4. The method of claim 3, wherein the forming the shield gate dielectric layer and the first polysilicon layer comprises:
forming a shielding gate dielectric layer on the side wall and the bottom of the groove;
forming first polysilicon to fill the trench;
and carrying out back etching on the first polycrystalline silicon to form the first polycrystalline silicon layer, wherein the surface of the first polycrystalline silicon is lower than the surface of the substrate.
5. The method of claim 3, wherein the forming the first dielectric layer and the second polysilicon layer comprises:
forming a first dielectric layer above the first polycrystalline silicon layer in the groove, wherein the surface of the first dielectric layer is lower than the surface of the substrate, and the shielding gate dielectric layer above the first dielectric layer in the groove is removed;
and forming a second polycrystalline silicon layer above the first dielectric layer, wherein the surface of the second polycrystalline silicon layer is lower than the surface of the substrate.
6. The method of claim 3, wherein laterally etching the hard mask layer and forming a well region in the substrate outside the trench comprises:
performing transverse etching on the hard mask layer, and defining a well injection region pattern on the outer side of the groove;
and forming a well region in the substrate outside the groove through an ion implantation process.
7. The method of claim 3, wherein forming the source region in an inverted L-shape distribution in the well region by an ion implantation process comprises:
and performing angled ion implantation, and forming a source region on the top of the well region and the side wall of the groove above the second polycrystalline silicon layer, wherein the source region is distributed in an inverted L shape.
8. The method of claim 3, wherein forming a second dielectric layer overlying the second polysilicon layer and the well region comprises:
forming a second dielectric layer which covers the hard mask layer, the well region and a second polycrystalline silicon layer in the groove;
and removing the second dielectric layer above the hard mask layer.
9. The method of claim 3, wherein removing the hard mask layer to form well contact regions on sidewalls of the well region comprises:
removing the hard mask layer;
taking the second medium layer as a mask, and carrying out first contact hole etching to form a first contact hole;
and injecting doping ions into the bottom of the first contact hole and the side wall of the well region outside the first contact hole through angled ion injection.
10. The method of claim 3, wherein forming a Schottky implant region outside the well region comprises:
taking the second dielectric layer as a mask, and performing second contact hole etching to form a second contact hole, wherein the bottom of the second contact hole is lower than the bottom of the well contact area;
and forming a Schottky injection region in the substrate below the second contact hole by an ion injection process, wherein the bottom of the Schottky injection region is higher than the bottom of the well region.
11. The method according to any of claims 3 to 10, wherein after the etching the second dielectric layer to expose the surface of the source region, the method further comprises:
forming a front metal layer on the front surface of the substrate;
and forming a back metal layer on the back of the substrate.
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