CN110620153A - Shielded gate field effect transistor and manufacturing method thereof - Google Patents
Shielded gate field effect transistor and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title description 16
- 238000002353 field-effect transistor method Methods 0.000 title description 2
- 238000005530 etching Methods 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 31
- 230000005669 field effect Effects 0.000 claims abstract description 30
- 239000000463 material Substances 0.000 claims abstract description 27
- 238000000151 deposition Methods 0.000 claims abstract description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 239000011810 insulating material Substances 0.000 claims description 7
- 229910052681 coesite Inorganic materials 0.000 claims description 4
- 229910052906 cristobalite Inorganic materials 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 229910052682 stishovite Inorganic materials 0.000 claims description 4
- 229910052905 tridymite Inorganic materials 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 230000005684 electric field Effects 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000009826 distribution Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a method for forming a shielded gate field effect transistor, which comprises the following steps: depositing a first dielectric layer on the inner wall of a groove formed in the conductive epitaxial layer, wherein the first dielectric layer is of a groove-shaped structure, and filling a shielding grid in the groove of the first dielectric layer and etching back the shielding grid; etching back the first dielectric layer to enable the top of the first dielectric layer to be flush with the top of the shielding grid; filling a second dielectric layer to a first target thickness on the tops of the first dielectric layer and the shielding gate, wherein two sides of the second dielectric layer are in contact with the inner wall of the groove, and the second dielectric layer and the first dielectric layer are made of different materials; and growing a grid oxide layer on the upper part of the second dielectric layer and on the inner wall of the groove, and then depositing a grid, wherein the grid is positioned in the middle of the grid oxide layer. The technical scheme disclosed by the invention can freely adjust the required capacitance according to the requirement.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a shielded gate field effect transistor and a manufacturing method thereof.
Background
A shielding gate (Shield gate) field effect transistor (MOSFET) is called SGT for short, the low on-resistance of the MOSFET is widely applied to the field of medium and low voltage switching devices, the MOSFET is used as a longitudinal voltage-resistant device, when the MOSFET works reversely, the MOSFET and N-type doped (N-EPI) are mutually depleted through a P-type doped well (P-well), and the electric field distribution of the MOSFET is a triangular electric field according to a Poisson equation. The breakdown voltage versus resistance relationship at a particular N-type doping concentration is limited by the silicon limit (a law that exists for the mutual limit between product breakdown voltage and on-resistance). By introducing a shielded gate structure (which is shorted to the source) into the original N-doped epitaxial layer, a lateral electric field is formed. And finally, the triangular electric field distribution is changed into the trapezoidal electric field distribution, so that the silicon limit limitation is broken through, and the lower on-resistance is realized in the same area. For the SGT, the key parameters are Cgd (capacitance between the gate and the drain) and Cgs (capacitance between the gate and the source), because of the characteristics of the product, the switching speed is fast, the EMI (electromagnetic interference) problem is easy to occur in the fast switching process, and meanwhile, the capacitance is directly related to the dynamic loss of the device, so that it is important to obtain a transistor with proper capacitance.
Disclosure of Invention
The object of the present application is to overcome the above problems or to at least partially solve or alleviate them, and the object of the present invention is to achieve a free adjustment of the required capacitance by means of an unconventional oxide layer.
According to a first aspect of the present application there is provided a method of forming a shielded gate field effect transistor comprising: depositing a first dielectric layer on the inner wall of a groove formed in the conductive epitaxial layer, wherein the first dielectric layer is of a groove-shaped structure, and filling a shielding grid in the groove of the first dielectric layer and etching back the shielding grid;
etching back the first dielectric layer to enable the top of the first dielectric layer to be flush with the top of the shielding grid;
filling a second dielectric layer to a first target thickness on the tops of the first dielectric layer and the shielding gate, wherein two sides of the second dielectric layer are in contact with the inner wall of the groove, and the second dielectric layer and the first dielectric layer are made of different materials;
and growing a grid oxide layer on the upper part of the second dielectric layer and on the inner wall of the groove, and then depositing a grid, wherein the grid is positioned in the middle of the grid oxide layer. Preferably, the cross-sectional area of the shielding grid is smaller than that of the second dielectric layer.
Preferably, the second dielectric layer is made of a material having a dielectric coefficient, and the first dielectric layer is made of an insulating material.
Preferably, the target thickness of the second dielectric layer is adjusted according to the capacitance of the transistor and the dielectric coefficient of the second dielectric.
Preferably, the second dielectric layer is made of one or two of SiN and SiLK, and the first dielectric layer is SiO 2.
Preferably, the thickness of the gate oxide layer is smaller than that of the first dielectric layer.
In another aspect, an embodiment of the present invention further provides a method for forming a shielded gate field effect transistor, including:
depositing a first dielectric layer on the inner wall of a groove formed in the conductive epitaxial layer, wherein the first dielectric layer is of a groove-shaped structure, and filling a shielding grid in the groove of the first dielectric layer and etching back the shielding grid;
filling a second dielectric layer to a second target thickness on the top of the shielding grid, and then etching back the first dielectric layer to enable the top of the first dielectric layer to be flush with the top of the shielding grid, wherein the second dielectric layer and the first dielectric layer are made of different materials;
carrying out back etching on the second dielectric layer to enable the top of the second dielectric layer to be higher than or lower than the first dielectric layer after back etching, or to enable the top of the second dielectric layer to be flush with the first dielectric layer after back etching;
and growing a grid oxide layer on the upper part of the second dielectric layer and on the inner wall of the groove, and then depositing a grid, wherein the grid is positioned in the middle of the grid oxide layer. Preferably, the cross-sectional area of the shielding grid is the same as that of the second dielectric layer.
Preferably, the second dielectric layer is made of a material having a dielectric coefficient, and the first dielectric layer is made of an insulating material.
Preferably, the target thickness of the second dielectric layer is adjusted according to the capacitance of the transistor and the dielectric coefficient of the second dielectric.
Preferably, the second dielectric layer is made of one or two of SiN and SiLK, and the first dielectric layer is SiO 2.
Preferably, the thickness of the gate oxide layer is smaller than that of the first dielectric layer.
In another aspect, an embodiment of the present invention further provides a shielded gate field effect transistor, which is manufactured by using any one of the above manufacturing methods.
In another aspect, an embodiment of the present invention further provides a shielded gate field effect transistor, which is characterized by being manufactured by using any one of the above manufacturing methods.
Compared with the prior art, the embodiment of the invention has the following advantages:
the embodiment of the invention discloses a shielded gate field effect transistor and a manufacturing method thereof, wherein the shielded gate field effect transistor is obtained by adopting different processes, different materials are adopted for a first dielectric layer and a second dielectric layer, the second dielectric layer is made of a material with a dielectric coefficient, the first dielectric layer is made of an insulating material, and the shielded gate transistor obtained by different manufacturing processes can realize freely adjusting the required capacitance.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. Some specific embodiments of the present application will be described in detail hereinafter by way of illustration and not limitation with reference to the accompanying drawings. The same reference numbers in the drawings identify the same or similar elements or components. Those skilled in the art will appreciate that the drawings are not necessarily drawn to scale. In the drawings:
FIG. 1 is a schematic structural diagram of a shielded gate field effect transistor according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method for manufacturing a shielded gate field effect transistor according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating an effect of an implementation manner of the invention after etching back a shielding gate;
fig. 4 is a schematic effect diagram of performing etching back on the first dielectric layer in an implementation manner according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating the effect of filling and growing a gate oxide layer and depositing a gate in an implementation manner according to an embodiment of the present invention;
FIG. 6 is a flow chart of a method of fabricating a shielded gate field effect transistor in accordance with another implementation of an embodiment of the invention;
fig. 7 is a diagram illustrating an etching-back effect performed on the first dielectric layer after the second dielectric layer is directly filled in another implementation manner according to the embodiment of the invention;
fig. 8 is an effect diagram of a second dielectric layer etching back, a gate oxide layer growing and a gate deposited in another implementation manner according to an embodiment of the invention.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Fig. 1 is a cross-sectional view of a shielded gate field effect transistor, the product structure includes a gate 01, a first dielectric layer 02, a shielded gate 03, a gate oxide layer 04, a second dielectric layer 05, a conductive epitaxial layer 06, a source metal 07, a drain metal 08, a source 09, and a P-well 10, as shown in fig. 1, the drain metal 08 is disposed at the lowest end of the transistor, the conductive epitaxial layer 06 is disposed above the drain metal 08, when the transistor is an N-type MOS transistor, the conductive epitaxial layer 06 is N-type doped, when the transistor is a P-type MOS transistor, the conductive epitaxial layer 06 is P-type doped, one or more trenches are formed in the conductive epitaxial layer 06, the first dielectric layer 02 is deposited in the trenches, the first dielectric layer 02 is an insulating layer, the first dielectric layer 02 covers the inner walls of the trenches, the first dielectric layer 02 is a groove-like structure, the shielded gate 03 is grown in the groove-like structure, the shielding grid 03 is made of polysilicon, the shielding grid 03 is in short circuit with the source electrode 09, a second dielectric layer 05 grows on the top of the shielding grid 03 and can cover the tops of the shielding grid 03 and the first dielectric layer 02 or only cover the top of the shielding grid 03, and the second dielectric layer 05 is made of a material with a dielectric coefficient, so that free control of capacitance between the grid and the drain electrode and capacitance between the grid and the source electrode is facilitated, and the problem of electromagnetic interference is not easy to occur in a rapid switching process.
A gate oxide layer 04 is disposed on the upper portion of the first dielectric layer 05, two sides of the gate oxide layer 04 are in contact with the trench, a gate 01 is grown in the middle of the gate oxide layer 04, a P-well 10 is disposed on the upper side of the conductive epitaxial layer 06, the doping type of the P-well 10 is opposite to that of the conductive epitaxial layer 06, a source 09 is disposed on the upper portion of the P-well 10, and two sides of the source 09 are in contact with the gate oxide layer 04. A source metal 7 is provided above the source 09 and the gate oxide layer 04.
The shielded gate field effect transistor disclosed by the embodiment of the invention can freely control the capacitance between the grid electrode and the drain electrode and the capacitance between the grid electrode and the source electrode, so that the problem of electromagnetic interference is not easy to occur in the rapid switching process.
On the other hand, the embodiment of the invention also discloses a manufacturing process of the shielded gate field effect transistor, as shown in fig. 2, fig. 2 is a flow chart of the manufacturing process of the shielded gate field effect transistor;
the method specifically comprises the following steps:
step S01, depositing a first dielectric layer on the inner wall of a groove formed in the conductive epitaxial layer, wherein the first dielectric layer is of a groove-shaped structure, and filling a shielding gate in the groove of the first dielectric layer and etching back the shielding gate;
as shown in fig. 3, fig. 3 is a diagram illustrating an effect of etching back a shielding gate in an implementation manner according to an embodiment of the present invention;
it should be noted that, the first dielectric layer, that is, the insulating layer, needs to be deposited, grown and extended, after the insulating layer grows well, since the insulating layer is of a groove-shaped structure, the shielding gate is deposited in the groove-shaped structure of the insulating layer, the specific shielding gate is made of polysilicon and is in short circuit with the source electrode, after the growth of the shielding gate is completed, the shielding gate is etched back as needed, that is, the depth of the shielding gate is reduced, and the requirement of the next process is met, and the depth of the specific shielding gate after etching back is slightly higher than or slightly lower than the depth of the first dielectric layer.
Step S02, etching back the first dielectric layer to make the top of the first dielectric layer flush with the top of the shield gate;
as shown in fig. 4, according to step S01, after the back etching is performed on the shielding gate, the first dielectric layer of the insulating layer needs to be back etched, and the depth of the first dielectric layer is reduced, so that the second dielectric layer can be filled, and specifically, the depth of the back etched first dielectric layer is flush with the top of the shielding gate, or slightly higher or lower than the shielding gate, which is beneficial to filling the second dielectric layer.
Step S03, filling a second dielectric layer to a first target thickness on the top of the first dielectric layer and the shielding gate, wherein two sides of the second dielectric layer are in contact with the inner wall of the trench, and the second dielectric layer and the first dielectric layer are made of different materials;
as shown in fig. 5, the cross-sectional area of the shielding gate is smaller than that of the second dielectric layer. When the second dielectric layer is filled to be the first target thickness, the specific target thickness is in direct proportion to the dielectric constant according to the plate capacitance and in inverse proportion to the target thickness L1 of the second dielectric layer, the size of the capacitor is adjusted according to the relation, the second dielectric layer is made of materials with dielectric coefficients, and the first dielectric layer is made of insulating materials. The second dielectric layer may be made of a single material having a specific dielectric constant, or may be made of at least one material having a specific dielectric constant. Optionally, the second dielectric layer is made of one or a mixture of SiN and SiLK, and the first dielectric layer is SiO2, but is not limited thereto. The second dielectric layer is made of non-oxide layer material, and the thickness of the second dielectric layer and the corresponding dielectric constant material can be selected according to the design requirement of the capacitor.
The target thickness of the second dielectric layer is adjusted according to the capacitance of the transistor and the dielectric coefficient of the constituent material of the second dielectric layer. The conventional dielectric layer can only adjust the thickness of the dielectric layer to realize the adjustment of the capacitance, and the embodiment of the invention can adjust the dielectric constant of the second dielectric layer to realize the required capacitance.
Step S04, growing a gate oxide layer on the upper portion of the second dielectric layer and on the inner wall of the trench, and then depositing a gate, where the gate is located in the middle of the gate oxide layer. .
As shown in fig. 5, the thickness of the gate oxide layer is smaller than that of the first dielectric layer.
The invention also discloses a shielded gate field effect transistor formed according to the manufacturing process as described in fig. 2.
As shown in fig. 6, on the other hand, the present invention also discloses another manufacturing process of a shielded gate field effect transistor, which specifically includes the following steps:
step S05, depositing a first dielectric layer on the inner wall of a groove formed in the conductive epitaxial layer, wherein the first dielectric layer is of a groove-shaped structure, and filling a shielding gate in the groove of the first dielectric layer and etching back the shielding gate;
as shown in fig. 3, fig. 3 is a diagram illustrating an effect of etching back a shielding gate in an implementation manner according to an embodiment of the present invention;
it should be noted that, the first dielectric layer, that is, the insulating layer, needs to be deposited, grown and extended, after the insulating layer grows well, since the insulating layer is of a groove-shaped structure, the shielding gate is deposited in the groove-shaped structure of the insulating layer, the specific shielding gate is made of polysilicon and is in short circuit with the source electrode, after the growth of the shielding gate is completed, the shielding gate is etched back as needed, that is, the depth of the shielding gate is reduced, the requirement of the next process is met, and the depth of the specific shielding gate after etching back needs to be slightly lower than or slightly higher than the depth of the first dielectric layer.
Step S06, filling a second dielectric layer to a second target thickness on the top of the shielding gate, and then etching back the first dielectric layer to make the top of the first dielectric layer flush with the top of the shielding gate, wherein the second dielectric layer is made of a different material from the first dielectric layer;
the cross-sectional area of the shielding grid is the same as that of the second dielectric layer, the second dielectric layer is made of a material with a dielectric coefficient, and the first dielectric layer is made of an insulating material.
The target thickness of the second dielectric layer is adjusted according to the capacitance of the transistor and the dielectric coefficient of the second dielectric layer, in the embodiment of the present invention, the second dielectric layer is made of one or a mixture of SiN and SiLK, and the first dielectric layer is SiO2, but is not limited thereto.
As shown in fig. 7, it should be noted that, first, a second dielectric layer is filled at the top of the shielding gate, where the second dielectric layer may be made of a single material with a specific dielectric coefficient or may be made of at least one material with a specific dielectric coefficient, the second dielectric layer is filled to a target thickness, then, the first dielectric layer is etched back to reach the target thickness, and the first dielectric layer after etching back may be slightly lower than, higher than, or flush with the shielding gate.
Step S07, performing etching back on the second dielectric layer to make the top of the second dielectric layer higher than or lower than the first dielectric layer after etching back, or to make the top of the second dielectric layer flush with the first dielectric layer after etching back;
as shown in fig. 8, it should be noted that, after the first dielectric layer is etched back according to step S06, the filled second dielectric layer needs to be etched back, so that the top of the etched-back second dielectric layer may be slightly lower than, higher than, or flush with the etched-back first dielectric layer.
Step S08, growing a gate oxide layer on the upper portion of the second dielectric layer and on the inner wall of the trench, and then depositing a gate, where the gate is located in the middle of the gate oxide layer. (ii) a
As shown in fig. 8, after the second dielectric layer is etched back to the target thickness, a gate oxide layer needs to be grown on the top of the second dielectric layer, the gate oxide layer is an insulating layer, and a gate is deposited in the middle of the gate oxide layer.
The thickness of the grid oxide layer is smaller than that of the first medium layer.
The invention also discloses a shielded gate field effect transistor formed according to the manufacturing process as described in fig. 6
According to the technical scheme disclosed by the invention, the required proper material with the dielectric coefficient and the deposition thickness can be calculated in advance according to the required capacitance, and the shielding grid field effect transistor can be manufactured according to the material selected in advance and the deposition thickness in the process of manufacturing the technology, and the process of manufacturing the shielding grid field effect transistor is changed due to the change of the material of the second dielectric layer of the shielding grid field effect transistor, so that the technical problem that the Cgd (capacitance between a grid electrode and a drain electrode) and the Cgs (capacitance between the grid electrode and a source electrode) of the shielding grid field effect transistor cannot be adjusted in the prior art can be solved.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (14)
1. A method of forming a shielded gate field effect transistor, comprising:
depositing a first dielectric layer on the inner wall of a groove formed in the conductive epitaxial layer, wherein the first dielectric layer is of a groove-shaped structure, and filling a shielding grid in the groove of the first dielectric layer and etching back the shielding grid;
etching back the first dielectric layer to enable the top of the first dielectric layer to be flush with the top of the shielding grid;
filling a second dielectric layer to a first target thickness on the tops of the first dielectric layer and the shielding gate, wherein two sides of the second dielectric layer are in contact with the inner wall of the groove, and the second dielectric layer and the first dielectric layer are made of different materials;
and growing a grid oxide layer on the upper part of the second dielectric layer and on the inner wall of the groove, and then depositing a grid, wherein the grid is positioned in the middle of the grid oxide layer.
2. The method of claim 1, wherein a cross-sectional area of the shield gate is less than a cross-sectional area of the second dielectric layer.
3. The method of claim 1, wherein the second dielectric layer is comprised of a material having a dielectric constant and the first dielectric layer is comprised of an insulating material.
4. The method of claim 3, wherein the target thickness of the second dielectric layer is adjusted based on a capacitance level of the transistor and a dielectric constant of a material comprising the second dielectric layer.
5. A method of forming a shielded gate field effect transistor as claimed in claim 3The second dielectric layer is composed of one or two of SiN and SiLK, and the first dielectric layer is SiO2。
6. The method of forming a shielded gate field effect transistor according to claim 1 wherein said gate oxide layer has a thickness less than a thickness of said first dielectric layer.
7. A method of forming a shielded gate field effect transistor, comprising:
depositing a first dielectric layer on the inner wall of a groove formed in the conductive epitaxial layer, wherein the first dielectric layer is of a groove-shaped structure, and filling a shielding grid in the groove of the first dielectric layer and etching back the shielding grid;
filling a second dielectric layer to a second target thickness on the top of the shielding grid, and then etching back the first dielectric layer to enable the top of the first dielectric layer to be flush with the top of the shielding grid, wherein the second dielectric layer and the first dielectric layer are made of different materials;
carrying out back etching on the second dielectric layer to enable the top of the second dielectric layer to be higher than or lower than the first dielectric layer after back etching, or to enable the top of the second dielectric layer to be flush with the first dielectric layer after back etching;
and growing a grid oxide layer on the upper part of the second dielectric layer and on the inner wall of the groove, and then depositing a grid, wherein the grid is positioned in the middle of the grid oxide layer.
8. The method of claim 7, wherein the shield gate has the same cross-sectional area as the second dielectric layer.
9. The method of claim 7, wherein the second dielectric layer is comprised of a material having a dielectric constant and the first dielectric layer is comprised of an insulating material.
10. The method of claim 7, wherein the target thickness of the second dielectric layer is adjusted based on a capacitance level of the transistor and a dielectric constant of the second dielectric layer.
11. The method of claim 7, wherein the second dielectric layer is a mixture of SiN and SiLK, and the first dielectric layer is SiO2。
12. The method of forming a shielded gate field effect transistor according to claim 7 wherein said gate oxide layer has a thickness less than a thickness of said first dielectric layer.
13. A shielded gate field effect transistor formed by the method of any one of claims 1 to 6.
14. A shielded gate field effect transistor produced by the method of any one of claims 7 to 12.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111524976A (en) * | 2020-04-28 | 2020-08-11 | 电子科技大学 | Power MOS device with low grid charge and manufacturing method thereof |
| CN111599866A (en) * | 2020-05-29 | 2020-08-28 | 电子科技大学 | Low-grid charge power MOSFET device with U-shaped separation grid and manufacturing method thereof |
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