CN105702736A - A shield grid oxide layer of a shield grid-deep groove MOSFET and a formation method thereof - Google Patents
A shield grid oxide layer of a shield grid-deep groove MOSFET and a formation method thereof Download PDFInfo
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- CN105702736A CN105702736A CN201610064114.1A CN201610064114A CN105702736A CN 105702736 A CN105702736 A CN 105702736A CN 201610064114 A CN201610064114 A CN 201610064114A CN 105702736 A CN105702736 A CN 105702736A
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 230000015572 biosynthetic process Effects 0.000 title abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 71
- 229920005591 polysilicon Polymers 0.000 claims abstract description 67
- 238000000151 deposition Methods 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000006396 nitration reaction Methods 0.000 claims description 40
- 238000005137 deposition process Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 238000005516 engineering process Methods 0.000 abstract description 6
- 238000002955 isolation Methods 0.000 abstract description 4
- 230000008021 deposition Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 119
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 17
- 229910052710 silicon Inorganic materials 0.000 description 17
- 239000010703 silicon Substances 0.000 description 17
- 238000010586 diagram Methods 0.000 description 7
- 238000001039 wet etching Methods 0.000 description 7
- 238000000407 epitaxy Methods 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 230000001590 oxidative effect Effects 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
Abstract
The invention discloses a shield grid oxide layer of a shield grid-deep groove MOSFET and a formation method thereof. The method comprises the following steps: 1, grooves are formed in an epitaxial layer through etching; first oxide layers form on the bottom surfaces and the sidewall surfaces of the grooves through adoption thermooxidizing growth technology; 2, nitridation layers form on surfaces of the first oxide layers; 3, deposited polysilicon layers form on the surfaces of the nitridation layers through adoption of polysilicon deposition technology; 4, thermooxidizing is carried out, and the deposited polysilicon layers are all oxidized to form second oxides; and the first oxide layers, the nitridation layers and the second oxide layers together form a shield grid oxide layer. According to the invention, an existing mode of directly depositing oxide layers on nitridation layers through SACVD is replaced by a mode of depositing polysilicon on the nitridation layers and carrying out thermooxidizing on the polysilicon, so that the thickness of each shield grid oxide layer used for isolation between shield grids and the groove sidewalls and between the shield grids and the groove bottom portions is ensured; technology conditions are simplified; the production cost is reduced; and the production power is raised.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing process field, particularly to the shield grid oxide layer being positioned at trenched side-wall in a kind of shield grid-deep trench MOSFET, further relate to a kind of shield grid-deep trench MOSFET is positioned at the forming method of the shield grid oxide layer of trenched side-wall。
Background technology
As shown in Figure 1, it is existing there is shield grid (ShieldGateTrench, be called for short SGT) structural representation of trench gate mosfet of structure, illustrate for N-type device, described in there is shielded gate structures the cellular construction of trench gate mosfet include:
N-type silicon epitaxy layer 101, is formed on silicon substrate, and silicon substrate is heavy doping and is formed with drain electrode overleaf, and silicon epitaxy layer 101 is light doping, is used for forming drift region；
P-well 102, is formed on the surface of silicon epitaxy layer 101；
Groove enters in silicon epitaxy layer 101 through p-well 102, groove has polysilicon gate 103a and polysilicon shield grid 104a, the sidewall surfaces isolation of polysilicon gate 103a and groove has gate oxide (gateoxide) 105a, between polysilicon gate 103a and polysilicon shield grid 104a, isolation has polysilicon interlevel oxide layer (interpolyoxide) 106a, and the sidewall surfaces of polysilicon shield grid 104a and groove and bottom directly isolate shield grid oxide layer (shieldingoxide) 107a；
Source region 108 is formed in p-well 102, polysilicon gate 103a covers source region 108 and p-well 102 from the side, the degree of depth of polysilicon gate 103a is more than the junction depth of p-well 102, and the surface of the p-well 102 covered by polysilicon gate 103a side is for forming the raceway groove connecting source region 108 and bottom silicon epitaxial layer 101；
Source contact openings 109 is through source region 108 and contacts with source region 108 and p-well 102 simultaneously, shield grid contact hole 110a contacts through the oxide layer at polysilicon shield grid 104a top with polysilicon shield grid 104a, source contact openings 109 and be filled with metal in shield grid contact hole 110a；
Being formed with contact hole in interlayer film 111 and draw source electrode and grid respectively, wherein source contact openings 109 and shield grid contact hole 110a are all connected to source electrode。
Illustrate for the trench gate structure comprising middle pressure SGT (80V～200V), its gash depth is typically in 4～6 microns, the thickness of shield grid oxide layer is right at 5000 Izods, and the method forming shield grid oxide layer in this trench gate structure with shield grid comprises the steps:
1st step, forms groove 2 on epitaxial layer 1, and as shown in Figure 2 A, the etching depth of groove 2 is 4 microns～6 microns；
2nd step, thermal oxide forms oxide layer 3, and as shown in Figure 2 B, the thickness of described oxide layer 3 is 4000 angstroms～6000 angstroms；
3rd step, deposits the first polysilicon layer 4 and is filled up completely with by groove 2, and the first polysilicon layer 4 is carried out dry back carve to silicon face keep flush, as shown in Figure 2 C；
4th step, carries out second time and is etched to groove 2 inside the first polysilicon layer 4, and as shown in Figure 2 D, the first polysilicon layer 4 being positioned at groove 2 forms shield grid；
5th step, carries out wet etching, by the oxide layer 3 of silicon face and formed at trenched side-wall and be positioned at the oxide layer 3 above shield grid and etch totally, as shown in Figure 2 E, in groove, the region of etching is used for forming polysilicon gate, and wherein width is 2 microns, and the degree of depth is 1.5 microns；
6th step, by HDP (high-density plasma)+SACVD (secondary aumospheric pressure cvd), groove is fully filled with oxide layer, as shown in Figure 2 F, owing to width and the degree of depth of groove are bigger, so in order to ensure the technology stability of subsequent CMP (chemically mechanical polishing), it is necessary to fill 15500 angstroms by HDP and groove could be filled up and ensure that enough thickness is to carry out follow-up CMP processing procedure by SACVD filling 10000 angstroms；
7th step, carries out CMP (chemically mechanical polishing) processing procedure and the oxide layer on surface is polished, and makes the oxidated layer thickness of silicon face be maintained at 2000 angstroms～3000 angstroms, as shown in Figure 2 G；
8th step, carries out wet method and returns quarter to certain depth oxide layer, and the oxide layer above shield grid polysilicon forms polysilicon interlevel oxide layer 5, and the oxide layer between shield grid and trenched side-wall and channel bottom forms shield grid oxide layer 3, as illustrated in figure 2h；
9th step, forms gate oxide by thermal oxide；
10th step, deposits the second polysilicon, is filled up completely with by groove, and the second polysilicon is carried out dry back carve to silicon face keep flush, formed polysilicon gate。
Costly due to HDP technique; therefore mostly form polysilicon interlevel oxide layer by thermal oxide at present; one way in which is that gate oxide 6 has aoxidized together with polysilicon interlevel oxide layer 5; because the thickness requirement of polysilicon interlevel oxide layer 5 is more than 2000 angstroms; form, with silicon face, the oxidizing condition that oxide thickness differs greatly at polysilicon so needing to adopt; ensure that oxide thickness above the first polysilicon layer 4 ratio with the oxide thickness of the silicon face of trenched side-wall is at more than 3:1; as it is shown on figure 3, and this oxidizing condition is protected by existing patent limitation。
Except the method that above-mentioned gate oxide aoxidizes together with polysilicon interlevel oxide layer; in order to the oxidation of follow-up use ordinary hot forms polysilicon interlevel oxide layer to avoid the patent protection oxidizing condition that device shown in Fig. 3 adopts; also has another method; namely by depositing a nitration case 7 in the oxide layer 3 forming shield grid oxide layer; as shown in Figure 4 A; then polysilicon interlevel oxide layer 5 is formed when carrying out the oxidation of shield grid; as shown in Figure 4 B, thus can pass through common thermal oxidizing conditions oxidation and form sufficiently thick polysilicon interlevel oxide layer 5。It is right that the gross thickness that oxide layer 3 and nitration case 7 add up is about 5000 Izods, the wherein thickness of oxide layer 3 3500 angstroms～4000 angstroms, the thickness of nitration case 7 1000 angstroms～1500 angstroms。After aoxidizing formation polysilicon interlevel oxide layer 5 on the polysilicon, respectively nitration case 7 and oxide layer 3 are carried out wet etching, because the character of the isotropic of wet etching, nitration case 7 and oxide layer 3 all can form the pattern of oblique triangle after etching, affect device property, as shown in Fig. 4 C, Fig. 4 D。
So further, first pass through first step thermal oxidation technology in groove, directly form the gate oxide 6 of desired thickness, then on gate oxide 6, deposit nitration case 7 again, as shown in Figure 5A, so can realize gate oxide 6 one-shot forming, then pass through SACVD deposit mode to supply the gross thickness of required shield grid oxide layer, it is desirable to right at 5000 Izods。And the thickness of gate oxide 6 that preceding method is formed is approximately 1000 angstroms～1500 angstroms with the thickness sum of nitration case 7, oxide-film uses directly as gate oxide, follow-up without using wet etching。The thickness of nitride film is also relatively thin, forms chamfering less after subsequent wet etching。Final pattern is comparatively excellent, and as shown in Figure 5 B, general is utilize the SACVD oxide layer 8 depositing 9000 angstroms at present, and this process costs is higher and needs to use specific condition, and therefore yield is non-normally low。
Summary of the invention
The technical problem to be solved in the present invention is to provide shield grid oxide layer of a kind of shield grid-deep trench MOSFET and forming method thereof, and process conditions are simple, it is easy to accomplish, and production cost can be reduced, improve production efficiency。
For solving above-mentioned technical problem, the shield grid oxide layer of shield grid-deep trench MOSFET provided by the invention, including the first oxide layer, nitration case and the second oxide layer, described first oxide layer is formed in the lower surface of groove and sidewall surfaces, described nitration case is formed on the surface of described first oxide layer, described second oxide layer is formed on the surface of described nitration case, and described second oxide layer is formed by polysilicon deposit thermal oxide。
Further improving is that the thickness of described polysilicon is 1000 angstroms～2500 angstroms。
Further improving is that the degree of depth of described groove is 4 microns～6 microns, and Sidewall angles is 86.5 °～88.5 °。
Further improving is that the thickness of described first oxide layer is identical with the thickness of gate oxide in MOSFET, and the thickness of described nitration case is 500 angstroms～1500 angstroms。
For solving above-mentioned technical problem, the method that in shield grid-deep trench MOSFET provided by the invention, trenched side-wall forms shield grid oxide layer, comprise the steps:
1st step, on epitaxial layer, etching is formed with groove, adopts thermal oxide growth technique to form the first oxide layer in lower surface and the sidewall surfaces of described groove；
2nd step, forms nitration case on the surface of described first oxide layer；
3rd step, adopts polycrystalline silicon deposition process to form depositing polysilicon layer on the surface of described nitration case；
4th step, carries out thermal oxide, and described depositing polysilicon layer is fully oxidized to the second oxide layer, and described first oxide layer, nitration case and the second oxide layer are collectively forming shield grid oxide layer。
Further improving is that the thickness of described depositing polysilicon layer is 1000 angstroms～2500 angstroms。
Further improving is that the degree of depth of described groove is 4 microns～6 microns, and Sidewall angles is 86.5 °～88.5 °。
Further improving is that the thickness of described first oxide layer is identical with the thickness of gate oxide in MOSFET, and the thickness of described nitration case is 500 angstroms～1500 angstroms。
The present invention has the method forming shield grid oxide layer at trenched side-wall in shield grid-deep trench MOSFET, by depositing polysilicon on nitration case and polysilicon is carried out the mode of thermal oxide to form the shield grid oxide layer meeting thickness requirement, instead of the existing mode either directly through SACVD deposited oxide layer on nitration case, not only can ensure that between shield grid and trenched side-wall and channel bottom the thickness of shield grid oxide layer for isolating, and simplify process conditions, reduce production cost, improve production capacity。
Accompanying drawing explanation
Fig. 1 is the structural representation of the existing trench gate mosfet with shielded gate structures；
Fig. 2 A to Fig. 2 H is the existing MOSFET with the shield grid-deep trench device architecture schematic diagram forming in each step of shield grid oxide layer in the trench；
Fig. 3 is the device architecture schematic diagram that thermal oxide of existing employing forms polysilicon interlevel oxide layer and gate oxide；
Fig. 4 A to Fig. 4 D is the existing device architecture schematic diagram adopting deposit nitration case+ordinary hot oxidation to form polysilicon interlevel oxide layer；
Fig. 5 A to Fig. 5 B is the device architecture schematic diagram that existing employing gate oxide one-shot forming+nitration case deposit+deposited oxide layer forms shield grid oxide layer；
Fig. 6 A to Fig. 6 B is the device architecture schematic diagram that the present invention forms shield grid oxide layer；
Fig. 6 C to Fig. 6 G is that the present invention forms shield grid and the device architecture schematic diagram of each step of polysilicon gate；
Fig. 7 is the method flow diagram that the present invention forms shield grid oxide layer。
Detailed description of the invention
Below in conjunction with accompanying drawing, the present invention is further detailed explanation with detailed description of the invention。
The shield grid oxide layer of shield grid-deep trench MOSFET provided by the invention, as shown in Figure 6B, including the first oxide layer (i.e. the gate oxide 6 of MOSFET), nitration case 7 and the second oxide layer 8, described first oxide layer is formed in the lower surface of groove and sidewall surfaces, described nitration case 7 forms the surface in described first oxide layer, described second oxide layer 8 is formed on the surface of described nitration case 7, and described second oxide layer 8 is formed by polysilicon deposit thermal oxide。The ONO layer formed by described first oxide layer (i.e. gate oxide 6), described nitration case 7 and described second oxide layer 8 superposition in the present invention is as the shield grid oxide layer (ShieldingOxide) of directly isolation between lower surface and the sidewall surfaces of shield grid in MOSFET and groove。Preferably selection is, the thickness of described polysilicon is 1000 angstroms～2500 angstroms, the thickness of described first oxide layer is identical with the thickness of gate oxide in MOSFET, and the thickness of described first oxide layer is 400 angstroms～1000 angstroms, and the thickness of described nitration case 7 is 500 angstroms～1000 angstroms。
Described groove is formed in epitaxial layer such as silicon epitaxy layer 1, it is advantageous to the degree of depth being chosen as groove be 4 microns～6 microns, Sidewall angles is 86.5 °～88.5 °。
The forming method of the shield grid oxide layer of trenched side-wall in above-mentioned shield grid-deep trench MOSFET, as it is shown in fig. 7, comprises following steps:
1st step, on epitaxial layer 1, etching is formed with groove, adopts thermal oxide growth technique to form the first oxide layer in lower surface and the sidewall surfaces of described groove；
Preferably it is chosen as, epitaxial layer 1 is silicon epitaxy layer, and the degree of depth of groove is 4 microns～6 microns, and Sidewall angles is 86.5 °～88.5 °, the thickness of the first oxide layer is identical with the thickness of gate oxide in MOSFET 6, and the thickness of described first oxide layer is 400 angstroms～1000 angstroms；
2nd step, forms nitration case 7 on the surface of described first oxide layer (i.e. gate oxide 6)；
Preferably being chosen as, the thickness of described nitration case 7 is 500 angstroms～1500 angstroms；
3rd step, adopts polycrystalline silicon deposition process to form depositing polysilicon layer 9 on the surface of described nitration case 7, as shown in Figure 6A；
Preferably being chosen as, the thickness of described depositing polysilicon layer 9 is 1000 angstroms～2500 angstroms；
4th step, carry out thermal oxide, described depositing polysilicon layer 9 is fully oxidized to the second oxide layer 8, as shown in Figure 6B, described first oxide layer 6, nitration case 7 and the second oxide layer 8 are collectively forming shield grid oxide layer, and this shield grid oxide layer is as the sealing coat between the shield grid being subsequently formed and trench bottom surfaces and sidewall surfaces。
Carry out the formation of shield grid and polysilicon gate after this, comprise the steps:
5th step, deposition gate polysilicon 10, first returns with dry etching and is carved into silicon face, then return with dry etching and carve to groove, as shown in Figure 6 C；
6th step, aoxidizes on shield grid polysilicon 10, forms polysilicon interlevel oxide layer 5, as shown in Figure 6 D；
7th step, by wet etching, the second layer oxide layer 8 that depositing polysilicon layer 9 aoxidizes formation is all etched to nitration case 7, as illustrated in fig. 6e；
8th step, by wet etching, will be located in the nitration case 7 on polysilicon interlevel oxide layer 5 and all removes, as fig 6 f illustrates；
9th step, deposits grid polycrystalline silicon 11, and by dry etching to silicon face, forms polysilicon gate, as shown in Figure 6 G。
After this, conventionally technique forms p-well, source region, source contact hole, shield grid contact hole etc., and these are all routine techniquess to those skilled in the art, are not described in detail at this。
The present invention has the method forming shield grid oxide layer at trenched side-wall in shield grid-deep trench MOSFET, by depositing polysilicon on nitration case and polysilicon is carried out the mode of thermal oxide to form the shield grid oxide layer meeting thickness requirement, instead of the existing mode either directly through SACVD deposited oxide layer on nitration case, not only can ensure that between shield grid and trenched side-wall and channel bottom the thickness of shield grid oxide layer for isolating, and simplify process conditions, reduce production cost, improve production capacity。
Above by specific embodiment, the present invention is described in detail, but these have not been construed as limiting the invention。Without departing from the principles of the present invention, those skilled in the art can make many deformation and improvement, and these also should be regarded as protection scope of the present invention。
Claims (8)
1. the shield grid oxide layer of shield grid-deep trench MOSFET, it is characterized in that, including the first oxide layer, nitration case and the second oxide layer, described first oxide layer is formed in the lower surface of groove and sidewall surfaces, described nitration case is formed on the surface of described first oxide layer, described second oxide layer is formed on the surface of described nitration case, and described second oxide layer is formed by polysilicon deposit thermal oxide。
2. the shield grid oxide layer of shield grid-deep trench MOSFET according to claim 1, it is characterised in that the thickness of described polysilicon is 1000 angstroms～2500 angstroms。
3. the shield grid oxide layer of shield grid-deep trench MOSFET according to claim 1, it is characterised in that the degree of depth of described groove is 4 microns～6 microns, Sidewall angles is 86.5 °～88.5 °。
4. the shield grid oxide layer of shield grid-deep trench MOSFET according to claim 1, it is characterised in that the thickness of described first oxide layer is identical with the thickness of gate oxide in MOSFET, the thickness of described nitration case is 500 angstroms～1500 angstroms。
5. the method that in shield grid-deep trench MOSFET, trenched side-wall forms shield grid oxide layer, it is characterised in that comprise the steps:
1st step, on epitaxial layer, etching is formed with groove, adopts thermal oxide growth technique to form the first oxide layer in lower surface and the sidewall surfaces of described groove；
2nd step, forms nitration case on the surface of described first oxide layer；
3rd step, adopts polycrystalline silicon deposition process to form depositing polysilicon layer on the surface of described nitration case；
4th step, carries out thermal oxide, and described depositing polysilicon layer is fully oxidized to the second oxide layer, and described first oxide layer, nitration case and the second oxide layer are collectively forming shield grid oxide layer。
6. the method that in shield grid-deep trench MOSFET according to claim 5, trenched side-wall forms shield grid oxide layer, it is characterised in that the thickness of described depositing polysilicon layer is 1000 angstroms～2500 angstroms。
7. the method that in shield grid-deep trench MOSFET according to claim 5, trenched side-wall forms shield grid oxide layer, it is characterised in that the degree of depth of described groove is 4 microns～6 microns, and Sidewall angles is 86.5 °～88.5 °。
8. the method that in shield grid-deep trench MOSFET according to claim 5, trenched side-wall forms shield grid oxide layer, it is characterized in that, the thickness of described first oxide layer is identical with the thickness of gate oxide in MOSFET, and the thickness of described nitration case is 500 angstroms～1500 angstroms。
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111446157A (en) * | 2020-04-07 | 2020-07-24 | 中芯集成电路制造(绍兴)有限公司 | Shielded gate field effect transistor and method of forming the same |
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| CN112133637A (en) * | 2020-11-30 | 2020-12-25 | 中芯集成电路制造(绍兴)有限公司 | Method for manufacturing semiconductor device with shielded gate trench |
| CN113035715A (en) * | 2019-12-25 | 2021-06-25 | 华润微电子（重庆）有限公司 | Shielded gate trench field effect transistor and method of making same |
| CN113066860A (en) * | 2021-02-10 | 2021-07-02 | 华为技术有限公司 | Manufacturing method of dielectric layer of shielded gate field effect transistor and related product |
| CN113644028A (en) * | 2021-08-11 | 2021-11-12 | 重庆万国半导体科技有限公司 | Split gate power device and manufacturing method thereof |
| CN113782446A (en) * | 2021-09-30 | 2021-12-10 | 深圳市芯电元科技有限公司 | Manufacturing method of shielded gate MOSFET |
| CN113808949A (en) * | 2021-09-30 | 2021-12-17 | 深圳市芯电元科技有限公司 | Manufacturing method of shielded gate trench MOSFET |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010008788A1 (en) * | 1999-09-14 | 2001-07-19 | Fwu-Iuan Hshieh | Trench DMOS transistor having reduced punch-through |
| CN101785091A (en) * | 2007-08-21 | 2010-07-21 | 飞兆半导体公司 | Method and structure for shielded gate trench FET |
| US20110070708A1 (en) * | 2009-09-21 | 2011-03-24 | Force Mos Technology Co. Ltd. | Method for making trench MOSFET with shallow trench structures |
| CN104541374A (en) * | 2012-04-30 | 2015-04-22 | 维西埃-硅化物公司 | Semiconductor device |
-
2016
- 2016-01-29 CN CN201610064114.1A patent/CN105702736B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010008788A1 (en) * | 1999-09-14 | 2001-07-19 | Fwu-Iuan Hshieh | Trench DMOS transistor having reduced punch-through |
| CN101785091A (en) * | 2007-08-21 | 2010-07-21 | 飞兆半导体公司 | Method and structure for shielded gate trench FET |
| US20110070708A1 (en) * | 2009-09-21 | 2011-03-24 | Force Mos Technology Co. Ltd. | Method for making trench MOSFET with shallow trench structures |
| CN104541374A (en) * | 2012-04-30 | 2015-04-22 | 维西埃-硅化物公司 | Semiconductor device |
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| CN113035715A (en) * | 2019-12-25 | 2021-06-25 | 华润微电子（重庆）有限公司 | Shielded gate trench field effect transistor and method of making same |
| CN111446157A (en) * | 2020-04-07 | 2020-07-24 | 中芯集成电路制造(绍兴)有限公司 | Shielded gate field effect transistor and method of forming the same |
| CN111785618A (en) * | 2020-06-28 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of trench gate structure |
| CN111883592B (en) * | 2020-08-06 | 2023-08-22 | 上海华虹宏力半导体制造有限公司 | Shielding gate trench power device and manufacturing method thereof |
| CN111883592A (en) * | 2020-08-06 | 2020-11-03 | 上海华虹宏力半导体制造有限公司 | Shielded gate trench power device and method of making same |
| CN112133637A (en) * | 2020-11-30 | 2020-12-25 | 中芯集成电路制造(绍兴)有限公司 | Method for manufacturing semiconductor device with shielded gate trench |
| CN112133637B (en) * | 2020-11-30 | 2021-02-12 | 中芯集成电路制造(绍兴)有限公司 | Method for manufacturing semiconductor device with shielded gate trench |
| CN113066860A (en) * | 2021-02-10 | 2021-07-02 | 华为技术有限公司 | Manufacturing method of dielectric layer of shielded gate field effect transistor and related product |
| WO2023016305A1 (en) * | 2021-08-11 | 2023-02-16 | 重庆万国半导体科技有限公司 | Separation gate power device and manufacturing method therefor |
| CN113644028A (en) * | 2021-08-11 | 2021-11-12 | 重庆万国半导体科技有限公司 | Split gate power device and manufacturing method thereof |
| CN113644028B (en) * | 2021-08-11 | 2023-10-03 | 重庆万国半导体科技有限公司 | Split gate power device and manufacturing method thereof |
| CN113782446A (en) * | 2021-09-30 | 2021-12-10 | 深圳市芯电元科技有限公司 | Manufacturing method of shielded gate MOSFET |
| CN113808949A (en) * | 2021-09-30 | 2021-12-17 | 深圳市芯电元科技有限公司 | Manufacturing method of shielded gate trench MOSFET |
| CN114023812A (en) * | 2021-10-20 | 2022-02-08 | 上海华虹宏力半导体制造有限公司 | Shielded gate trench type MOSFET device and manufacturing method thereof |
| CN114023812B (en) * | 2021-10-20 | 2023-08-22 | 上海华虹宏力半导体制造有限公司 | Shielded gate trench type MOSFET device and manufacturing method thereof |
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