CN109767986B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN109767986B CN109767986B CN201910069243.3A CN201910069243A CN109767986B CN 109767986 B CN109767986 B CN 109767986B CN 201910069243 A CN201910069243 A CN 201910069243A CN 109767986 B CN109767986 B CN 109767986B
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Abstract
The invention provides a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductors. In the process of manufacturing the grid electrode, a part of the electrode material is removed firstly, so that an isolation groove is formed between the electrode material reserved in the electrode groove and the first isolation layer, and meanwhile, a second isolation layer can be manufactured in the isolation groove. So, the sum of the thickness of first isolation layer and second isolation layer can obviously be greater than the thickness of first oxide layer to make the total quality of the isolation layer between first electrode and the field plate obtain improving, make semiconductor device's gate source maximum voltage's extreme value higher, can solve the IGSS HTGB failure problem of device simultaneously, can improve the tightness between the electrode, improve the reliability of device, the preparation flow of device is simple, the thickness of isolation layer is controllable, the cost of manufacture is lower.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.
Background
In some application scenarios, certain properties of the semiconductor device may have a certain influence on practical use. For example, for some field effect transistors, the limit value of the maximum gate-source voltage of the device is required to be higher in some application scenarios, but in the existing field effect transistors, the factors restricting the performance of the device are many, so that some devices cannot adapt to some application scenarios. For example, in prior devices, if during the growth of the gate oxide layer, the isolation oxide layer is formed at the same time. Although the isolation oxide is slightly thicker than the gate oxide (polysilicon oxidizes faster than single crystal silicon, the thickness of the first oxide is approximately between 200A and 900A, which is limited by the designed threshold voltage)) However, the isolation oxide layer formed of polysilicon is inferior in quality to the gate oxide layer formed of single crystal silicon. Typically, the isolation oxide layer between the gate polysilicon and the field plate polysilicon is weak. Device VGSSIs limited by a limit value of IGSSthe/HTGB failure causes a lot of troubles.
If the isolation oxide layer 36 is formed by the method described in U.S. Pat. No. 7098500B2, as shown in fig. 1a, the isolation oxide layer can be formed by High Density Plasma Chemical Vapor Deposition (HDPCVD) to fill the trench, followed by a chemical mechanical polishing process and then an oxide etch back process. Although the isolation oxide layer 36 can be made thicker, the process is complicated and costly to manufacture, and it is difficult to control the thickness of the isolation oxide layer 36 during the manufacturing process, which depends on the remaining thickness of the polysilicon 38 and the termination point of the etching of the isolation oxide layer 36 itself. Meanwhile, the manufacturing process is difficult to control the position of the bottom of the gate polysilicon 34, and the influence factors are similar to the above. If the bottom of the gate polysilicon 34 is shallower than the bottom of the P-well 16, the device will be hard to turn on. If the bottom of the gate polysilicon 34 is too deep, an undesirably large Miller Capacitance (Miller Capacitance) will result.
Disclosure of Invention
The present invention provides a semiconductor device and a method for manufacturing the same.
The technical scheme provided by the invention is as follows:
a method of manufacturing a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a first semiconductor layer and a second semiconductor layer positioned on one side of the first semiconductor layer, the first semiconductor layer is provided with a first conduction type, the second semiconductor layer is provided with a second conduction type, and the first conduction type and the second conduction type are the same or different;
forming a trench in the second semiconductor layer;
forming a field oxide layer and a field plate in the groove, wherein the field oxide layer covers the bottom of the groove and a part of the side wall of the groove, and a gap is formed between the field plate and the part of the second semiconductor layer, which is far away from one side of the first semiconductor layer;
manufacturing a dielectric material on the side wall of the gap, the surface of the field plate far away from the first semiconductor layer and the surface of the second semiconductor layer far away from the first semiconductor layer so as to form an electrode groove for depositing an electrode material between the field plate and the second semiconductor layer;
depositing an electrode material in the electrode groove to manufacture a first electrode, forming a first isolation layer by using a dielectric material manufactured on the surface of a field plate of the electrode groove, and forming a first oxidation layer by using a dielectric material manufactured on the surface of a second semiconductor layer of the electrode groove;
removing part of the electrode material close to the first isolation layer to form an isolation trench between the electrode material remained in the electrode groove and the first isolation layer, wherein the isolation trench is used for manufacturing a second isolation layer;
manufacturing and forming the second isolation layer in the isolation groove;
manufacturing a first conductive type region and a second conductive type region in the substrate;
manufacturing a dielectric layer covering the first electrode on one side of the substrate; and
and manufacturing a second electrode and a third electrode on two sides of the substrate.
Furthermore, the electrode grooves comprise two electrode grooves positioned on two sides of the field plate, the electrode material is filled in each electrode groove, and the electrode material covers the dielectric material of the second semiconductor layer far away from the surface of the first semiconductor layer; wherein the step of removing a portion of the electrode material adjacent to the first isolation layer comprises:
removing a part of the electrode material in each electrode groove close to the first isolating layer;
removing a part of the electrode material on one side of the second semiconductor layer far away from the first semiconductor layer, and reserving a part of the electrode material close to the electrode groove in the electrode material on one side of the second semiconductor layer far away from the first semiconductor layer;
and the gap between the electrode material reserved in the electrode groove and the first isolation layer forms the isolation groove.
Further, the electrode grooves comprise two electrode grooves positioned on two sides of the field plate, and the electrode material is filled in each electrode groove; wherein the step of removing a portion of the electrode material adjacent to the first isolation layer comprises:
and removing part of the electrode material in each electrode groove, which is close to the first isolation layer, wherein a gap between the electrode material reserved in the electrode groove and the first isolation layer forms the isolation groove.
Further, the isolation trench includes two isolation trenches located at both sides of the field plate; the step of forming the second isolation layer within the isolation trench includes:
filling an isolation material in each isolation trench, wherein the isolation material between the electrode material reserved in the electrode groove and the first isolation layer forms the second isolation layer;
the isolating material also covers the electrode material remained in the electrode groove and the dielectric material on the surface of the second semiconductor layer far away from the first semiconductor layer.
Further, the isolation trench includes two isolation trenches located at both sides of the field plate; the step of forming the second isolation layer within the isolation trench includes:
and in the thermal oxidation growth condition, growing the electrode material reserved in the electrode groove to form a thermal growth oxide layer, and filling the isolation groove with the thermal growth oxide layer to form the second isolation layer.
Further, the first conductive type is N-type or P-type, and the second conductive type is N-type or P-type.
The present invention also provides a semiconductor device comprising:
a substrate including a first semiconductor layer having a first conductive type and a second semiconductor layer having a second conductive type, the first conductive type being the same as or different from the second conductive type;
a field oxide layer and a field plate within the second semiconductor layer, the field oxide layer being between the field plate and the second semiconductor layer;
the first electrode is positioned on two sides of the field plate, a first isolation layer and a second isolation layer are manufactured between the first electrode and the field plate, a first oxidation layer is manufactured between the first electrode and the second semiconductor layer, and the sum of the thicknesses of the first isolation layer and the second isolation layer is larger than the thickness of the first oxidation layer; the second isolation layer is obtained by growing the first electrode in a thermal oxygen growth environment on the basis of growth, or an isolation groove is formed between the reserved electrode material and the first isolation layer after part of the first electrode is removed, and the second isolation layer is manufactured in the isolation groove;
a dielectric layer covering the first electrode;
a first conductive type region and a second conductive type region formed in the substrate; and
and the second electrode and the third electrode are manufactured on two sides of the substrate.
Further, the first electrode is disposed between the field plate and the second semiconductor layer.
Further, the first electrode includes a first portion provided between the field plate and the second semiconductor layer, and a second portion provided on a side of the second semiconductor layer away from the first semiconductor layer.
Further, the first conductive type is N-type or P-type, and the second conductive type is N-type or P-type.
In the embodiment of the application, a part of the electrode material is removed firstly in the process of manufacturing the grid electrode, so that an isolation groove is formed between the electrode material reserved in the electrode groove and the first isolation layer, and meanwhile, the second isolation layer can be manufactured in the isolation groove. In this way, the sum of the thicknesses of the first and second isolation layers may be significantly greater than the thickness of the first oxide layer, thereby enabling the overall quality of the isolation layer between the first electrode and the field plate to be improved. The semiconductor device has a higher gate-source maximum voltage limit value, and can solve the problem of IGSS/HTGB failure of the device, thereby manufacturing a device with a higher gate-source maximum voltage, and improving the robustness between electrodes and the reliability of the device. The manufacturing process of the device is simple, the thickness of the isolation layer is controllable, and the manufacturing cost is low.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1a is a schematic diagram of a device for forming an isolation oxide layer and a gate oxide layer in the prior art.
Fig. 1b is a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.
Fig. 1c is a schematic structural diagram corresponding to step S101 in the method for manufacturing a semiconductor device according to the embodiment of the present application.
Fig. 2 is a schematic structural diagram corresponding to step S102 in the method for manufacturing a semiconductor device according to the embodiment of the present application.
Fig. 3 to fig. 5 are schematic structural diagrams corresponding to step S103 in a method for manufacturing a semiconductor device according to an embodiment of the present application.
Fig. 6 is a schematic structural diagram corresponding to step S104 in the method for manufacturing a semiconductor device according to the embodiment of the present application.
Fig. 7 is a schematic structural diagram corresponding to step S105 in the method for manufacturing a semiconductor device according to the embodiment of the present application.
Fig. 8 is a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure after a first isolation layer and a first oxide layer are formed.
Fig. 9 is a partially enlarged schematic view of a portion I in fig. 8.
Fig. 10 is a schematic diagram of a gate structure in a method for manufacturing a semiconductor device according to an embodiment of the present application.
Fig. 11 is a schematic diagram of another gate structure in a method for manufacturing a semiconductor device according to an embodiment of the present application.
Fig. 12 is a schematic structural diagram corresponding to substep S161 in the method for manufacturing a semiconductor device according to the embodiment of the present application.
Fig. 13 is a schematic structural diagram of a semiconductor device manufacturing method according to an embodiment of the present disclosure after removing a portion of an electrode material.
Fig. 14 is a schematic structural diagram corresponding to sub step S162 and sub step S163 in the method for manufacturing a semiconductor device according to the embodiment of the present application.
Fig. 15 is another schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure after removing a portion of an electrode material.
Fig. 16 and 17 are schematic structural diagrams corresponding to substep S171 in a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.
Fig. 18 is a schematic structural diagram of forming a second isolation layer in the method for manufacturing a semiconductor device according to the embodiment of the present application.
Fig. 19 is a partially enlarged view of portion II in fig. 18.
Fig. 20 is another schematic structural diagram illustrating formation of a second isolation layer in the method for manufacturing a semiconductor device according to the embodiment of the present application.
Fig. 21 is a partially enlarged view of the portion III in fig. 20.
Fig. 22 to 25 are schematic structural diagrams corresponding to the first conductive type region, the second conductive type region, the dielectric layer and the second electrode manufactured in the method for manufacturing a semiconductor device according to the embodiment of the present application.
Fig. 26, 27, and 28 are schematic structural diagrams of a semiconductor device according to an embodiment of the present application.
Icon: 10-a semiconductor device; 101-a substrate; 111-a first semiconductor layer; 112-a second semiconductor layer; 113-a trench; 114-a first conductivity type region; 115-second conductivity type region; 116-a contact hole ion implantation region; 102-field oxide layer; 103-field plate; 131-voids; 104-a dielectric material; 141-electrode slots; 142-a first isolation layer; 143-first oxide layer; 105-an electrode material; 151-first electrode; 106-photoresist; 107-isolation trenches; 108-a second isolation layer; 181-isolating material; 109-a dielectric layer; 110-a second electrode; 120-third electrode.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present invention, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
The embodiment of the application provides a manufacturing method of a semiconductor device, which comprises the following steps as shown in fig. 1 b.
Step S101, as shown in fig. 1c, providing a substrate 101, where the substrate 101 includes a first semiconductor layer 111 and a second semiconductor layer 112 located on one side of the first semiconductor layer 111, the first semiconductor layer 111 has a first conductivity type, the second semiconductor layer 112 has a second conductivity type, and the first conductivity type is the same as or different from the second conductivity type. Both the first semiconductor layer 111 and the second semiconductor layer 112 may be doped N-type, and specifically, the first semiconductor layer 111 may be heavily doped N-type, and the second semiconductor layer 112 may be lightly doped N-type, so that the first semiconductor layer 111 and the second semiconductor layer 112 have the same conductivity type. It is to be understood that the first conductive type is N or P type, and the second conductive type is N or P type. When the first semiconductor layer 111 is doped P-type and the second semiconductor layer 112 is doped N-type, an IGBT can be manufactured and formed, and the conductivity types of the first semiconductor layer 111 and the second semiconductor layer 112 are not limited in this embodiment of the application.
In step S102, as shown in fig. 2, a trench 113 is formed in the second semiconductor layer 112.
The depth of the trench 113 in the second semiconductor layer 112 may be determined according to practical situations, and the specific depth of the trench 113 is not limited in the embodiments of the present application. It is understood that after the trenches 113 are etched in the second semiconductor layer 112, the growth and removal of the sacrificial oxide layer may also be performed.
Step S103, forming a field oxide layer 102 and a field plate 103 in the trench 113, where the field oxide layer 102 covers the bottom and a portion of the sidewall of the trench 113, and a gap 131 is formed between the field plate 103 and the second semiconductor layer 112.
After the trench 113 is formed, the field oxide layer 102 and the field plate 103 can be formed in the trench 113. In detail, as shown in fig. 3, a field oxide layer 102 may be grown in the trench 113, and then as shown in fig. 4, a field plate 103 may be formed in the field oxide layer 102. The field oxide layer 102 is etched back to form the structure shown in fig. 5. It is understood that the field plate 103 may be made of a polysilicon material. After the etching back of the field oxide layer 102 is completed, a gap 131 is formed between the field plate 103 and the second semiconductor layer 112.
Step S104, as shown in fig. 6, a dielectric material 104 is grown on the sidewall and the bottom of the gap 131, the surface of the field plate 103 away from the first semiconductor layer 111, and the surface of the second semiconductor layer 112 away from the first semiconductor layer 111, so as to form an electrode trench 141 for depositing an electrode material 105 between the field plate 103 and the second semiconductor layer 112.
Step S105, as shown in fig. 7, deposits the electrode material 105 in the electrode groove 141.
The electrode material 105 may not only fill the electrode groove 141 but also cover the surface of the second semiconductor layer 112.
For convenience of description, as shown in fig. 8, the dielectric material 104 between the electrode material 105 and the field plate 103 serves as the first isolation layer 142, and the oxide material between the electrode material 105 and the second semiconductor layer 112 serves as the first oxide layer 143. First spacer layer 142 and first oxide layer 143 are formed on dielectric material 104 grown as described above.
In the present embodiment, the first isolation layer 142 is obtained by performing oxide growth on the basis of the field plate 103, and the first oxide layer 143 is obtained by performing oxide growth on the basis of the second semiconductor layer 112. When the field plate 103 is made of polysilicon material and the substrate 101 is made of single crystal silicon material, under the same growth environment, the growth rate of the first isolation layer 142 is faster than that of the first oxide layer 143, so that the thickness D2 of the first isolation layer 142 is greater than the thickness D1 of the first oxide layer 143, as shown in fig. 9. It is understood that the specific thickness of the first oxide layer 143 may be determined according to a threshold voltage when designing a device, and the specific thickness of the first oxide layer 143 is not limited by the embodiments of the present application. Optionally, the thickness of the first oxide layer 143 may be between 200A and 900A.
The semiconductor device in the embodiment of the present application may be a field effect transistor, and the first electrode 151 may be a gate electrode in the field effect transistor. The inventors have found that although the thickness of the first isolation layer 142 between the field plate 103 and the first electrode 151 is thicker than that of the first oxide layer 143, the first isolation layer 142 grown directly on the basis of the field plate 103 is still relatively weak, and the relatively weak first isolation layer 142 may limit the limit value of the gate-source maximum voltage VGSS of the device, and at the same time, may cause the IGSS/HTGB failure problem.
Step S106, removing a portion of the electrode material 105 near the first isolation layer 142, so as to form an isolation trench 107 between the electrode material 105 remaining in the electrode trench 141 and the first isolation layer 142, where the isolation trench 107 is used for manufacturing the second isolation layer 108.
In order to increase the gate-source voltage of the device and solve the problem caused by IGSS/HTGB failure, in the embodiment of the present invention, after filling the electrode material 105 in the electrode trench 141, other structures are not continuously fabricated, but a portion of the electrode material 105 in the electrode trench 141 is removed. In detail, a portion of the electrode material 105 near the first isolation layer 142 may be removed, so that a new isolation trench 107 is formed between the electrode material 105 remaining in the electrode trench 141 and the first isolation layer 142.
In the embodiment of the present application, the number of the electrode grooves 141 is two, and the two electrode grooves are respectively located on two sides of the field plate 103, so that the first electrode 151 can be also two first electrodes 151, thereby forming a split gate structure. In the fabrication of the isolation trenches 107, also the portion of the electrode material 105 in each electrode trench 141 near the first isolation layer 142 is removed, thereby forming two isolation trenches 107 on both sides of the field plate 103.
In detail, the structure of the first electrode 151 may be formed in two cases, one is that, as shown in fig. 10, the first electrode 151 is located only between the field plate 103 and the second semiconductor layer 112; alternatively, as shown in fig. 11, the first electrode 151 includes not only a portion located between the field plate 103 and the second semiconductor layer 112 but also another portion located on the surface of the second semiconductor layer 112 away from the first semiconductor layer 111.
The step of forming the isolation trench 107 is different according to the structure of the first electrode 151. Specifically, in an embodiment, the electrode trenches 141 may further include two electrode trenches 141 located on both sides of the field plate 103, and the electrode material 105 is filled in each of the electrode trenches 141. Wherein the step of removing a portion of the electrode material 105 adjacent to the first isolation layer 142 comprises the following substeps.
In the sub-step S161, a portion of the electrode material 105 in each electrode groove 141 near the first isolation layer 142 is removed, and the isolation trench 107 is formed in a gap between the electrode material 105 remaining in the electrode groove 141 and the first isolation layer 142.
When removing the electrode material 105 shown in fig. 10, a photoresist 106 may be coated on one side of the device, as shown in fig. 12, the photoresist 106 exposes a portion of the electrode material 105 in the electrode trench 141 near the first isolation layer 142, so that a portion of the electrode material 105 near the first isolation layer 142 may be removed in a subsequent step, resulting in the structure shown in fig. 13, and the electrode material 105 remaining in the electrode trench 141 forms the first electrode 151.
In another embodiment, the electrode trenches 141 include two electrode trenches 141 located on two sides of the field plate 103, the electrode material 105 is filled in each electrode trench 141, and the electrode material 105 covers the dielectric material 104 on the surface of the second semiconductor layer 112 away from the first semiconductor layer 111. The step of removing a portion of the electrode material 105 adjacent to the first isolation layer 142 comprises the following sub-steps.
In the substep S162, a portion of the electrode material 105 near the first isolation layer 142 in each electrode groove 141 is removed.
A substep S163 of removing a portion of the electrode material 105 on the side of the second semiconductor layer 112 away from the first semiconductor layer 111, and retaining a portion of the electrode material 105 covering the side of the second semiconductor layer 112 away from the first semiconductor layer 111 close to the electrode groove 141; the gap between the electrode material 105 remaining in the electrode groove 141 and the first isolation layer 142 forms the isolation trench 107.
When the first electrode 151 structure shown in fig. 11 is partially removed, as shown in fig. 14, a photoresist 106 may be coated on a portion of the electrode material 105, and then the electrode material 105 is etched to remove a portion of the electrode material 105, so that an isolation trench 107 is formed between the remaining electrode material 105 and the field plate 103, thereby obtaining the structure shown in fig. 15, where the number of the isolation trenches 107 in this embodiment is two. In the etching process of removing the electrode material 105, in order to avoid etching the dielectric material 104 below the electrode material 105 in the electrode groove 141 as much as possible, an etching method with a high selectivity may be adopted. After the removal of the electrode material 105 is completed, the photoresist 106 may be removed.
In step S107, the second isolation layer 108 is formed in the isolation trench 107.
The method of forming the second isolation layer 108 in the isolation trench 107 may include two methods, one is to fill the isolation material 181 in the isolation trench 107, and the other is to grow the field plate 103 polysilicon and the first electrode 151 polysilicon on the basis of thermal oxidation conditions.
In detail, the second isolation layer 108 may be formed by the following sub-steps.
In the substep S171, an isolation material 181 is filled in each of the isolation trenches 107, and the isolation material 181 between the electrode material 105 remaining in the electrode groove 141 and the first isolation layer 142 forms the second isolation layer 108.
As shown in fig. 16 and 17, while the isolation material 181 fills the isolation trench 107, the isolation material 181 also covers the surface of the electrode material 105 remaining in the electrode trench 141, and the isolation material 181 also covers the dielectric material 104 on the surface of the second semiconductor layer 112 away from the first semiconductor layer 111. The isolation material 181 may form the second isolation layer 108 in the isolation trench 107 by a high density plasma chemical vapor deposition process.
In another embodiment, second isolation layer 108 may be formed by the following sub-steps.
In the sub-step S172, in the thermal oxidation growth condition, the electrode material 105 remaining in the electrode trench 141 and the first isolation layer 142 grow to form a thermally grown oxide layer, and the thermally grown oxide layer fills the isolation trench 107 to form the second isolation layer 108.
The second spacer 108 may be grown under thermal oxide growth conditions on the basis of the first electrode 151 polysilicon and the field plate 103 polysilicon. Alternatively, the second isolation layer 108 may be formed by oxidizing the polysilicon of the first electrode 151 and the polysilicon of the field plate 103 in the P-type second conductive type region 115 push junction process.
The second isolation layer 108 is formed of an isolation material 181 between the first electrode 151 and the first isolation layer 142, and for convenience of illustration, only the second isolation layer 108 is shown in fig. 18 and 20, and the isolation material 181 in other portions is not shown. As shown in fig. 19 and 21, the dielectric material between the first electrode 151 and the field plate 103 includes the first isolation layer 142 and the second isolation layer 108, the sum of the thicknesses of which is D3, the thickness of the first oxide layer 143 is D1, and D3 is significantly greater than D1, it being understood that D3 is also greater than D2 described above in the same device specification.
In step S108, a first conductive type region 114 and a second conductive type region 115 are formed in the substrate 101.
Step S109, a dielectric layer 109 covering the first electrode 151 is formed on one side of the substrate 101.
Step S110, a second electrode 110 and a third electrode 120 are formed on both sides of the substrate 101.
After the fabrication of the second isolation layer 108 is completed, other structures of the device can be fabricated. As shown in fig. 22 to 25, ion implantation may be performed in the second semiconductor layer 112 to form the first conductive type region 114 and the P-type second conductive type region 115, and a junction push-out of the P-type second conductive type region 115 may be performed. In fabricating and forming the MOS structure, the first conductive type region 114 may form a source region of the device, and the second conductive type region 115 may form a well region of the device. Then, a dielectric layer 109 covering the first electrode 151 is formed, and then, the surface of the second semiconductor layer 112 not covered by the dielectric layer 109 may be subjected to photolithography to form a contact hole through which the second electrode 110 contacts the second semiconductor layer 112. Further, ion implantation may be performed at the contact hole portion to form the contact hole ion implantation region 116. Then, a metal material is deposited to form the second electrode 110 and the third electrode 120. In addition, operations such as photoetching and thinning of metal materials can be performed in the manufacturing process, and the application is not limited. When the semiconductor device in the embodiment of the present application is used as a field effect transistor, as described above, the first electrode 151 may be used as a gate of the field effect transistor, and the second electrode 110 and the third electrode 120 located at two sides of the device may be used as a source and a drain of the field effect transistor.
By the above manufacturing method, a field effect transistor having a split gate structure can be manufactured, in such a semiconductor device, two layers of isolation layers, i.e., the first isolation layer 142 and the second isolation layer 108, are provided between the first electrode 151 and the field plate 103, and the second isolation layer 108 can be formed by filling the isolation material 181, or can be formed by thermal oxidation growth on the basis of polysilicon of the first electrode 151 and polysilicon of the field plate 103. In this way, the thickness of the isolation material 181 between the first electrode 151 and the field plate 103 is significantly greater than the thickness of the first oxide layer 143 between the first electrode 151 and the second semiconductor layer 112, and the overall quality of the isolation layer between the first electrode 151 and the field plate 103 is improved by additionally fabricating the second isolation layer 108. The limit value of the maximum gate-source voltage of the semiconductor device is higher, and meanwhile, the problem of IGSS/HTGB failure of the device can be solved.
In summary, in the embodiment of the present invention, during the process of manufacturing the first electrode 151, a portion of the electrode material 105 is removed, so that the isolation trench 107 is formed between the electrode material 105 remaining in the electrode trench 141 and the first isolation layer 142, and the second isolation layer 108 can be further manufactured in the isolation trench 107. As such, the sum of the thicknesses of the first spacer layer 142 and the second spacer layer 108 may be significantly greater than the thickness of the first oxide layer 143, resulting in an improved overall quality of the spacer layer between the first electrode 151 and the field plate 103. The semiconductor device has a higher gate-source maximum voltage limit value, and can solve the problem of IGSS/HTGB failure of the device, thereby manufacturing a device with a higher gate-source maximum voltage, and improving the robustness between electrodes and the reliability of the device. The manufacturing process of the device is simple, the thickness of the isolation layer is controllable, and the manufacturing cost is low.
The embodiment of the present application further provides a semiconductor device 10, which includes a substrate 101, a field oxide layer 102, a field plate 103, a first isolation layer 142, a second isolation layer 108, a first electrode 151, a first oxidation layer 143, a dielectric layer 109, a second electrode 110, and a third electrode 120.
As described above, the substrate 101 includes the first semiconductor layer 111 and the second semiconductor layer 112, and the conductivity type of the second semiconductor layer 112 is the same as the conductivity type of the first semiconductor layer 111. Optionally, the first semiconductor layer 111 is an N-type heavily doped layer, and the second semiconductor layer 112 is an N-type lightly doped layer.
A field oxide layer 102 and a field plate 103 are located within the second semiconductor layer 112, the field oxide layer 102 being located between the field plate 103 and the second semiconductor layer 112.
The first electrode 151 is located on both sides of the field plate 103, a first isolation layer 142 and a second isolation layer 108 are formed between the first electrode 151 and the field plate 103, a first oxide layer 143 is formed between the first electrode 151 and the second semiconductor layer 112, and the sum of the thicknesses of the first isolation layer 142 and the second isolation layer 108 is greater than the thickness of the first oxide layer 143. The second isolation layer 108 is grown in a thermal oxygen growth environment based on the first isolation layer 142 and the first electrode 151, or after a portion of the first electrode 151 is removed, an isolation trench 107 is formed between the remaining electrode material 105 and the first isolation layer 142, and the second isolation layer 108 is formed in the isolation trench 107.
In the embodiment of the present application, the second isolation layer 108 and the first isolation layer 142 are not fabricated at the same time, and the second isolation layer 108 is fabricated after the first isolation layer 142 is fabricated, the electrode groove 141 is filled with the electrode material 105, and a portion of the electrode material 105 is removed. The first isolation layer 142 and the first oxide layer 143 are formed simultaneously, the first isolation layer 142 is formed on the surface of the field plate 103, and the first oxide layer 143 is formed on the surface of the second semiconductor layer 112. As mentioned above, the field plate 103 can be made of polysilicon, so that the thickness of the first isolation layer 142 formed on the basis of the field plate 103 is slightly larger than the thickness of the first oxide layer 143, but is not enough to greatly increase the threshold value of the maximum gate-source voltage of the device.
In the embodiment of the present application, the second isolation layer 108 is separately formed between the first electrode 151 and the first isolation layer 142, so that the thickness of the isolation material 181 between the first electrode 151 and the field plate 103 is thicker than that in the case where only the first isolation layer 142 is disposed, that is, the thickness of the isolation material 181 between the first electrode 151 and the field plate 103 is significantly larger than that of the first oxidation layer 143. Therefore, the limit value of the maximum gate-source voltage VGSS of the device can be obviously improved, and meanwhile, the problem of IGSS/HTGB failure can be solved.
The dielectric layer 109 may cover the first electrode 151, or the dielectric layer 109 may cover the isolation material 181 forming the second isolation layer 108, the substrate 101 is further formed with a second conductive type region 115 and a first conductive type region 114, and the substrate 101 is further formed with a second electrode 110 and a third electrode 120 on two sides.
In the embodiment of the present application, the structure of the first electrode 151 may include two kinds, one is as shown in fig. 26, the first electrode 151 is disposed between the field plate 103 and the second semiconductor layer 112. In another embodiment, as shown in fig. 27, the first electrode 151 includes a first portion disposed between the field plate 103 and the second semiconductor layer 112, and a second portion disposed on a side of the second semiconductor layer 112 away from the first semiconductor layer 111.
The covering position of the photoresist 106 is different when the isolation trench 107 is formed for different first electrode 151 structures, and the practical manufacturing method for different first electrode 151 structures is not limited in the embodiments of the present application.
In another embodiment, as shown in fig. 28, the substrate in the semiconductor device 10 may also be a doped substrate material, and the substrate does not form the first semiconductor layer and the second semiconductor layer.
In the semiconductor device 10 of the embodiment of the present application, two isolation layers are provided between the gate and the field plate, the sum of the thicknesses of the first isolation layer 142 and the second isolation layer 108 is significantly larger than the thickness of the first oxide layer 143, and the second isolation layer is separately formed, so that the overall quality of the isolation layer between the first electrode 151 and the field plate 103 is improved. The limit value of the maximum gate-source voltage of the semiconductor device is higher, the problem of IGSS/HTGB failure of the device can be solved, the firmness between the electrodes is better, larger peak voltage can be borne, and the reliability of the device is higher.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a first semiconductor layer and a second semiconductor layer positioned on one side of the first semiconductor layer, the first semiconductor layer is provided with a first conduction type, the second semiconductor layer is provided with a second conduction type, and the first conduction type and the second conduction type are the same or different;
forming a trench in the second semiconductor layer;
forming a field oxide layer and a field plate in the groove, wherein the field oxide layer covers the bottom of the groove and a part of the side wall of the groove, and a gap is formed between the field plate and the part of the second semiconductor layer, which is far away from one side of the first semiconductor layer;
manufacturing a dielectric material on the side wall of the gap, the surface of the field plate far away from the first semiconductor layer and the surface of the second semiconductor layer far away from the first semiconductor layer so as to form an electrode groove for depositing an electrode material between the field plate and the second semiconductor layer;
depositing an electrode material in the electrode groove to manufacture a first electrode, forming a first isolation layer by using a dielectric material manufactured on the surface of a field plate of the electrode groove, and forming a first oxidation layer by using a dielectric material manufactured on the surface of a second semiconductor layer of the electrode groove;
removing part of the electrode material close to the first isolation layer to form an isolation trench between the electrode material remained in the electrode groove and the first isolation layer, wherein the isolation trench is used for manufacturing a second isolation layer;
manufacturing and forming the second isolation layer in the isolation groove;
manufacturing a first conductive type region and a second conductive type region in the substrate;
manufacturing a dielectric layer covering the first electrode on one side of the substrate; and
and manufacturing a second electrode and a third electrode on two sides of the substrate.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the electrode trenches include two electrode trenches located on both sides of the field plate, the electrode material is filled in each electrode trench, and the electrode material covers the dielectric material of the second semiconductor layer away from the surface of the first semiconductor layer; wherein the step of removing a portion of the electrode material adjacent to the first isolation layer comprises:
removing a part of the electrode material in each electrode groove close to the first isolating layer;
removing a part of the electrode material on one side of the second semiconductor layer far away from the first semiconductor layer, and reserving a part of the electrode material close to the electrode groove in the electrode material on one side of the second semiconductor layer far away from the first semiconductor layer;
and the gap between the electrode material reserved in the electrode groove and the first isolation layer forms the isolation groove.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the electrode trenches include two electrode trenches on both sides of the field plate, the electrode material being filled in each of the electrode trenches; wherein the step of removing a portion of the electrode material adjacent to the first isolation layer comprises:
and removing part of the electrode material in each electrode groove, which is close to the first isolation layer, wherein a gap between the electrode material reserved in the electrode groove and the first isolation layer forms the isolation groove.
4. A method for manufacturing a semiconductor device according to claim 2 or 3, wherein the isolation trench includes two isolation trenches located on both sides of the field plate; the step of forming the second isolation layer within the isolation trench includes:
filling an isolation material in each isolation trench, wherein the isolation material between the electrode material reserved in the electrode groove and the first isolation layer forms the second isolation layer;
the isolating material also covers the electrode material remained in the electrode groove and the dielectric material on the surface of the second semiconductor layer far away from the first semiconductor layer.
5. A method for manufacturing a semiconductor device according to claim 2 or 3, wherein the isolation trench includes two isolation trenches located on both sides of the field plate; the step of forming the second isolation layer within the isolation trench includes:
and in the thermal oxidation growth condition, growing the electrode material reserved in the electrode groove to form a thermal growth oxide layer, and filling the isolation groove with the thermal growth oxide layer to form the second isolation layer.
6. The method for manufacturing a semiconductor device according to claim 1, wherein the first conductivity type is N-type or P-type, and the second conductivity type is N-type or P-type.
7. A semiconductor device, comprising:
a substrate including a first semiconductor layer having a first conductive type and a second semiconductor layer having a second conductive type, the first conductive type being the same as or different from the second conductive type;
a field oxide layer and a field plate within the second semiconductor layer, the field oxide layer being between the field plate and the second semiconductor layer;
the first electrode is positioned on two sides of the field plate, a first isolation layer and a second isolation layer are manufactured between the first electrode and the field plate, a first oxidation layer is manufactured between the first electrode and the second semiconductor layer, and the sum of the thicknesses of the first isolation layer and the second isolation layer is larger than the thickness of the first oxidation layer; the second isolation layer is obtained by growing the first electrode in a thermal oxygen growth environment on the basis of growth, or an isolation groove is formed between the reserved electrode material and the first isolation layer after part of the first electrode is removed, and the second isolation layer is manufactured in the isolation groove;
a dielectric layer covering the first electrode;
a first conductive type region and a second conductive type region formed in the substrate; and
and the second electrode and the third electrode are manufactured on two sides of the substrate.
8. The semiconductor device of claim 7, wherein the first electrode is disposed between the field plate and the second semiconductor layer.
9. The semiconductor device according to claim 7, wherein the first electrode comprises a first portion and a second portion, the first portion being disposed between the field plate and a second semiconductor layer, the second portion being disposed on a side of the second semiconductor layer remote from the first semiconductor layer.
10. The semiconductor device according to any one of claims 7 to 9, wherein the first conductivity type is N-type or P-type, and the second conductivity type is N-type or P-type.
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