CN111244096B - 3D NAND memory device and method of manufacturing the same - Google Patents

3D NAND memory device and method of manufacturing the same Download PDF

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CN111244096B
CN111244096B CN202010228163.0A CN202010228163A CN111244096B CN 111244096 B CN111244096 B CN 111244096B CN 202010228163 A CN202010228163 A CN 202010228163A CN 111244096 B CN111244096 B CN 111244096B
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channel hole
memory device
channel
oxide layer
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CN111244096A (en
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张坤
夏志良
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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Abstract

The invention relates to the field of semiconductor devices, and discloses a 3D NAND memory device and a manufacturing method thereof. The method comprises the following steps: providing a substrate; forming a stacked layer on a substrate, the stacked layer including interlayer insulating layers and dielectric layers alternately arranged; forming a channel hole in the stack layer; oxidizing the outermost part of the dielectric layer, which is adjacent to the channel hole, and the exposed substrate to form a sacrificial oxide layer; removing the sacrificial oxide layer and the partial interlayer insulating layer with the same lateral thickness and adjacent to the channel hole; a first portion of the dielectric layer adjacent to the channel hole is oxidized to form a first oxide layer. The first oxide layer is used as a tunneling barrier layer on the side wall of the channel hole. The method provided by the invention repairs the damage of the side wall of the channel hole and the exposed damage of the substrate surface in the etching process of the channel hole, and reduces the key dimension of the channel.

Description

3D NAND memory device and method of manufacturing the same
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a 3D NAND memory device and a manufacturing method thereof.
Background
With the development of the planar flash memory, the manufacturing process of the semiconductor has been greatly improved. In recent years, however, the development of planar flash memories has met with various challenges: physical limits, existing development technology limits, and storage electron density limits, among others.
To address the difficulties encountered with flat flash memory and to seek lower production costs per unit cell, three-dimensional (3D) flash memory structures have evolved. In the structure of the 3D NAND flash memory device, a plurality of gate layers and insulating layers are vertically and alternately stacked, a channel hole is formed in a stack layer (or "stack"), a memory cell string is formed in the channel hole, and the gate layer in the stack layer is used as a gate line of each layer of memory cells, thereby realizing the stacked 3D NAND flash memory device.
The formation of the channel hole can be realized by adopting an anisotropic plasma dry etching process, however, plasma may damage the sidewall of the channel hole and generate leakage current, and at the same time, a Critical Dimension (CD for short) of the channel may also be increased, thereby affecting the performance of the channel hole and the performance of the final 3D NAND flash memory. Therefore, how to solve the problem of the damage to the side wall of the trench hole and the reduction of the critical dimension of the trench caused in the trench hole etching process is urgently needed to be solved.
Disclosure of Invention
The invention provides a 3D NAND memory device and a manufacturing method thereof, which can repair the damage of the side wall of a channel hole and the damage of the exposed substrate surface in the etching process of the channel hole and reduce the key dimension of the channel.
In one aspect, the present invention provides a method of manufacturing a 3D NAND memory device, including:
providing a substrate;
forming a stacked layer including alternately arranged interlayer insulating layers and dielectric layers on the substrate;
forming a longitudinally extending channel hole in the stack of layers, the channel hole being perpendicular to the substrate;
oxidizing the outermost part of the dielectric layer adjacent to the channel hole and the exposed substrate to form a sacrificial oxide layer;
removing portions of the interlayer insulating layer adjacent to the channel holes of the sacrificial oxide layer and the lateral thickness;
oxidizing a first part of the dielectric layer adjacent to the channel hole in the dielectric layer to form a first oxide layer;
forming a functional layer and a channel layer on the side wall of the channel hole;
forming a longitudinally extending grid line slit in the stacked layer, the grid line slit dividing the stacked layer into a plurality of stacked layer sub-blocks;
and removing the rest part of the dielectric layer by using the grid line slit and replacing the dielectric layer by the grid layer.
Preferably, the method further comprises: after removing the sacrificial oxide layer and before forming the first oxide layer, forming a selective silicon epitaxial layer at the bottom of the channel hole;
forming the first oxide layer further comprises: oxidizing a portion of the selective silicon epitaxial layer adjacent to the bottom of the channel hole.
Preferably, the reaction conditions for forming the sacrificial oxide layer and the first oxide layer include: the temperature is 700-1000 ℃.
Preferably, the lateral thickness of the sacrificial oxide layer is 2-15nm.
Preferably, the lateral thickness of the first oxide layer is 2-15nm.
Preferably, the channel layer includes a connection region at the bottom of the channel hole in contact with the upper surface of the selective silicon epitaxial layer.
Preferably, the gate layer comprises a high-K layer and an adhesion layer;
wherein the bonding layer comprises an adhesive buffer layer and a metal material layer.
Preferably, the method further comprises removing a portion of the adhesive layer adjacent to the gate line slits in the gate layer such that the adhesive layer is between the gate line slits, forming a recessed adhesive layer and a lateral void portion;
the lateral width of the vacant part is 0-100nm.
Preferably, the channel hole is communicated with the substrate and forms a groove with a certain depth, and the sacrificial oxide layer is partially formed on the surface of the groove.
Preferably, after removing the remaining dielectric layer by using the gate line slit and before replacing the dielectric layer with the gate layer, the method further includes: and oxidizing the side wall of the selective silicon epitaxial layer to form a second oxidation layer.
Preferably, the functional layer comprises a charge storage layer and a tunneling layer, and the outer diameter of the charge storage layer and the maximum outer diameter of the selective silicon epitaxial layer are on the same vertical extension line.
In another aspect, the present invention also provides a 3D NAND memory device, comprising:
a substrate;
a stacked layer on the substrate, the stacked layer including interlayer insulating layers and gate electrode layers alternately disposed;
a channel hole extending longitudinally through the stacked layers, the channel hole being perpendicular to the substrate;
the first oxide layer is formed on the outer side of the side wall of the channel hole and is at the same layer with the grid layer, and the functional layer and the channel layer are formed on the inner side of the side wall of the channel hole;
a grid line slit extending longitudinally through the stacked layer, the grid line slit dividing the stacked layer into a plurality of stacked layer sub-blocks.
Preferably, the lateral thickness of the first oxide layer is 2-15nm.
Preferably, the 3D NAND memory device further includes: a selective silicon epitaxial layer formed at the bottom of the channel hole;
the channel layer includes a connection region at the bottom of the channel hole in contact with the upper surface of the selective silicon epitaxial layer.
Preferably, the gate layer comprises a high-K layer and an adhesion layer;
wherein the bonding layer comprises a bonding buffer layer and a metal material layer.
Preferably, the adhesive layer includes a lateral vacant portion adjacent to the gate line slit and a retracted adhesive layer;
the lateral width of the vacant part is 0-100nm.
Preferably, the channel hole is opened to the substrate and forms a groove of a certain depth.
Preferably, a second oxide layer is arranged between the side wall of the selective silicon epitaxial layer and the laterally adjacent gate level layer.
Preferably, the functional layer comprises a charge storage layer and a tunneling layer, and the outer diameter of the charge storage layer and the maximum outer diameter of the selective silicon epitaxial layer are on the same vertical extension line.
The invention has the beneficial effects that: according to the manufacturing method of the 3D NAND memory device, the dielectric layer is oxidized in situ for multiple times to serve as the oxide layer, the outermost part of the dielectric layer, which is adjacent to the channel hole, and the exposed substrate are oxidized to form the sacrificial oxide layer for the first time, namely before the selective silicon epitaxial layer is formed, so that the damage to the side wall of the channel hole and the damage to the surface of the exposed substrate, which are caused in the etching process of the channel hole, are repaired, and the further expansion of the key size of the channel hole caused by the technological process is reduced; and oxidizing a first part of the dielectric layer adjacent to the channel hole and a part of the selective silicon epitaxial layer adjacent to the bottom of the channel hole to form a first oxide layer serving as a tunneling barrier layer on the side wall of the channel hole after forming the selective silicon epitaxial layer at the bottom of the channel hole for the second time, wherein the first part of the dielectric layer and the part of the selective silicon epitaxial layer are used for fixing and optimizing the critical dimension of the channel, and the tunneling barrier layer with uniform thickness can improve the storage characteristic of the channel hole.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a final structure according to a method provided by an embodiment of the present invention;
fig. 2 to 12 are schematic structural diagrams in a process of manufacturing a 3D NAND memory device according to the method provided by the embodiment of the invention.
Description of reference numerals:
100-a substrate; 110-stacked layers; 111-interlayer insulating layer/silicon oxide layer; 112-dielectric layer/silicon nitride layer; 1121-sacrificial oxide layer; 1122-first oxide layer; 113-gate layer; 1131 — high K layer; 1132-adhesion buffer layer; 1133 — a metallic material layer; 1134-vacant part; 121-channel holes; 122-a charge storage layer; 123-tunneling layer; 124-a channel layer; 1241-attachment area; 1242-plug polysilicon; 125-trench insulation filling layer; 130-selective silicon epitaxial layer; 131-a second oxide layer; 140-insulating oxide layer; 150-a grid line slit; 151-insulating layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. In the drawings, elements having similar structures are denoted by the same reference numerals. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "first", "second", and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to imply that the number of technical features indicated are in fact significant. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
The embodiment of the invention is used for solving the problem that the critical dimension of a channel is enlarged while the side wall of the channel hole is damaged and leakage current is generated due to channel hole etching in the forming process of the existing 3D NAND memory device.
The charge trap type 3D NAND memory device is described in the embodiments of the present invention.
FIG. 1 is a schematic structural diagram of a final structure according to a method provided by an embodiment of the present invention; fig. 2 to 12 are schematic structural diagrams in a process of manufacturing a 3D NAND memory device according to the method provided by the embodiment of the invention. As shown in fig. 2 to 12, an embodiment of the present invention provides a method of manufacturing a 3D NAND memory device and a structure formed by the method, the method including the steps of: providing a substrate 100; forming a stacked layer 110 on the substrate 100, the stacked layer 110 including interlayer insulating layers 111 and dielectric layers 112 alternately arranged; forming a longitudinally extending channel hole 121 (CH) in the stacked layer 110, the channel hole 121 being perpendicular to the substrate 100; oxidizing the outermost portion of the dielectric layer 112 adjacent to the channel hole 121 and the exposed substrate 100 to form a sacrificial oxide layer 1121; removing the sacrificial oxide layer 1121 and portions of the interlayer insulating layer 111 adjacent to the channel holes 121 in lateral thickness; forming a selective silicon epitaxial layer (SEG) 130 at the bottom of the channel hole 121; oxidizing a first portion of the dielectric layer 112 adjacent to the channel hole 121 and a portion of the selective silicon epitaxial layer 130 adjacent to the bottom of the channel hole 121 to form a first oxide layer 1122 as a tunneling barrier layer on the sidewall of the channel hole 121; forming a functional layer and a channel layer 124 on sidewalls of the channel hole 121, the channel layer 124 including a connection region 1241 at a bottom of the channel hole 121 in contact with an upper surface of the selective silicon epitaxial layer 130; forming a grid Line Slit 150 (GLS, gate Line Slit, or "Gate Slit") extending in the stack layer 110, wherein the grid Line Slit 150 divides the stack layer 110 into a plurality of sub-blocks of stack layers; the remaining portion of the dielectric layer is removed by the gate line slit 150 and replaced with the gate layer 113.
Specifically, as shown in fig. 2, the stacked layer 110 is formed on the substrate 100, the stacked layer 110 includes interlayer insulating layers 111 and dielectric layers 112 alternately arranged, and thicknesses of the interlayer insulating layers 111 and the dielectric layers 112 may not be equal. The number of stacked layers 110 is determined according to the number of memory cells required to be formed in the vertical direction, and the number of stacked layers 110 may be, for example, 8, 32, 64, or more, and the greater the number of stacked layers, the greater the integration of the memory device can be. The interlayer insulating layer 111 and the dielectric layer 112 may be alternately deposited in sequence by using chemical vapor deposition, atomic layer deposition, or other suitable deposition method to form the stack layer 110. In this embodiment, the material of the interlayer insulating layer 111 may be silicon oxide (SiOx), and the material of the dielectric layer 112 may be silicon nitride (SiNx).
Further, the silicon oxide layer and the silicon nitride layer located at the topmost layer in the stacked layer 110 may be used as a hard mask layer to ensure that the pattern is not changed after the subsequent patterning process of the stacked layer 110.
In this embodiment, the substrate 100 may be a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or GOI (Germanium On Insulator) or the like. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, such as SiC, and may also be a stacked structure, such as Si/SiGe or the like.
A channel hole 121 is formed in the stack of layers 110 perpendicular to the substrate 100. Specifically, a patterned photoresist is formed on the stack layer 110, and then, the stack layer 110 is etched by using an etching process to form the channel hole 121.
The etching process of the channel hole 121 is a plasma/polymer process, for example, an anisotropic plasma dry etching process is usually adopted to etch the stack layer 110 to form the channel hole 121, and the plasma/polymer may damage the sidewall of the channel hole 121 and the exposed substrate 100, thereby causing difficulty in epitaxially growing single crystal silicon in a subsequent process, and also causing generation of leakage current, which affects stability of the 3D NAND memory device.
After the channel hole 121 is formed by etching, a sacrificial oxide layer 1121 is preferably formed by in-situ oxidizing the outermost portion of the dielectric layer 112 adjacent to the channel hole 121 and the exposed substrate 100, as shown in fig. 3. The oxidation temperature is 700 to 1000 ℃, for example 700 ℃, 800 ℃, 900 ℃ or 1000 ℃, and any temperature between the above temperatures. The dielectric layer 112 is oxidized to form a sacrificial oxide layer 1121 at the outermost portion of the dielectric layer adjacent to the channel hole 121 and the exposed substrate 100, so that damage to the silicon nitride layer at the sidewall of the channel hole 121 and damage to the surface of the exposed substrate 100 are repaired, generation of leakage current is reduced, and stability of the 3D NAND memory device is improved.
Specifically, the channel hole 121 may reach the substrate 100, a groove with a certain depth is formed on the substrate 100, and the sacrificial oxide layer 1121 is partially formed on the surface of the groove, so that the damaged surface of the substrate 100 exposed in the in-situ oxidation process can be oxidized.
In the conventional 3D NAND memory device manufacturing process, before the channel is etched to selectively grow single crystal silicon at the bottom of the channel hole 121, there is a certain lateral consumption of the silicon oxide layer and the silicon nitride layer on the sidewall of the channel hole 121, i.e., the critical dimension of the channel hole 121 will continue to expand. In the method provided in the embodiment of the present invention, after the channel hole 121 is formed by etching, the outermost portion of the dielectric layer 112 adjacent to the channel hole 121 is oxidized to the sacrificial oxide layer 1121 by using in-situ oxidation, so that the sidewall of the channel hole 121 is covered by silicon oxide, which prevents the critical dimension of the channel hole 121 from being continuously enlarged.
When the critical dimension of the trench is too large, the gap between adjacent trench holes 121 will be small, and more voids may be generated when filling the gate material when replacing the dielectric layer 112 with the gate layer 113 in the subsequent process. The voids may affect the resistance of the gate layer 113, such that the resistance of the gate layer 113 increases, thereby affecting the electrical performance of the 3D NAND memory device. And reaction by-products generated during the gate material filling process, such as fluorine gas (F), may exist in the voids 2 ) The reaction by-product has strong oxidation performance, and is easy to cause the damage of the device and influence the stability of the device.
Preferably, the lateral thickness of the sacrificial oxide layer 1121 may be 2-15nm.
Fig. 4 shows a schematic structural view after removing the sacrificial oxide layer 1121, and a portion of the interlayer insulating layer 111 adjacent to the channel hole 121 in a plasma thickness through pretreatment. The pretreatment comprises pre-cleaning and H 2 (hydrogen) baking.
In this embodiment, by controlling the temperature and the oxidation time of the in-situ oxidation, the lateral thickness of the sacrificial oxide layer 1121 can be about 2-15nm, and the critical dimension of the channel can still be enlarged by about 15-20nm after the channel etching is completed in the conventional 3D NAND memory device. Therefore, under the same etching aperture condition, the final aperture of the channel hole 121 obtained by the preprocessing in this embodiment is still smaller than the final channel aperture of the conventional 3D NAND memory device, i.e., the critical dimension of the channel is reduced. Under the condition that the final channel aperture is the same, the method provided by the embodiment of the invention can etch a channel with a larger size when the stack layer 110 is etched, so that the difficulty in etching the channel hole 121 is reduced. In the etching process of the channel hole 121, the damaged surface of the substrate 100 exposed is oxidized into silicon dioxide, and is removed by pretreatment, thereby greatly reducing the difficulty of selectively growing monocrystalline silicon at the bottom of the channel hole 121, i.e., on the surface of the substrate 100.
Fig. 5 shows a schematic structural view of forming the selective silicon epitaxial layer (SEG) 130 at the bottom of the channel hole 121.
Further, the first silicon nitride layer 112 at the bottom of the stack layer 110 is used for a bottom-selective gate (BSG) in a subsequent process, and the selective silicon epitaxial layer 130 is used for a channel layer of the BSG, so that the upper surface of the selective silicon epitaxial layer 130 needs to exceed the upper surface of the first silicon nitride layer 112 at the bottom and be between the first silicon nitride layer 112 at the bottom and the second silicon nitride layer 112 at the bottom. The optimal upper surface positions of the selective silicon epitaxial layer 130 are: between the bottommost first layer and the second layer of the silicon nitride layer 112 at a position of 1/3-2/3.
Referring to fig. 6, the first oxide layer 1122, which is a tunneling barrier layer for the sidewalls of the channel hole 121, is then formed by oxidizing the first portion of the dielectric layer 112 adjacent to the channel hole 121 and the portion of the selective silicon epitaxial layer 130 adjacent to the bottom of the channel hole 121, again by in-situ oxidation. The oxidation temperature is 700 to 1000 ℃, and may be 700 ℃, 800 ℃, 900 ℃ or 1000 ℃, for example, and any temperature between the above temperatures.
Preferably, the lateral thickness of the first oxide layer 1122 may be 2 to 15nm.
The first oxide layer 1122 serves as a tunneling barrier layer, so that the steps of depositing the tunneling barrier layer are reduced, and the uniformity of the tunneling barrier layer is improved. The tunneling barrier layer of the conventional 3D NAND memory device is formed by depositing silicon oxide on the sidewalls of the channel hole 121, for example, depositing silicon oxide on the sidewalls of the channel hole 121 using an ALD process to form the tunneling barrier layer. The thickness of the silicon oxide grown on the top, middle and bottom of the channel hole 121 is different due to the ALD process, and thus the uniformity of the tunnel barrier layer is poor. In the method provided by the embodiment of the present invention, the first oxide layer 1122 is formed by in-situ oxidizing the first portion of the dielectric layer 112 adjacent to the channel hole 121 and the portion of the selective silicon epitaxial layer 130 adjacent to the bottom of the channel hole 121 and serves as a tunneling barrier layer. Because the in-situ oxidation process makes any position of the inner wall of the channel hole 121 be oxidized, and the depth of the lateral oxidation can be controlled by adjusting the process parameters, the uniformity of the tunneling barrier layer covering the whole inner side of the channel hole 121 is improved, that is, the uniformity of the tunneling barrier layer is improved.
In addition to the problem of poor thickness uniformity of the tunneling barrier layer when depositing silicon oxide on the entire sidewall of the trench hole 121 to form the tunneling barrier layer, a portion of the silicon nitride layer adjacent to the trench hole may be oxidized during the deposition process, so that the replaceable silicon nitride layer may be reduced when the silicon nitride layer is removed and replaced with a gate layer in the subsequent process, thereby resulting in a larger critical dimension of the trench at the gate layer compared to the critical dimension of the trench at the silicon oxide layer, and the critical dimensions of the trenches at the gate layers may be different, which may affect the uniformity of the critical dimension of the trench. In the embodiment of the present invention, the first oxide layer 1122 is used as a tunneling barrier layer, and the lateral oxidation depth of the first oxide layer 1122 formed by oxidation is controllable, so that the critical dimension of the channel at each gate layer tends to be as consistent as possible when the subsequent silicon nitride layer is removed and replaced with the gate layer, thereby avoiding the improper expansion of the critical dimension of the channel due to the poor thickness uniformity of the tunneling barrier layer, and realizing the fixation and optimization of the critical dimension of the channel.
After the first oxide layer 1122 is formed by oxidation, the functional layer and the channel layer 124 are formed on the sidewalls of the channel hole 121, as shown in fig. 7. The functional layer sequentially includes a charge storage layer 122 and a tunneling layer 123 inward along the sidewall of the channel hole 121. The first oxide layer 1122 serves as a tunneling barrier layer, and forms a storage function layer of the 3D NAND memory device together with the charge storage layer 122 and the tunneling layer 123. The tunneling layer 123 may be silicon oxide (SiOx), the charge storage layer 122 may be silicon nitride (SiNx) or silicon oxynitride (SiON), and the channel layer 124 may be polysilicon.
The first oxide layer 1122, the charge storage layer 122, the tunneling layer 123, and the channel layer 124 are etched to form a recess region on the upper surface of the selective silicon epitaxial layer 130. Polysilicon deposition is then continued to form a connection region 1241 where the channel layer 124 is located at the bottom of the channel hole 121 in contact with the upper surface of the selective silicon epitaxial layer 130.
In the above steps, a chemical vapor deposition or atomic layer deposition method may be adopted to form the charge storage layer 122, the tunneling layer 123 and the channel layer 124.
In other embodiments of the present invention, the shape of the connection region 1241 is not limited to a groove type, and may be any known shape as long as the channel layer 124 is brought into conduction with the selective silicon epitaxial layer 130.
Further, the outer diameter of the charge storage layer 122 is on the same vertical extension line as the maximum outer diameter of the selective silicon epitaxial layer 130. Compared with the conventional 3D NAND memory device in which the maximum outer diameter of the selective silicon epitaxial layer 130 and the tunneling barrier layer are on the same vertical extension line, the 3D NAND memory device manufactured by the method provided by the embodiment of the invention reduces the enlargement of the critical dimension of the channel, further compresses the dimension of the selective silicon epitaxial layer 130, and is beneficial to improving the uniformity of the dimension of the selective silicon epitaxial layer 130.
As shown in fig. 8, after the functional layer and the channel layer 124 are formed on the sidewall of the channel hole 121, the channel hole 121 is filled with silicon oxide to form a channel insulating filling layer 125. Then, a portion of the trench isolation filling layer 125 is etched back, and the silicon oxide layer and the silicon nitride layer located at the topmost layer in the stack layer 110 are removed, and the resulting structure is schematically shown in fig. 9. Wherein, the etch-back depth is 30-120nm downward along the topmost layer of the stack layer 110.
After etching back a portion of the trench insulating filling layer 125, plug polysilicon 1242 is deposited and Chemical Mechanical Polishing (CMP) is performed to form a trench structure. Silicon Oxide is deposited on the surface of the stack layer 110 to form an insulating Oxide layer 140 (also called CAP Oxide), and the insulating Oxide layer 140 covers the polysilicon plug 1242 to protect the channel structure and perform an insulating function. A longitudinally extending gridline slit 150 is then patterned in the stack 110. A plurality of the channel structures are included between the adjacent gate line slits 150, and the gate line slits 150 divide the stacked layer 110 into a plurality of stacked layer sub-blocks. The resulting structure is schematically shown in FIG. 10.
As shown in fig. 11, the remaining portion of the dielectric layer is removed by using the gate line slit 150 to form a groove structure. Specifically, after the remaining portion of the dielectric layer is exposed through the gate line slit 150, wet etching is performed on the remaining portion of the dielectric layer through the gate line slit 150, and the remaining portion of the dielectric layer is removed to form a groove structure. The sidewall of the selective silicon epitaxial layer 130 is oxidized by a high temperature wet oxygen oxidation process to form a second oxide layer 131.
As shown in fig. 12, the recess structure is filled with a conductive material to form the gate layer 113. Specifically, in order to prevent diffusion of metal atoms in the gate layer 113 to the silicon oxide layer 111, the gate layer 113 includes a high-K layer 1131 and an adhesion layer; wherein the bonding layer comprises a bonding buffer layer 1132 and a metal material layer 1133. The material of the high-K layer 1131 may be aluminum oxide (Al) 2 O 3 ) Or zirconium oxide (ZrO) 2 ) (ii) a The material of the adhesion buffer layer 1132 may be titanium nitride (TiN); the material of the metal material layer 1133 may be tungsten (W), and may further include polysilicon or a metal silicide material, for example, the metal silicide material may be provided as a silicide material including a metal selected from tungsten (W) and titanium (Ti).
In the embodiment of the present invention, in order to achieve a better blocking effect for metal atoms, an aluminum oxide layer is located as the high-K layer 1131 on a side close to the silicon oxide layer 111, and a TiN layer is located as the adhesion buffer layer 1132 between the high-K layer 1131 and the metal material layer 1133. The adhesive buffer layer 1132 alsoAs a conductive layer and F 2 And the barrier layer further improves the stability of the device.
Further, the high-K layer 1131 on the sidewall of the gate line slit 150 extends outward to cover the silicon oxide layer 111 exposed on the sidewall of the gate line slit 150, so as to ensure that the metal material layer 1133 does not enter the silicon oxide layer 111 during filling, thereby avoiding damage to the silicon oxide layer 111.
The method provided by the embodiment of the invention also comprises the following steps: portions of the adhesive layer in the gate layer 113 adjacent to the grid line slits 150 are removed so that the adhesive layer is between the grid line slits 150, forming a recessed adhesive layer and lateral void portions 1134.
Specifically, the portion of the bonding layer in the gate layer 113 adjacent to the gate line slit 150 is removed, and typically, with the high-K layer 1131 as an etching starting point, 0-100nm is etched inwards along the bonding layer to form an undercut bonding layer and a lateral gap portion 1134, where the lateral width of the gap portion 1134 is 0-100nm.
In the embodiment of the present invention, an insulating layer 151 is further formed on the sidewall of the gate line slit 150, and a schematic view of a final device structure is shown in fig. 1. The insulating layer 151 covers the vacant portions 1134, so that an insulating effect is further ensured, and stability of the device is improved.
Embodiments of the present invention also provide a 3D NAND memory device manufactured by the above method, referring to fig. 1, the memory device including: a substrate 100; a stack layer 110 on the substrate 100, the stack layer 110 including interlayer insulating layers 111 and gate layers 113 alternately disposed; a channel hole 121 extending longitudinally through the stacked layers 110, the channel hole 121 being perpendicular to the substrate 100 and forming a recess with a depth through the substrate 100; a selective silicon epitaxial layer 130 formed at the bottom of the channel hole 121, and a second oxide layer 131 is arranged between the sidewall of the selective silicon epitaxial layer 130 and the laterally adjacent gate level layer; a first oxide layer 1122 formed on the outer side of the sidewall of the channel hole 121 and on the same layer as the gate layer 113, a tunneling barrier layer as the sidewall of the channel hole 121, and a functional layer and a channel layer 124 formed on the inner side of the sidewall of the channel hole 121, wherein the channel layer 124 includes a connection region 1241 located at the bottom of the channel hole 121 and contacting the upper surface of the selective silicon epitaxial layer 130; a wire slit 150 extending longitudinally through the stack of layers 110, the wire slit 150 dividing the stack of layers 110 into a plurality of stacked layer sub-blocks.
Wherein the first oxide layer 1122 has a lateral thickness of 2-15nm.
Specifically, the functional layers include a charge storage layer 122 and a tunneling layer 123, and an outer diameter of the charge storage layer 122 is on the same vertical extension line as a maximum outer diameter of the selective silicon epitaxial layer 130. The first oxide layer 1122 serves as a tunneling barrier layer, and forms a storage function layer of the 3D NAND memory device together with the charge storage layer 122 and the tunneling layer 123.
Further, the 3D NAND memory device further includes a channel insulating filling layer 125 filled in the channel hole 121; and plug polysilicon 1242 covering the trench insulating fill layer 125 to form a trench structure; an insulating Oxide layer 140 (also referred to as CAP Oxide) covering the surface of the stack layer 110 and the polysilicon plug 1242 protects the channel structure and plays an insulating role.
Further, the gate layer 113 includes a high-K layer 1131 and an adhesion layer; wherein the bonding layer comprises a bonding buffer layer 1132 and a metal material layer 1133. The adhesive layer further includes a laterally absent portion 1134 adjacent the gridline slot 150 and a necked-in adhesive layer; the width of the void portion 1134 in the lateral direction is 0 to 100nm. The material of the high-K layer 1131 may be aluminum oxide (Al) 2 O 3 ) Or zirconium oxide (ZrO) 2 ) (ii) a The material of the adhesion buffer layer 1132 may be titanium nitride (TiN); the material of the metal material layer 1133 may be tungsten (W), and may further include polysilicon or a metal silicide material, for example, the metal silicide material may be provided as a silicide material including a metal selected from tungsten (W) and titanium (Ti).
In the memory device provided in this embodiment, an aluminum oxide layer is formed as the high-K layer 1131 on the side close to the silicon oxide layer 111, and a TiN layer is formed as the high-K layerThe adhesion buffer layer 1132 is located between the high-K layer 1131 and the metal material layer 1133, so as to achieve a better blocking effect on metal atoms. The adhesive buffer layer 1132 also serves as a conductive layer and F 2 And the barrier layer further improves the stability of the device.
Further, the high-K layer 1131 on the sidewall of the gate line slit 150 extends outward to cover the silicon oxide layer 111 exposed on the sidewall of the gate line slit 150, so as to ensure that the metal material layer 1133 does not enter the silicon oxide layer 111 during filling, thereby avoiding damage to the silicon oxide layer 111.
An insulating layer 151 is formed on the side wall of the gate line slit 150, and the insulating layer 151 covers the vacant portion 1134, so that an insulating effect is further ensured, and the stability of the device is improved.
According to the manufacturing method of the 3D NAND memory device provided by the embodiment of the invention, the damage of the side wall of the channel hole 121 and the surface damage of the exposed substrate 100 are repaired by performing in-situ oxidation on the dielectric layer 112 twice, the critical dimension of the channel is reduced, the step of depositing the tunneling barrier layer is reduced, and the uniformity of the tunneling barrier layer is improved. Under the core idea of the invention, for the floating gate type 3D NAND memory device, the damage of the side wall of the channel and the damage of the exposed substrate surface can be repaired by oxidizing the dielectric layer in situ, and the effect of reducing the key size of the channel is achieved; and part of the floating gate is subjected to in-situ oxidation to be used as the tunneling barrier layer, so that the steps of depositing the tunneling barrier layer are reduced, and the uniformity of the tunneling barrier layer is improved.
The above detailed description of the 3D NAND memory device and the manufacturing method thereof provided by the embodiments of the present invention are provided, and the principle and the embodiments of the present invention are described herein by applying specific examples, and the description of the above embodiments is only for assisting understanding of the technical solution and the core idea of the present invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (9)

1. A method of manufacturing a 3D NAND memory device, comprising:
providing a substrate;
forming a stacked layer including alternately arranged interlayer insulating layers and dielectric layers on the substrate;
forming a longitudinally extending channel hole in the stacked layers, the channel hole being perpendicular to the substrate;
oxidizing the outermost part of the dielectric layer adjacent to the channel hole and the exposed substrate to form a sacrificial oxide layer;
removing the sacrificial oxide layer and the part of the interlayer insulating layer with equal transverse thickness and adjacent to the channel hole;
oxidizing a first part of the dielectric layer adjacent to the channel hole in the dielectric layer to form a first oxide layer;
forming a functional layer and a channel layer on the side wall of the channel hole;
forming a grid line slit extending longitudinally in the stacked layer, wherein the grid line slit divides the stacked layer into a plurality of stacked layer sub-blocks;
removing the rest part of the dielectric layer by using the gate line slit, and replacing the dielectric layer with a gate layer;
after removing the sacrificial oxide layer and before forming the first oxide layer, forming a selective silicon epitaxial layer at the bottom of the channel hole; forming the first oxide layer further comprises: oxidizing a portion of the selective silicon epitaxial layer adjacent to the bottom of the channel hole, and after removing a remaining portion of the dielectric layer by using the gate line slit, before replacing the dielectric layer with a gate layer, further comprising: and oxidizing the side wall of the selective silicon epitaxial layer to form a second oxidation layer.
2. The method of manufacturing a 3D NAND memory device according to claim 1, wherein the reaction conditions for forming the sacrificial oxide layer and the first oxide layer include: the temperature is 700-1000 ℃.
3. The method of manufacturing a 3D NAND memory device of claim 1 wherein the sacrificial oxide layer has a lateral thickness of 2-15nm.
4. The method of manufacturing a 3D NAND memory device in accordance with claim 1, wherein the first oxide layer has a lateral thickness of 2-15nm.
5. The method of manufacturing a 3D NAND memory device of claim 1 wherein the channel layer includes a connection region at the bottom of the channel hole in contact with the upper surface of the selective silicon epitaxial layer.
6. The method of manufacturing a 3D NAND memory device of claim 1 wherein the gate layer comprises a high-K layer and an adhesion layer;
wherein the bonding layer comprises a bonding buffer layer and a metal material layer.
7. The method of manufacturing a 3D NAND memory device of claim 1, further comprising removing a portion of the adhesive layer adjacent to the gate line slits in the gate layer such that the adhesive layer is between the gate line slits, forming a recessed adhesive layer and a lateral vacant portion;
the lateral width of the vacant part is 0-100nm.
8. The method of manufacturing a 3D NAND memory device as claimed in claim 1, wherein the channel hole is opened to the substrate and a groove is formed to a certain depth, and the sacrificial oxide layer is partially formed on a surface of the groove.
9. The method of claim 1, wherein the functional layer comprises a charge storage layer and a tunneling layer, and an outer diameter of the charge storage layer is on a same vertical extension as a maximum outer diameter of the selective silicon epitaxial layer.
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