CN113745233A - Three-dimensional memory and manufacturing method thereof - Google Patents
Three-dimensional memory and manufacturing method thereof Download PDFInfo
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- CN113745233A CN113745233A CN202111036507.9A CN202111036507A CN113745233A CN 113745233 A CN113745233 A CN 113745233A CN 202111036507 A CN202111036507 A CN 202111036507A CN 113745233 A CN113745233 A CN 113745233A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Abstract
The application provides a three-dimensional memory and a manufacturing method thereof, wherein the method comprises the following steps: forming a stack layer on a substrate, wherein the stack layer comprises dielectric layers and sacrificial layers which are alternately stacked; forming a trench hole through the stacked layers; removing at least a portion of the sacrificial layer through the channel hole to form a recess; forming a charge storage portion in the recess, the charge storage portion being disposed between adjacent dielectric layers; removing the remaining portion of the sacrificial layer to expose the charge storage portion; and converting at least a portion of the exposed charge storage portion into a blocking portion. The barrier layer formed by the manufacturing method does not occupy the vertical space of the gate layer. Under the same stacking height, the three-dimensional memory can stack more layers of dielectric layers and gate layers, so that the storage capacity is increased.
Description
Technical Field
The present application relates to the field of semiconductor technology. In particular, the present application relates to a three-dimensional memory device and a method of manufacturing the same.
Background
With the increase of the number of stacked layers of the three-dimensional memory, the gate layer and the dielectric layer in the stacked layers are generally required to be thinned so as to reduce the height of the whole stacked layers, thereby relieving the load caused by deep hole etching. However, thinning the gate layer and dielectric layer thickness can create coupling effects between the memory cells and reduce the data retention capability of the three-dimensional memory.
It is to be appreciated that this background section is intended in part to provide a useful background for understanding the technology, however, it is not necessary for these matters to be within the knowledge or understanding of those skilled in the art prior to the filing date of the present application.
Disclosure of Invention
An aspect of the present application provides a method of manufacturing a three-dimensional memory, the method including: forming a stack layer on a substrate, wherein the stack layer comprises dielectric layers and sacrificial layers which are alternately stacked; forming a trench hole through the stacked layers; removing at least a portion of the sacrificial layer through the channel hole to form a recess; forming a charge storage portion in the recess, the charge storage portion being disposed between adjacent ones of the dielectric layers; removing the remaining portion of the sacrificial layer to expose the charge storage portion; and oxidizing at least a portion of the exposed charge storage portion to a blocking portion.
In one embodiment of the present application, the method further comprises: forming a gate slit through the stacked layers; wherein the step of removing the remaining portion of the sacrificial layer to expose the charge storage portion comprises: removing the remaining portion of the sacrificial layer through the gate slit to expose the charge storage portion.
In one embodiment of the present application, the method further comprises: filling a conductive layer in a void formed due to the removal of the remaining portion of the sacrificial layer through the gate slit.
In one embodiment of the present application, before forming the charge storage portion, the method further includes:
and forming an etching stop layer on the part of the sacrificial layer, which is positioned on the side wall of the recess, wherein the etching stop layer comprises polycrystalline silicon.
In one embodiment of the present application, forming the etch stop layer includes: forming an initial etch stop layer on the sacrificial layer and the walls of the dielectric layer exposed to the channel hole; and removing the part of the initial etching stop layer on the wall of the dielectric layer so as to form the etching stop layer on the part of the sacrificial layer on the side wall of the recess.
In one embodiment of the present application, the sacrificial layer has a predetermined first etch selectivity with respect to the charge storage portion to retain the charge storage portion upon removal of the sacrificial layer.
In one embodiment of the present application, forming the charge storage portion includes: forming a storage layer in the recess and on the side wall of the dielectric layer; and removing portions of the storage layer on sidewalls of the dielectric layer to form a plurality of discrete charge storage portions within the recesses.
In one embodiment of the present application, a chemical vapor deposition process is performed to form the stack layer, and an atomic layer deposition is performed to form the charge storage portion.
In one embodiment of the present application, prior to removing the remaining portion of the sacrificial layer, the method further comprises: a tunneling layer, a channel layer, and a dielectric core are sequentially deposited along a sidewall of the channel hole.
In one embodiment of the present application, removing the remaining portion of the sacrificial layer comprises: etching the rest part of the sacrificial layer and stopping at the etching stopping layer; and removing the etching stop layer.
An aspect of the present application provides another method of manufacturing a three-dimensional memory, including:
forming a stack layer on a substrate, wherein the stack layer comprises dielectric layers and sacrificial layers which are alternately stacked; forming a trench hole through the stacked layers; removing at least a portion of the sacrificial layer through the channel hole to form a recess; forming an etching stop layer on the side wall of the sacrificial layer; forming a charge storage portion within the recess, wherein the charge storage portion covers sidewalls of the etch stop layer; removing the rest part of the sacrificial layer to expose the etching stop layer; and oxidizing the etch stop layer to at least a portion of the barrier portion.
In one embodiment of the present application, forming the etch stop layer includes: forming an initial etch stop layer on the sacrificial layer and the walls of the dielectric layer exposed to the channel hole; and removing the part of the initial etching stop layer on the wall of the dielectric layer so as to form the etching stop layer on the part of the sacrificial layer on the side wall of the recess.
In one embodiment of the present application, the forming the charge storage portion in the recess includes: forming a storage layer in the recess and on the side wall of the dielectric layer; and removing the part of the storage layer positioned on the side wall of the dielectric layer so as to form the charge storage part in the recess.
In one embodiment of the present application, the sacrificial layer has a predetermined second etch selectivity with respect to the etch stop layer to leave the etch stop layer when the sacrificial layer is removed.
In one embodiment of the present application, a chemical vapor deposition process is performed to form the stack layer, and an atomic layer deposition is performed to form the charge storage portion.
In one embodiment of the present application, prior to removing the remaining portion of the sacrificial layer, the method further comprises: a tunneling layer, a channel layer, and a dielectric core are sequentially deposited along a sidewall of the channel hole.
In one embodiment of the present application, the oxidizing the etch stop layer into at least a portion of the barrier portion comprises: oxidizing the etch stop layer to be part of the barrier portion; and simultaneously oxidizing a portion of the charge storage portion to a remaining portion of the blocking portion.
Yet another aspect of the present application provides a three-dimensional memory, including: the stacked structure comprises conductive layers and dielectric layers which are stacked alternately; and a channel structure having a first portion passing through the stacked structure and a plurality of second portions disposed between adjacent ones of the dielectric layers, the second portions comprising: a plurality of blocking portions covering sidewalls of the respective conductive layers facing the first portion; and a plurality of storage portions covering sidewalls of the respective blocking portions facing the first portion.
In one embodiment of the present application, the three-dimensional memory further comprises: a gate slit structure including an insulating layer formed in a gate slit that penetrates the memory stack structure and a conductive channel formed on the insulating layer.
In one embodiment of the present application, the first portion includes a tunneling layer, a channel layer, and a dielectric core sequentially stacked on sidewalls of the dielectric layer and the memory portion.
In one embodiment of the present application, the barrier portion includes silicon oxynitride or silicon oxide, and the storage portion includes silicon nitride.
Drawings
Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. In the drawings, there is shown in the drawings,
fig. 1 is a flowchart of a method for manufacturing a three-dimensional memory according to a first embodiment of the present application;
fig. 2 is a partial schematic view of a device structure after forming a trench hole according to a method of fabricating a three-dimensional memory according to a first embodiment of the present application;
fig. 3 is a partial schematic view of a device structure formed after removing at least a portion of a sacrificial layer according to a method of fabricating a three-dimensional memory according to a first embodiment of the present application;
FIG. 4 is a partial schematic view of a device structure after forming a memory layer according to a first embodiment of the present disclosure;
fig. 5 is a partial schematic view of a device structure after forming a plurality of charge storage portions according to a method of fabricating a three-dimensional memory according to a first embodiment of the present application;
fig. 6 is a partial schematic view of a device structure formed after filling a channel hole according to a method of fabricating a three-dimensional memory according to a first embodiment of the present application;
fig. 7 is a partial schematic view of a device structure formed after removing the remaining portion of the sacrificial layer according to a method of fabricating a three-dimensional memory according to a first embodiment of the present application;
FIG. 8 is a partial schematic view of a device structure after oxidation of the charge storage portion according to a method of fabricating a three-dimensional memory according to a first embodiment of the present application;
FIG. 9 is a partial schematic view of a device structure after forming a barrier layer according to a three-dimensional memory fabrication method of some embodiments of the present application;
fig. 10 is a partial schematic view of a device structure formed after filling a conductive layer according to a method of fabricating a three-dimensional memory according to a first embodiment of the present application;
FIG. 11 is a partial schematic view of a three-dimensional memory according to a first embodiment of the present application;
fig. 12 is a flowchart of a method of manufacturing a three-dimensional memory according to a second embodiment of the present application;
FIG. 13 is a partial schematic view of a device structure after forming an initial etch stop layer in a method of fabricating a three-dimensional memory according to a second embodiment of the present application;
fig. 14 is a partial schematic view of a device structure after forming an etch stop layer according to a method of fabricating a three-dimensional memory according to a second embodiment of the present application;
fig. 15 is a partial schematic view of a device structure after forming a memory layer according to a three-dimensional memory manufacturing method of a second embodiment of the present application;
fig. 16 is a partial schematic view of a device structure after forming a plurality of charge storage portions according to a three-dimensional memory manufacturing method of a second embodiment of the present application;
fig. 17 is a partial schematic view of a device structure formed after filling a channel hole according to a method of fabricating a three-dimensional memory according to a second embodiment of the present application;
fig. 18 is a partial schematic view of a device structure formed after removal of the remaining portions of the sacrificial layer according to a three-dimensional memory fabrication method of a second embodiment of the present application;
fig. 19 is a partial schematic view of a device structure formed after oxidizing an etch stop layer according to a method of fabricating a three-dimensional memory according to a second embodiment of the present application;
FIG. 20 is a partial schematic view of a device structure after oxidizing an etch stop layer and simultaneously oxidizing a portion of a charge storage portion according to a method of fabricating a three-dimensional memory of a second embodiment of the present application
Detailed Description
For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification.
Note that references in the specification to "one embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
In general, terms may be understood at least in part from the context of their use. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe a combination of features, structures, or characteristics in the plural, depending, at least in part, on the context. Similarly, terms such as "a" or "the" may also be understood to convey a singular use or to convey a plural use, depending, at least in part, on the context. Moreover, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors not necessarily explicitly described, again depending at least in part on the context.
It should be readily understood that the meanings of "on", "above" and "over" in the present disclosure should be interpreted in the broadest manner, such that "on" not only means "directly on" but also includes the meaning of "on" and having intermediate features or layers therebetween, and "above" or "over" not only means "above" or "over" but also can include the meaning of "above" or "over" and having no intermediate features or layers therebetween (i.e., directly on something).
Furthermore, spatially relative terms such as "under," "below," "lower," "above," "upper," and the like may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entire superstructure or understructure, or may have a smaller extent than the understructure or superstructure. Furthermore, the layer may be a region of a continuous structure, uniform or non-uniform, having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of levels at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, above, and/or below. The layer may comprise a plurality of layers.
In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. For example, as used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-wise terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.
It will be further understood that the terms "comprises," "comprising," "has," "having," "includes" and/or "including," when used in this specification, specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Moreover, when a statement such as "at least one of" appears after a list of listed features, the entirety of the listed features is modified rather than modifying individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.
Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In addition, the embodiments and features of the embodiments in the present application may be combined with each other without conflict. In addition, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
In describing the embodiments of the present application, the schematic diagram illustrating the structure of the device is not partially enlarged in general scale for convenience of illustration, and the schematic diagram is only an example, which should not limit the scope of protection of the present application. In addition, a three-dimensional space ruler with length, width and depth is required in actual manufacturing. It should be understood that the operations shown in the method are not exhaustive and that other operations may be performed before, after, or in between any of the operations described.
Implementation mode one
Fig. 1 is a flowchart of a method 200 for manufacturing a three-dimensional memory according to a first embodiment. Referring to fig. 1, the manufacturing method includes an operation S210 of forming a stack layer on a substrate, the stack layer including dielectric layers and sacrificial layers alternately stacked.
As shown in fig. 2, a stacked layer formed by alternating a plurality of dielectric layers 101 and sacrificial layers 102 may be formed over a substrate (not shown), and the material for preparing the substrate may be selected from any suitable semiconductor material, such as monocrystalline silicon, polycrystalline silicon, monocrystalline germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide, or other iii-v compounds.
In this step, the substrate has opposite top and bottom surfaces, the top surface of the substrate representing one surface in contact with the stack of layers. A first direction in or parallel to the top surface of the substrate represents an X direction, a second direction in or parallel to the top surface of the substrate represents a Y direction, a direction perpendicular to the top surface of the substrate represents a Z direction, and a symbol adjacent to the letter "Y" and showing a combination of a circle and a cross indicates that the Y direction in the drawing is directed inward with respect to the drawing page of the figure. In some examples, dielectric layers 101 and sacrificial layers 102 may be alternately stacked in the Z-direction from the top surface of the substrate.
In some embodiments, the stack layer may include a plurality of dielectric layer 101/sacrificial layer 102 pairs, and the number of pairs may be selected according to various application scenarios, for example, the number of pairs may be 32, 64, 96, 128, 160, 192, 224, 256 or more. In some examples, materials that may be used for dielectric layer 101 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. Under the same etching process, the dielectric layer 101 and the sacrificial layer 102 have a higher etching selectivity ratio to ensure that the dielectric layer 101 is hardly removed when the sacrificial layer 102 is subsequently removed. As one example, sacrificial layer 102 may comprise silicon nitride and dielectric layer 101 may comprise silicon oxide.
Illustratively, the stacked layers may be formed over the substrate by repeating and alternately performing a deposition process of the dielectric layer 101 and the sacrificial layer 102, which may include, for example, a thin film deposition process of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof. In some embodiments, as the number of stacked layers is more and more demanding, deposition processes with higher deposition rates, such as chemical vapor deposition, are often used to increase the deposition time and thus the throughput.
In some embodiments, a stair-step structure (not shown in FIG. 2) may be formed on both sides or in the middle of the stacked layers. The formation of the stair step structure may include repeatedly etching the dielectric layer 101 and the sacrificial layer 102 by using a mask layer (e.g., a patterned photoresist or PR layer) over the stacked layers. Illustratively, the masking layer may be trimmed to expose portions of the dielectric layer 101 and the sacrificial layer 102 to be etched such that the exposed portions may be etched using a suitable etching process. Wherein the etching of the dielectric layer 101 and the sacrificial layer 102 may include a wet etching process, and then the mask layer may be removed. It is understood that the stair-step structure may be formed at any suitable stage of a method of fabricating a three-dimensional memory device without departing from the teachings of the present invention.
Returning to fig. 1, the method continues to operation S220, a channel hole may be formed in a stack layer formed by alternately stacking a sacrificial layer and a dielectric layer.
As shown in fig. 2, after the stacked layers are formed, a plurality of channel holes 110 can be formed in the stacked layers. In some embodiments, the plurality of channel holes 110 can be arranged in an array in a stacked layer, and each channel hole 110 can extend vertically through the stacked layer and into the substrate along the Z-direction. In addition, the trench hole 110 can have a high aspect ratio and can be formed by etching the stack layer. Illustratively, the stack can be etched into the substrate by forming a masking layer over the stack and patterning the masking layer using, for example, a photolithographic process, and then performing a suitable etching process, such as a wet etch, a dry etch, or a combination thereof. In some embodiments, the mask layer may be removed after forming the plurality of channel holes 110.
Returning to fig. 1, the method continues to operation S230, where at least a portion of the sacrificial layer may be removed via the trench hole to form a recess, and fig. 3 shows a corresponding structure.
As shown in fig. 4, in some embodiments, a portion of each sacrificial layer 102 along the X-direction and the Z-direction may be removed through the channel hole 110 by an isotropic wet etching process to expose a portion of the top surface and the bottom surface of each dielectric layer 101, such that each adjacent dielectric layer 101 and the sacrificial layer 102 therebetween form a recess 111 along the X-direction, the recess 111 being perpendicular to and in communication with the channel hole 110.
Returning to fig. 1, the method continues to operation S240, where a charge storage portion may be formed within each recess, the charge storage portion being disposed between adjacent dielectric layers, and a corresponding structure is shown in fig. 5.
As shown in fig. 4, in some embodiments, a memory layer 103-1, which may be formed of a material including silicon nitride, silicon oxynitride, silicon, or any combination thereof, may be formed in the recess (not shown) and on the sidewall of the dielectric layer 101 along the channel hole 110 by a suitable deposition process, such as a thin film deposition process of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof. Then, the memory layer 103-1 of the portion of the dielectric layer 101 on the sidewall of the channel hole 110 is removed, thereby forming a plurality of discrete charge storage portions 103-2 as shown in fig. 5, wherein the charge storage portions 103-2 may be disposed between adjacent dielectric layers 101. The charge storage portion 103-2 is capable of storing charges to perform a storage operation, and thus the film quality requirement for the storage layer 103-1 is high. In some examples, to form the storage layer 103-1 with low roughness and high density, an atomic level deposition process, such as an atomic layer deposition process, is typically employed.
During the operation of the three-dimensional memory device, the plurality of charge storage portions 103-2 can reduce the diffusion of charges stored therein between adjacent memory cells along the Z-direction, thereby reducing the charge loss of the storage layer and enhancing the data retention capability of the three-dimensional memory. On the other hand, the coupling effect of the storage unit caused by the non-uniform electric field distribution can be improved, and the reliability of the three-dimensional storage device is improved.
As shown in fig. 6, in some examples, after forming the plurality of charge storage portions 103-2, a tunneling layer 105, a channel layer 106, and a dielectric core 107 may be sequentially deposited at sidewalls of the charge storage portions 103-2 and the dielectric layer 101 radially toward a center of the channel hole 110 by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, wherein charges of the charge storage portions 103-2 may tunnel into the channel layer 106 via the tunneling layer 105 and be transported in the channel layer 106.
Illustratively, the material for the tunneling layer 105 may include silicon oxide, silicon nitride, silicon oxynitride, a high-K dielectric material such as aluminum oxide or hafnium oxide. The material for the channel layer 106 may include one or more semiconductor materials, such as a single element semiconductor material, a group III-V compound semiconductor material, a group II-VI compound semiconductor material, and/or an organic semiconductor material. In some embodiments, the channel layer 106 may include a polysilicon layer for facilitating charge transport.
In some examples, the dielectric core 107 may include a suitable dielectric material, such as silicon oxide, and may fill the space of the remaining channel hole 110 surrounded by the channel layer 106.
Returning to fig. 1, the method continues to operation S250, where the remaining portion of the sacrificial layer may be removed to expose the charge storage portion, and fig. 7 shows a corresponding structure. In some examples, the gate slit (not shown in fig. 7) may continue to be formed in the stacked layers through the stacked dielectric layers 101 and sacrificial layers 102 after forming a portion of the channel structure. Illustratively, a gate slit (not shown in fig. 7) may be formed between adjacent channel holes by an anisotropic etching process such as dry etching and/or an isotropic etching process such as wet etching.
Then, the remaining portion of the sacrificial layer 102 is removed via the gate slit, thereby exposing sidewalls of the plurality of charge storage portions 103-2 at a side facing away from the channel hole. At the same time, the remaining portions of the top and bottom surfaces of dielectric layer 101 may also be exposed, such that adjacent dielectric layers 101 and the charge storage portion 103-2 therebetween form a void 112 that is perpendicular to and in communication with the gate slit.
In some embodiments, the process of removing the remaining portion of the sacrificial layer 102 may include an isotropic wet etch. The sacrificial layer 102 has a higher etch selectivity ratio than the charge storage portion 103-2 under the same wet etching process, and thus the charge storage portion 103-2 is hardly damaged.
In some embodiments, the sacrificial layer 102 and the charge storage portion 103-2 may comprise silicon nitride, and the ratio of nitrogen to silicon in the sacrificial layer 102 may be adjusted to be different from the ratio of nitrogen to silicon in the charge storage portion 103-2, so as to enable selective etching, while ensuring that the ratio of nitrogen to silicon in the charge storage portion 103-2 can achieve better storage performance.
In some examples, when sacrificial layer 102 and charge storage portion 103-2 both comprise silicon nitride, both may also be doped to change the elemental species to enable selective etching.
Returning to fig. 1, the method continues to operation S260, where at least a portion of the exposed charge storage portion may be oxidized into a blocking portion, and fig. 8 shows a corresponding structure.
As shown in fig. 8, in some examples, after forming the voids 112, a portion of the plurality of charge storage portions 103-2 (e.g., silicon nitride) facing away from the channel hole 110 may be oxidized into a plurality of blocking portions (e.g., silicon oxide or silicon oxynitride) by a thermal oxidation process and/or a chemical oxidation process via a gate slit (not shown in fig. 8) to form the plurality of blocking portions 104 and the final storage portion 103. For example, thermal oxidation may include an in situ steam process that uses oxygen and hydrogen to generate water in the form of steam. Illustratively, the material for the barrier portion 104 may include silicon oxide, silicon nitride, silicon oxynitride, a high-K dielectric material such as aluminum oxide or hafnium oxide. Alternatively, the channel structure may comprise a silicon-oxide-nitride-oxide (SONO) structure.
The manufacturing method provided by the present application can directly oxidize the charge storage portion 103-2 after removing the remaining portion of the sacrificial layer 102, so as to reduce the quality damage of the charge storage portion 103-2 caused by excessive etching processes.
In some embodiments, as shown in fig. 9, after the recess 111 is formed, the barrier layer 104 'may be formed on the inner wall of the recess 111 and the dielectric layer 111, and the formed barrier layer 104' tends to occupy a certain space in a direction perpendicular to the substrate (Z direction), so that the utilization rate of vertical space for a gate layer formed in a subsequent step is reduced, and thus the number of layers of the stacked structure is reduced, resulting in a reduction in storage capacity.
As shown in fig. 10, in some embodiments, after forming the barrier portion 104, the conductive layer 108 may be filled in the void 112 (fig. 8) via a gate slit (not shown in fig. 10) in a suitable step. As one example, the conductive layer 108 may serve as a gate layer of a three-dimensional memory.
Illustratively, the material used to form the conductive layer 108 includes a conductive material, which may include W, Co, Cu, Al, Ti, Ta, TiN, TaN, Ni, doped silicon, a silicide (e.g., NiSix, WSix, CoSix, TiSix), or any combination thereof.
Some embodiments of the present application will not occupy vertical space of the conductive layer 108 by first forming the charge storage portion 103-2 in the recess 111, which may have the same dimension in the Z-direction as the conductive layer 108, and then oxidizing at least a portion of the charge storage portion 103-2 for forming the blocking portion 104, which may have the same dimension in the Z-direction as the conductive layer 108. A greater number of dielectric 101 layers and conductive layers 108 can be stacked at the same stack height, thereby increasing storage capacity. Further, the barrier portion 104 formed by oxidizing the charge storage portion 103-2 is excellent in film denseness and uniformity, and leakage of charges can be effectively reduced.
In some embodiments, an insulating layer may also be formed in the gate slit (not shown) and a conductive channel may be formed on the insulating layer, wherein the insulating layer may serve to electrically isolate the conductive layer 108 from the conductive channel, which may serve as a lead-out channel for a common source line electrical connection.
Another aspect of the present embodiment provides a three-dimensional memory 100, as shown in fig. 11, the three-dimensional memory 100 including: a substrate (not shown in fig. 11), a stacked structure 109 formed on the substrate, and a channel structure 119 formed in the stacked structure 109. The stacked structure 109 includes dielectric layers 101 and conductive layers 108 stacked alternately, the conductive layers 108 can serve as gate layers, and memory cells can be formed at intersections of the gate layers and the channel structures 119. As one example, dielectric layer 101 may comprise silicon oxide and conductive layer 108 may comprise W.
Referring again to fig. 11, the channel structure 119 may include a first portion 120 vertically penetrating through the stacked structure 109 and a plurality of second portions 121 disposed between adjacent dielectric layers 101, and the first portion 120 and the second portions 121 between each adjacent dielectric layer 101 may remain connected.
In some examples, the second portion 121 includes a plurality of discrete blocking portions 104 and a plurality of discrete storage portions 103, wherein the blocking portions 104 may cover sidewalls of the respective conductive layers 108 facing the first portion 120, and the storage portions 103 may cover sidewalls of the respective blocking portions 104 facing the first portion 120.
In some examples, the dimensions of the barrier portion 104 and the storage portion 103 in the Z direction are the same as the dimensions of the conductive layer 108 in the same direction, so that the barrier portion may directly contact the inner surface of the adjacent dielectric layer 101 in the Z direction. Thus, the blocking portion 104 will not occupy the vertical space of the conductive layer 108 in the Z-direction. A greater number of dielectric 101 layers and conductive layers 108 can be stacked at the same stack height, thereby increasing storage capacity.
During the operation of the three-dimensional memory device, on one hand, the storage part 103 can prevent the stored charges from diffusing between adjacent storage units, reduce the charge loss of the storage part 103 and enhance the data retention capability of the three-dimensional memory; on the other hand, the coupling effect of the storage unit caused by the non-uniform electric field distribution can be improved, and the reliability of the three-dimensional storage device is improved.
In some examples, the first portion 120 includes a tunneling layer, a channel layer, and a dielectric core (not shown in the figures) sequentially stacked on sidewalls of the dielectric layer 101 and the memory portion 103.
Illustratively, the blocking portion 104 may include silicon oxide or silicon oxynitride, which may reduce leakage of charge; the memory portion 103 may include silicon nitride, which is capable of trapping and storing charge that may tunnel through a tunneling layer (not shown) into a channel layer (not shown) and may be transported in the channel layer (not shown). In some embodiments, the tunneling layer (not shown) may comprise silicon oxide and the channel layer (not shown) may comprise a polysilicon layer for facilitating charge transport.
In some examples, the three-dimensional memory 100 further includes a gate slit structure (not shown in fig. 11) including an insulating layer and a conductive channel filled in the gate slit formed through the stack structure 109. Wherein the insulating layer may serve to electrically isolate the conductive layer 108 from the conductive channel, which may serve as a lead-out channel for electrical connection of the common source line.
Second embodiment
When the sacrificial layer 102 and the charge storage portion 103-2 comprise silicon nitride at the same time, some embodiments may choose a suitable etching process by increasing the difference between the materials of the sacrificial layer 102 and the charge storage portion 103-2 when the remaining portion of the sacrificial layer 102 is removed by an etching process. In some embodiments, the charge storage portion 103-2 and the sacrificial layer may also be separated by forming an etch stop layer between the charge storage portion 103-2 and the sacrificial layer 102 that is a different material from the two.
Fig. 12 shows a flowchart of a method 300 for manufacturing a three-dimensional memory according to a second embodiment. The memory manufacturing method according to the second embodiment includes operations S210, S220, and S230, as shown in fig. 12. S210, S220, and S230 in this second embodiment are the same as the steps of forming the stack layers on the substrate, forming the channel hole 110 (fig. 2) through the stack layers, and removing at least a portion of the sacrificial layer 102 via the channel hole 110 to form the recess 111 in the first embodiment described above, and thus a detailed description thereof is omitted.
As shown in fig. 12, operation continues to S340, where an etch stop layer may be formed on portions of the sacrificial layer located on sidewalls of the recess.
As shown in fig. 13, an initial etch stop layer 130 'may be formed on the sacrificial layer 102 and the dielectric layer 101 exposed to the walls of the channel hole 110 using a suitable deposition process, such as a thin film deposition process of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof, the initial etch stop layer 130' having a certain difference from the material of the sacrificial layer 102. Then, as shown in fig. 14, a portion of the initial etch stop layer 130' on the wall of the dielectric layer 101 may be removed, thereby forming the etch stop layer 130 on the sidewall of the sacrificial layer 102 in the recess 111.
In some examples, the portion of the initial etch stop layer 130 'on the wall of the dielectric layer 101 may be removed by an etching process, wherein the initial etch stop layer 130' has an etch selectivity with respect to the dielectric layer 101 in a predetermined range, and the etch selectivity may be, for example, in a range of 2500 to 1000: 1. Due to the higher etch selectivity, dielectric layer 101 exposed to the etch ambient is less lost when etching initial etch stop layer 130'.
In some embodiments, the etching process through the channel hole 110 may cause an etching loss to the dielectric layer 101 on the sidewall of the channel hole 110 to a certain extent, which increases the radial dimension of the channel hole 110, and the number of the channel holes 110 may decrease in a certain storage area, thereby reducing the storage density.
In some examples, dielectric layer 101 comprises silicon oxide, initial etch stop layer 130' comprises polysilicon, and the first etch selectivity may be 1000. When the initial etch stop layer 130 'comprises polysilicon, the loss of the dielectric layer 101 along the sidewall of the channel hole 110 is relatively reduced, and the loss of the storage density caused by the etching process of the channel hole 110 can be reduced, compared to the initial etch stop layer 130' which is made of other material with lower etch selectivity.
In some examples, the first etch option may also be 1500 by adjusting the etch conditions.
Returning to fig. 12, operation continues to S350, where a charge storage portion may be formed within the recess, where the charge storage portion covers sidewalls of the etch stop layer.
In some embodiments, as shown in fig. 15, after forming the etch stop layer 130, a memory layer 103-1 may be formed in the recess (not shown) and on the sidewall of the dielectric layer 101 along the channel hole 110 by using a suitable thin film deposition process, and the material for forming the memory layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. Then, a portion of the storage layer 103-1 on the sidewall of the dielectric layer 101 is removed, thereby forming a plurality of discrete charge storage portions 103-2 as shown in fig. 16, wherein the charge storage portions 103-2 may cover the sidewall of the etch stop layer 130 facing the channel hole 110. The charge storage portion 103-2 is capable of storing charges to perform a storage operation, and thus the film quality requirement for the storage layer 103-1 is high. In some examples, to form the storage layer 103-1 with low roughness and high density, an atomic level deposition process, such as an atomic layer deposition process, is typically employed.
During operation of the three-dimensional memory device, the plurality of discrete charge storage portions 103-2 can reduce, on the one hand, diffusion of charges stored therein between adjacent memory cells along the Z-direction, thereby reducing charge loss of the storage layer 103-1 and enhancing data retention capability of the three-dimensional memory. On the other hand, the coupling effect of the storage unit caused by the non-uniform electric field distribution can be improved, and the reliability of the three-dimensional storage device is improved.
In some examples, as shown in fig. 17, after forming the plurality of charge storage portions 103-2, a tunneling layer 105, a channel layer 106, and a dielectric core 107 are sequentially deposited at sidewalls of the charge storage portions 103-2 and the dielectric layer 101 radially toward a center of the channel hole 110.
In some examples, the tunneling layer 105, the channel layer 106, and the dielectric core 107 may be formed by the same deposition process and materials as those in the first embodiment, which are not described herein.
Returning to fig. 12, operation continues to S360 where the remaining portion of the sacrificial layer may be removed to expose the etch stop layer.
In some embodiments, a gate slit (not shown) may be formed in the stacked layers through the stacked dielectric layer 101 and sacrificial layer 102. The remaining portions of the sacrificial layer 102 are then removed via the gate slits, respectively, thereby exposing the etch stop layer 130 at a side facing away from the channel hole.
As shown in fig. 18, when removing the remaining portion of the sacrificial layer 102, a suitable etching process may be employed such that the sacrificial layer 102 has a higher etching selectivity than the etch stop layer 130, so that the etching may stop at a surface of the etch stop layer 130 facing away from the channel hole 110 when the sacrificial layer 102 is removed. At the same time, the remaining portions of the top and bottom surfaces of dielectric layers 101 may also be exposed, such that adjacent dielectric layers 101 and etch stop layer 130 therebetween form a void 112 that is perpendicular to and in communication with the gate slit.
Returning to fig. 12, operation continues to S370 where the etch stop layer may be oxidized into at least a portion of the barrier portion.
In some embodiments, the etch stop layer 130 comprises, for example, polysilicon, as shown in fig. 18 and 19, the etch stop layer 130 may be oxidized into the plurality of barrier portions 104 (e.g., silicon oxide) by a chemical oxidation process, for example, comprising ozone, via gate slits (not shown). In some embodiments where etch stop layer 130 comprises polysilicon, the oxidation rate of etch stop layer 130 is relatively high compared to some embodiments where etch stop layer 130 comprises silicon nitride, with a ratio in the range of 400-800:1 at similar oxidation temperatures.
In some embodiments, as shown in fig. 20, the etch stop layer 130 comprises, for example, polysilicon, and a portion of the etch stop layer 130 and the charge storage portion 103-2 may be oxidized into the blocking portion 104. For example, the etch stop layer 130 may be oxidized into a portion of the barrier portion 104 by a suitable oxidation process, while a portion of the charge storage portion 103-2 in contact with the etch stop layer 130 is oxidized into the remaining portion of the barrier portion 104, thereby forming the final storage portion 103.
In some embodiments, after forming the plurality of barrier portions 104, a conductive layer may be filled in the voids via the gate slits in a suitable step, and the conductive layer may serve as a gate layer of the three-dimensional memory.
In some embodiments, after removing the remaining portion of the sacrificial layer 102, the etch stop layer 130 may be removed using a suitable etch process to expose the charge storage portion 103-2 on a side facing away from the channel hole 110, and then at least a portion of the charge storage portion 103-2 may be oxidized to the blocking portion 104 by a thermal oxidation process and/or a chemical oxidation process, for example, the thermal oxidation may include an in-situ steam method that uses oxygen and hydrogen to generate water in vapor form. The device structure formed by the method for manufacturing a three-dimensional memory according to the second embodiment may be the same as the structure of the three-dimensional memory 100 according to the first embodiment, and will not be described in detail herein.
The above description is only an embodiment of the present application and an illustration of the technical principles applied. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.
Claims (21)
1. A method of fabricating a three-dimensional memory, comprising:
forming a stack layer on a substrate, wherein the stack layer comprises dielectric layers and sacrificial layers which are alternately stacked;
forming a trench hole through the stacked layers;
removing at least a portion of the sacrificial layer through the channel hole to form a recess;
forming a charge storage portion in the recess, the charge storage portion being disposed between adjacent ones of the dielectric layers;
removing the remaining portion of the sacrificial layer to expose the charge storage portion; and
oxidizing at least a portion of the exposed charge storage portion to a blocking portion.
2. The method of manufacturing of claim 1, further comprising: forming a gate slit through the stacked layers;
wherein the step of removing the remaining portion of the sacrificial layer to expose the charge storage portion comprises:
removing the remaining portion of the sacrificial layer through the gate slit to expose the charge storage portion.
3. The method of manufacturing of claim 2, further comprising:
filling a conductive layer in a void formed due to the removal of the remaining portion of the sacrificial layer through the gate slit.
4. The manufacturing method according to claim 1, wherein before the forming of the charge storage portion, the method further comprises:
and forming an etching stop layer on the part of the sacrificial layer, which is positioned on the side wall of the recess, wherein the etching stop layer comprises polycrystalline silicon.
5. The manufacturing method according to claim 4, wherein forming the etch stop layer comprises:
forming an initial etch stop layer on the sacrificial layer and the walls of the dielectric layer exposed to the channel hole; and
and removing the part of the initial etching stop layer on the wall of the dielectric layer so as to form the etching stop layer on the part of the sacrificial layer on the side wall of the recess.
6. The manufacturing method according to claim 1, wherein the sacrificial layer has a predetermined first etching selection ratio with respect to the charge storage portion to retain the charge storage portion when the sacrificial layer is removed.
7. The manufacturing method according to any one of claims 1 to 6, wherein forming the charge storage portion includes:
forming a storage layer in the recess and on the side wall of the dielectric layer; and
and removing the part of the storage layer on the side wall of the dielectric layer so as to form a plurality of discrete charge storage parts in the recess.
8. The manufacturing method according to claim 1, wherein a chemical vapor deposition process is performed to form the stacked layers, and an atomic layer deposition is performed to form the charge storage portion.
9. The method of manufacturing of claim 1, wherein prior to removing the remaining portion of the sacrificial layer, the method further comprises:
a tunneling layer, a channel layer, and a dielectric core are sequentially deposited along a sidewall of the channel hole.
10. The manufacturing method according to claim 4 or 5, wherein removing the remaining portion of the sacrificial layer comprises:
etching the rest part of the sacrificial layer and stopping at the etching stopping layer; and
and removing the etching stop layer.
11. A method of fabricating a three-dimensional memory, comprising:
forming a stack layer on a substrate, wherein the stack layer comprises dielectric layers and sacrificial layers which are alternately stacked;
forming a trench hole through the stacked layers;
removing at least a portion of the sacrificial layer through the channel hole to form a recess;
forming an etching stop layer on the side wall of the sacrificial layer;
forming a charge storage portion within the recess, wherein the charge storage portion covers sidewalls of the etch stop layer;
removing the rest part of the sacrificial layer to expose the etching stop layer; and
the etch stop layer is oxidized to at least a portion of the barrier portion.
12. The method of manufacturing according to claim 11, wherein forming the etch stop layer comprises:
forming an initial etch stop layer on the sacrificial layer and the walls of the dielectric layer exposed to the channel hole; and
and removing the part of the initial etching stop layer on the wall of the dielectric layer so as to form the etching stop layer on the part of the sacrificial layer on the side wall of the recess.
13. The method of manufacturing according to claim 12, wherein the forming the charge storage portion within the recess comprises:
forming a storage layer in the recess and on the side wall of the dielectric layer; and
and removing the part of the storage layer positioned on the side wall of the dielectric layer so as to form the charge storage part in the recess.
14. The method of manufacturing according to claim 11, wherein the sacrificial layer has a predetermined second etch selectivity with respect to the etch stop layer to remain the etch stop layer when the sacrificial layer is removed.
15. The manufacturing method according to claim 11, wherein a chemical vapor deposition process is performed to form the stacked layers, and an atomic layer deposition is performed to form the charge storage portion.
16. The method of manufacturing of claim 11, wherein prior to removing the remaining portion of the sacrificial layer, the method further comprises:
a tunneling layer, a channel layer, and a dielectric core are sequentially deposited along a sidewall of the channel hole.
17. The method of manufacturing according to claim 11, wherein oxidizing the etch stop layer into at least a portion of the barrier portion comprises:
oxidizing the etch stop layer to be part of the barrier portion; and simultaneously oxidizing a portion of the charge storage portion to a remaining portion of the blocking portion.
18. A three-dimensional memory comprising:
the stacked structure comprises conductive layers and dielectric layers which are stacked alternately; and
a channel structure having a first portion passing through the stacked structure and a plurality of second portions disposed between adjacent ones of the dielectric layers, the second portions comprising:
a plurality of blocking portions covering sidewalls of the respective conductive layers facing the first portion; and
a plurality of storage portions covering sidewalls of the respective blocking portions facing the first portion.
19. The three-dimensional memory of claim 18, further comprising:
a gate slit structure including an insulating layer formed in a gate slit that penetrates the memory stack structure and a conductive channel formed on the insulating layer.
20. The three-dimensional memory according to claim 18, wherein the first portion comprises a tunneling layer, a channel layer, and a dielectric core sequentially stacked on sidewalls of the dielectric layer and the storage portion.
21. The three-dimensional memory according to claim 18, wherein the barrier portion comprises silicon oxynitride or silicon oxide, and the storage portion comprises silicon nitride.
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| US20210265372A1 (en) * | 2020-02-26 | 2021-08-26 | Sandisk Technologies Llc | Three-dimensional memory device including molybdenum word lines and metal oxide spacers and method of making the same |
| CN111466024A (en) * | 2020-03-16 | 2020-07-28 | 长江存储科技有限责任公司 | Memory device and method of forming a memory device |
| CN111244096A (en) * | 2020-03-27 | 2020-06-05 | 长江存储科技有限责任公司 | 3D NAND memory device and method of manufacturing the same |
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| CN116528589A (en) * | 2023-06-01 | 2023-08-01 | 联和存储科技(江苏)有限公司 | 3D NAND flash memory device and manufacturing method thereof |
| CN116528589B (en) * | 2023-06-01 | 2023-11-03 | 联和存储科技(江苏)有限公司 | 3D NAND flash memory device and manufacturing method thereof |
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