CN209045565U - A kind of groove-shaped insulated gate bipolar transistor device architecture - Google Patents
A kind of groove-shaped insulated gate bipolar transistor device architecture Download PDFInfo
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- CN209045565U CN209045565U CN201822171038.1U CN201822171038U CN209045565U CN 209045565 U CN209045565 U CN 209045565U CN 201822171038 U CN201822171038 U CN 201822171038U CN 209045565 U CN209045565 U CN 209045565U
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Abstract
A kind of groove-shaped insulated gate bipolar transistor device architecture, includes: trench area, polysilicon gate, semiconductor substrate；Polysilicon gate is located in trench area, and polysilicon gate extremely groove structure, trench area is set in the semiconductor substrate, the grid structure of polysilicon gate protrusion p-type epi-layer surface is formed at the top of trench area, polysilicon gate and N+ emitter region are seamlessly connected in trench area.The grid structure of p-type epi-layer surface 1-2um is protruded by polysilicon upper surface, so that polysilicon gate and N+ emitter region are seamlessly connected in trench area, reduce the overlapping area between emitter and polysilicon gate, reduce gate-source capacitance, reduce switching delay time, the switch dynamic loss for reducing device, improves switching characteristic.
Description
Technical field
The present invention relates to a kind of groove-shaped insulated gate bipolar transistor device architectures.
Background technique
Insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, hereinafter referred to as IGBT) is one
The Darlington configuration that kind combines metal oxide semiconductor field effect tube (MOSFET) and bipolar junction transistor (BJT)
Semiconductor power device, have voltage control, input impedance is big, driving power is small, conducting resistance is small, switching loss is low and work
The characteristics such as working frequency height, are more satisfactory semiconductor power switch devices, and switching frequency has between 10K-100K Hz
Wide development and application prospect.
Higher and higher now with the requirement of IGBT current density, the requirement to trench process is also higher and higher.Volume production at present
Groove-shaped IGBT be all using first carrying out etching groove, then regrowth polysilicon after etching is completed carries out polysilicon quarter
The process sequence of erosion.In order to ensure the polysilicon of surface of silicon can be etched completely, usually in polycrystalline silicon etching process
Over etching all has been carried out to polysilicon.Meeting is done so so that the sunk shape of polysilicon upper surface presentation, be easy to cause N+ to send out
The vertical overlapping area penetrated between area and trench gate is less than normal, so that conducting resistance increases, to increase IGBT on-state loss.It is existing
There is technique in order to solve this problem, be usually taken and increase N+ emitter region Implantation Energy, it is longer to push away the trap time, forms deeper N+ hair
Area's junction depth is penetrated, is overlapped with this to ensure that N+ emitter region is vertical with polysilicon gate, but do so and often make gate-source capacitance excessive,
Increase the switching loss of IGBT.In addition, in the formation process of existing carrier accumulation layer, it is former using high-energy injection phosphorus
Son, the doping concentration of N-type carrier is in Gaussian Profile in carrier accumulation layer, and the pattern of concentration distribution is easy with hangover
The peak concentration of p-well region in sequent surface MOS structure is impacted, to cause the unstability of threshold voltage, influences device
The conduction voltage drop of part also reduces the reliability of device.
Summary of the invention
The purpose of the present invention is to solve disadvantages existing in the prior art, and a kind of groove-shaped insulated gate proposed is double
Gated transistors device architecture.
To achieve the goals above, present invention employs following technical solutions: a kind of groove-shaped insulated gate bipolar transistor
Device architecture includes: trench area, polysilicon gate, semiconductor substrate；Polysilicon gate is located in trench area, polysilicon gate
For groove structure, trench area is set in the semiconductor substrate,
The grid structure of polysilicon gate protrusion p-type epi-layer surface, polysilicon gate in trench area are formed at the top of trench area
It is seamlessly connected with N+ emitter region.
Further, semiconductor substrate is N- silicon substrate, forms that thickness is controllable and the uniform N-type of bulk concentration on N- silicon substrate
Epitaxial layer.
Further, it is controllable that thickness is formed in the N-type epitaxy layer, the p-type epitaxial layer of even concentration.
Further, polysilicon gate through N-type epitaxy layer and p-type epitaxial layer and is arranged in N- silicon substrate, and convex
For p-type epi-layer surface 1-2 um；
Further, the two-layer epitaxial layer structure of N-type epitaxy layer and p-type epitaxial layer is used on N- silicon substrate, and outside p-type
Prolong the surface MOS structure that IGBT is formed on layer.
Further, the polysilicon of N-type high-dopant concentration is filled in the groove of polysilicon gate；The ditch of polysilicon gate
Groove depth is 3-6 um, and cross-sectional width is 0.5-2 um；The doping concentration of polysilicon is 5E19-5E20 cm-3。
Further, N+ emitter region is formed in p-type epi-layer surface, and is connected with the two sides of polysilicon gate, shape
At electronic conduction channel；The deep-well region P+ is formed among the N+ emitter region between two trench areas；Silicon dioxide blocking layer is formed
In p-type epi-layer surface；Silicon dioxide insulator dielectric layer is formed in silicon dioxide blocking layer and polysilicon gate pole surface；Polycrystalline
Silicon gate is formed in below emitter electrode, and silicon dioxide insulator dielectric layer is formed between polysilicon layer and emitter metal；N
Type field terminator is formed in the N- silicon substrate back side, p-type collector area and N-type field terminator rear-face contact；Emitter electrode is formed
In on N+ emitter region, the deep-well region P+ and silicon dioxide insulator dielectric layer；Backside collector is formed in the back side of p-type collector area；
Gate oxide is formed in the inner wall of trench area.
Further, the doping concentration of N- silicon substrate is 1E13-2E14 cm-3, with a thickness of 60-500 um.
Further, p-type epitaxial layer with a thickness of 3-8 um, doping concentration is 1E16-8E17 cm-3；N-type epitaxy layer
With a thickness of 1-5 um, doping concentration is 1E14-1E16 cm-3。
Further, the doping concentration of N+ emitter region is 1E19-5E20 cm-3, junction depth is 0.2-1 um；The deep-well region P+
Doping concentration is 1E19-5E20 cm-3, junction depth is 0.5-1 um；The deep-well region P+ and N+ emitter region overlap 0.5 um；P-type collector
Doping concentration be 1E18-5E19 cm-3, junction depth is 0.2-1 um；The doping concentration of N-type field terminator is 5E15-5E16 cm-3, junction depth is 1-2 um.
The beneficial effects of the present invention are: the polysilicon gate construction of polysilicon protrusion p-type epi-layer surface 1-2um is formed,
So that polysilicon gate and N+ emitter region are seamlessly connected in trench area, reduce the overlapping face between emitter and polysilicon gate
Product, reduces gate-source capacitance, reduces switching delay time, reduce the switch dynamic loss of device, improve switching characteristic；
And two-layer epitaxial layer is used, formation thickness is controllable, and the uniform N-type epitaxy layer of bulk concentration avoids carrier accumulation layer concentration
Distribution impacts the peak concentration of p-well region in the MOS structure of surface, and then influences threshold voltage and conduction voltage drop.Using double
Layer epitaxial layer structure both ensure that the consistency of threshold voltage and on state voltage, also reduce the on state voltage of device；Simultaneously
So that the metallurgical junction between p-type epitaxial layer and N-type epitaxy layer is more gentle, device longitudinal direction cellular region breakdown voltage is increased.
Detailed description of the invention
Fig. 1 is schematic structural view of the invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention 1, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.
Referring to Fig.1, a kind of groove-shaped insulated gate bipolar transistor device architecture, including trench area 290, polysilicon gate
292, p-type epitaxial layer 251, semiconductor substrate 240 and N+ emitter region 260；Polysilicon gate 292 is located in trench area 290, polycrystalline
Silicon gate 292 is groove structure, and trench area 290 is located in semiconductor substrate 240,
The grid structure that polysilicon gate 292 protrudes 251 surface of p-type epitaxial layer, trench area 290 are formed at the top of trench area 290
Interior polysilicon gate 292 is seamlessly connected with N+ emitter region 260.
A kind of groove-shaped insulated gate bipolar transistor device architecture, semiconductor substrate 240 is N- silicon substrate, on N- silicon substrate
Form that thickness is controllable and the uniform N-type epitaxy layer 250 of bulk concentration.N-type epitaxy layer 250, concentration 1E14-1E16cm-3, with a thickness of
1-5um.Reduction conduction voltage drop has been played, has guaranteed the effect of the consistency of threshold voltage and on state voltage.
A kind of groove-shaped insulated gate bipolar transistor device architecture, formation thickness is controllable in the N-type epitaxy layer, concentration
Uniform p-type epitaxial layer.
A kind of groove-shaped insulated gate bipolar transistor device architecture, p-type epitaxial layer 251 are formed in 250 table of N-type epitaxy layer
Face；Polysilicon gate 292 is through N-type epitaxy layer 250, p-type epitaxial layer 251 and is located in N- silicon substrate, and protrudes from p-type
The surface 1-2 um of epitaxial layer 251；The polysilicon of N-type high-dopant concentration is filled in the groove of polysilicon gate 292；Polysilicon
The trench depth of grid 292 is 3-6 um, and cross-sectional width is 0.5-2 um；The doping concentration of polysilicon is 5E19-5E20
cm-3。
A kind of groove-shaped insulated gate bipolar transistor device architecture, N+ emitter region 260 are formed in 251 surface of p-type epitaxial layer,
And be connected with the two sides of polysilicon gate 292, form electronic conduction channel；The deep-well region P+ 252 is formed in two polysilicons
Among N+ emitter region 260 between grid 292；Silicon dioxide blocking layer 271 is formed in 251 surface of p-type epitaxial layer；Silica
Insulating medium layer 270 is formed in 292 surface of silicon dioxide blocking layer 271 and polysilicon gate；N-type field terminator 230 is formed in
The N- silicon substrate back side, p-type collector area 220 and 230 rear-face contact of N-type field terminator；Emitter electrode 280 is formed in N+ transmitting
On area, the deep-well region P+ 252 and silicon dioxide insulator dielectric layer 270；Backside collector 210 is formed in the back of p-type collector area 220
Face；Gate oxide 291 is formed in the inner wall of trench area 290.Gate oxide 291 with a thickness of 1000-1500.Polysilicon gate
292 below emitter electrode 280, silicon dioxide insulator dielectric layer 270 polysilicon gate 292 and emitter electrode 280 it
Between.
A kind of groove-shaped insulated gate bipolar transistor device architecture uses N-type epitaxy layer and p-type epitaxial layer on N- silicon substrate
Two-layer epitaxial layer structure, and on p-type epitaxial layer formed IGBT surface MOS structure.
A kind of groove-shaped insulated gate bipolar transistor device architecture, the doping concentration of N- silicon substrate are 1E13-2E14 cm-3,
Ensure IGBT device withstanding voltage.
A kind of groove-shaped insulated gate bipolar transistor device architecture, p-type epitaxial layer 251 with a thickness of 1-5 um, adulterate dense
Degree is 1E16-8E17 cm-3.Concentration setting combines the thickness of 292 side wall gate oxide 291 of polysilicon gate, it is ensured that IGBT threshold
Threshold voltage has enough safe clearances in 5V or more.
A kind of groove-shaped insulated gate bipolar transistor device architecture, the doping concentration of N+ emitter region are 1E19-5E20 cm-3,
Junction depth is 0.2-1 um；Since N+ emitter region and the deep-well region P+ are overlapping, it is ensured that contact resistance is small.N+ emitter region and conducting channel connect
It is logical, guarantee electronic current access.
The doping concentration of the deep-well region P+ is 1E19-5E20 cm-3, junction depth is 0.5-1 um；The deep-well region P+ 252 and N+ transmitting
Area 260 overlaps 0.5 um, to ensure that contact resistance is sufficiently small；
The doping concentration of p-type collector is 1E18-5E19 cm-3, junction depth 0.2-1um；Play control hole emission efficiency
Effect.
The doping concentration of N-type field terminator is 5E15-5E16 cm-3, junction depth is 1-2 um.Can reach improves IGBT folding
Middle characteristic, the effect of current tail time when reducing IGBT shutdown.
A kind of groove-shaped insulated gate bipolar transistor device architecture, trench area are equipped with groove array, the groove of groove array
In be equipped with polysilicon gate.
The specific implementation step of production process: a kind of groove-shaped insulated gate bipolar transistor device architecture has in the device
By arsenic ion injection, simultaneously high temperature pushes away trap technique formation N+ emitter region 260 on p-type epitaxial layer 251 in source region.N+ emitter region 260
Doping concentration be 1E19-5E20 cm-3, junction depth is 0.2-1 um.
A kind of groove-shaped insulated gate bipolar transistor device architecture, is formed in the device active region by lithography and etching
Groove array.Specifically, on p-type epitaxial layer 251 by high temperature oxidation process grow layer of silicon dioxide barrier layer 271, two
The thickness of silica barrier layer can be 5000-10000, serve as the barrier layer of etching groove；In silicon dioxide blocking layer 271
Upper coating photoresist carries out groove domain exposure and imaging, forms the photoresist layer figure for defining trench area 290；Then it uses
The photoresist layer figure carries out wet etching to silicon dioxide blocking layer as mask, removes exposed silicon dioxide blocking layer；
Then wet etching removes photoresist, forms the silica layer pattern for defining trench area 290；Then the silicon dioxide layer is used
Figure performs etching p-type epitaxial layer, N-type epitaxy layer and N- silicon substrate as mask, i.e., deep-cuts multiple ditches through epitaxial layer
Slot forms groove array.Wherein, the depth of groove is 3-8 um, and cross-sectional width is 0.5-2 um.
Growth has gate oxide 291 of the higher silica of compactness as MOS structure in the active area of the device.
Specifically, it first passes through high-temperature oxydation and grows one layer of sacrificial oxide layer, then benefit on 251 surface of p-type epitaxial layer and 290 inner wall of trench area
Fall the sacrificial oxide layer with wet etching, to ensure the smooth of plane gate oxide and groove gate oxide；Pass through high temperature
Aoxidize the gate oxide 291 on 251 surface of p-type epitaxial layer and 290 inner wall of trench area growth MOS structure.Wherein gate oxide 291
With a thickness of 1000-1500；Aforesaid operations step is in order to reduce crystal defect and impurity, so that it is preferable to grow compactness
Gate oxide 291；
Polysilicon gate 292 is formed in the active area of the device.Specifically, first in 291 surface of gate oxide and groove
Deposit conducting mediums in 290, conducting medium can be polycrystalline silicon material, polysilicon with a thickness of 1-1.5 um；Then chemistry is carried out
Mechanical lapping, removes the polysilicon on 271 surface of silicon dioxide blocking layer, and chemical mechanical grinding stops at silicon dioxide blocking layer
271 surfaces only retain the polysilicon of 290 the inside of trench area.Made on polysilicon gate by chemical mechanical milling tech in this way
Protrude 251 surface 1-2 um of p-type epitaxial layer in surface.So that polysilicon gate and N+ emitter region are seamlessly connected in groove, reduce
Overlapping area between emitter and polysilicon gate, reduces gate-source capacitance, reduces switching delay time, reduces device
Switch dynamic loss, improve switching characteristic.
The deep-well region P+ 252 is formed between N+ emitter region 260.Specifically, by high-temperature oxydation in silicon dioxide blocking layer
The silicon dioxide insulator dielectric layer 270 of 271 and 292 surface of polysilicon gate growth 5000-10000；In silicon dioxide insulator
Coating photoresist on dielectric layer 270 carries out contact domain exposure and imaging, forms photoresist layer figure；Use the photoresist layer
Figure as mask, in N+ emitter region 260 silicon dioxide blocking layer 271 and silicon dioxide insulator dielectric layer 270 carve
Erosion forms contact hole；Wet etching removes photoresist；Using silicon dioxide insulator medium layer pattern as barrier layer, emitted by N+
Contact hole between area 260 injects boron ion into N+ emitter region highly doped silicon, forms the high-doped zone P+, the i.e. deep-well region P+ 252.
Wherein, the thickness of silicon dioxide insulator dielectric layer 270 can be 5000-10000；Boron ion Implantation Energy is 50-120
Kev, dosage are 1E15-8E15 cm-2, the doping concentration of the deep-well region P+ 252 is 1E19-5E20 cm-3, junction depth is 0.5-1 um.
Due to the overlapping setting of highly doped N+ emitter region 260 and the deep-well region P+ 252, the contact zone for collectively forming IGBT emitter ensures to connect
Electric shock resistance is sufficiently small.
Front side emitter pole metal is deposited, emitter electrode 280 is formed.Specifically, a layer thickness is deposited in the device surface
For the metal film of 1-5 um, the then coating photoresist on metal film carries out photoetching using metal layer domain, exposure and imaging,
Wet process or dry etching metal are used with photoresist；Metal and the surface and are deposited in the contact hole in the device active region
Metal be connected, formed emitter electrode 280；The photoresist of wet process removal layer on surface of metal.Metal be aluminium/silicon alloy or aluminium/
Silicon/copper alloy, with a thickness of 1-5 um, and by 400 DEG C or so of heating alloying, so that emitter region highly doped silicon and front
Ohmic contact is formed between metal, reduces contact resistance.
It carries out back thinning, carries out phosphonium ion injection at 240 back side of N- silicon substrate and high temperature pushes away trap technique and forms N-type field end
Only area 230；Wherein, the doping concentration of N-type field terminator 230 can be 5E15-1E17 cm-3, junction depth is 1-2 um, Neng Gouda
To IGBT compromise characteristic is improved, the effect of current tail time when IGBT is turned off is reduced.
Trap technique is pushed away by boron ion injection and high temperature at the back side of N-type field terminator 230 and forms p-type collector area 220.
Wherein, the doping concentration of p-type collector area 220 is 1E18-5E19 cm-3, depth is 0.2-1 um, reaches control hole emission
The effect of efficiency.
Backside collector 210 is formed by metal sputtering at 220 back side of p-type collector area.
More than, it is merely preferred embodiments of the present invention, but scope of protection of the present invention is not limited thereto, it is any
Those familiar with the art in the technical scope disclosed by the present invention, according to the technique and scheme of the present invention and its invents
Design is subject to equivalent substitution or change, should be covered by the protection scope of the present invention.
Claims (10)
1. a kind of groove-shaped insulated gate bipolar transistor device architecture, includes: trench area, polysilicon gate, semiconductor substrate；It is more
Polysilicon gate is located in trench area, and polysilicon gate extremely groove structure, trench area is set in the semiconductor substrate, it is characterised in that:
The grid structure of polysilicon gate protrusion p-type epi-layer surface, polysilicon gate and N+ in trench area are formed at the top of trench area
Emitter region seamless connection.
2. a kind of groove-shaped insulated gate bipolar transistor device architecture according to claim 1, it is characterised in that: semiconductor
Substrate is N- silicon substrate, forms that thickness is controllable and the uniform N-type epitaxy layer of bulk concentration on N- silicon substrate.
3. a kind of groove-shaped insulated gate bipolar transistor device architecture according to claim 2, it is characterised in that: described
It is controllable that thickness is formed in N-type epitaxy layer, the p-type epitaxial layer of even concentration.
4. a kind of groove-shaped insulated gate bipolar transistor device architecture according to claim 3, it is characterised in that: polysilicon
Grid is through N-type epitaxy layer and p-type epitaxial layer and is arranged in N- silicon substrate, and protrudes from p-type epi-layer surface 1-2 um.
5. a kind of groove-shaped insulated gate bipolar transistor device architecture according to claim 4, it is characterised in that: N- silicon lining
The two-layer epitaxial layer structure of N-type epitaxy layer and p-type epitaxial layer is used on bottom, and the surface MOS of IGBT is formed on p-type epitaxial layer
Structure.
6. a kind of groove-shaped insulated gate bipolar transistor device architecture according to claim 1 or 5, it is characterised in that: more
The polysilicon of N-type high-dopant concentration is filled in the groove of polysilicon gate；The trench depth of polysilicon gate is 3-6 um, transversal
Face width is 0.5-2 um；The doping concentration of polysilicon is 5E19-5E20cm-3。
7. a kind of groove-shaped insulated gate bipolar transistor device architecture according to claim 5, it is characterised in that: N+ transmitting
Area is formed in p-type epi-layer surface, and is connected with the two sides of polysilicon gate, forms electronic conduction channel；The deep-well region P+
It is formed among the N+ emitter region between two trench areas；Silicon dioxide blocking layer is formed in p-type epi-layer surface；Silica
Insulating medium layer is formed in the silicon dioxide blocking layer and polysilicon gate pole surface；Polysilicon gate is formed in emitter electricity
Below pole, silicon dioxide insulator dielectric layer is formed between polysilicon layer and emitter metal；N-type field terminator is formed in N- silicon
Substrate back, p-type collector area and N-type field terminator rear-face contact；Emitter electrode be formed in N+ emitter region, the deep-well region P+ and
On silicon dioxide insulator dielectric layer；Backside collector is formed in the back side of p-type collector area；Gate oxide is formed in trench area
Inner wall.
8. a kind of groove-shaped insulated gate bipolar transistor device architecture according to claim 2, it is characterised in that: N- silicon lining
The doping concentration at bottom is 1E13-2E14 cm-3, with a thickness of 60-500 um.
9. a kind of groove-shaped insulated gate bipolar transistor device architecture according to claim 5, it is characterised in that: outside p-type
Prolong layer with a thickness of 3-8 um, doping concentration is 1E16-8E17 cm-3；N-type epitaxy layer with a thickness of 1-5 um, doping concentration
For 1E14-1E16 cm-3。
10. a kind of groove-shaped insulated gate bipolar transistor device architecture according to claim 7, it is characterised in that: N+ hair
The doping concentration for penetrating area is 1E19-5E20 cm-3, junction depth is 0.2-1 um；The doping concentration of the deep-well region P+ is in 1E19-5E20
cm-3, junction depth is 0.5-1 um；The deep-well region P+ and N+ emitter region overlap 0.5 um；The doping concentration of p-type collector is 1E18-
5E19 cm-3, junction depth 0.2-1um；The doping concentration of N-type field terminator is 5E15-5E16 cm-3, junction depth is 1-2 um.
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| CN110718586A (en) * | 2019-10-24 | 2020-01-21 | 上海擎茂微电子科技有限公司 | Anti-latch-up trench type insulated gate transistor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110718586A (en) * | 2019-10-24 | 2020-01-21 | 上海擎茂微电子科技有限公司 | Anti-latch-up trench type insulated gate transistor device |
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