CN112366227A - Insulated gate bipolar transistor and preparation method thereof - Google Patents
Insulated gate bipolar transistor and preparation method thereof Download PDFInfo
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Abstract
The invention provides an insulated gate bipolar transistor and a preparation method thereof, wherein the insulated gate bipolar transistor comprises an N-drift region (4), a P-type base region (5), a P-type buried layer (11) and an N + emitter region (6); the P-type base region (5) is positioned on two sides of the upper surface of the N-drift region (4), the N + emitter region (6) is positioned on the upper surface of the P-type base region (5), and a set distance is reserved between the N + emitter region and the outer side of the P-type base region (5); the P-type buried layer (11) is positioned in the P-type base region (5) below the N + emitter region (6), the P-type buried layer (11) effectively inhibits the latch-up effect of the insulated gate bipolar transistor, improves the high-current turn-off capability of the insulated gate bipolar transistor and has better robustness; the Schottky contact can improve the carrier concentration on the surface of the insulated gate bipolar transistor and greatly enhance the conductance modulation effect, so that the conduction voltage drop of the insulated gate bipolar transistor is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an insulated gate bipolar transistor and a preparation method thereof.
Background
The power semiconductor device is used as a core element in a power electronic system, and is an indispensable important electronic element. Insulated Gate Bipolar Transistors (IGBTs) are an improved type of power device that can replace bipolar junction power transistors. As a new generation of power electronic devices, IGBTs have the advantages of easy driving of MOSFETs, low input impedance, and high switching speed due to the combination of the advantages of field effect transistors (MOSFETs) and Bipolar Junction Transistors (BJTs), and also have the advantages of high current density of BJTs on state, reduced on-state voltage, low loss, and good stability, and thus have been developed as one of the core electronic components in modern power electronic circuits, and have been widely applied to various fields such as transportation, communication, home appliances, and aerospace, and the application of IGBTs has also greatly improved the performance of power electronic systems.
The effective reduction of the switching loss of the IGBT and the reduction of the conduction voltage drop of the device have been the key points of the IGBT research, and the IGBTs are classified into planar IGBTs and trench IGBTs according to the structure. The existing plane type IGBT has the problem of high conduction voltage drop, and meanwhile, latch-up effect may occur when the plane type IGBT works, so that the plane type IGBT cannot work normally, and the firmness is low.
Disclosure of Invention
In order to overcome the defects that the IGBT in the prior art is easy to have latch-up effect and poor in firmness, the invention provides an insulated gate bipolar transistor which is characterized by comprising an N-drift region (4), a P-type base region (5), a P-type buried layer (11) and an N + emitter region (6);
the P-type base region (5) is positioned on two sides of the upper surface of the N-drift region (4), the N + emitter region (6) is positioned on the upper surface of the P-type base region (5), and a set distance is reserved between the N + emitter region and the outer side of the P-type base region (5);
the P-type buried layer (11) is positioned in the P-type base region (5) below the N + emitter region (6).
And the upper surfaces of the N + emitter region (6) and the outer side of the P-type base region (5) are also provided with emitters (7).
The emitter (7) comprises a first emitter (71) and a second emitter (72) connected to each other;
the first emitter (71) is positioned on the upper surface of the outer side of the P-type base region (5) and forms Schottky contact with the P-type base region (5);
the second emitter (72) is positioned on the upper surface of the N + emission region (6) and is in contact connection with a part of the N + emission region (6) to form ohmic contact.
A super-junction P column (12) is further arranged at the inner edge position of the N-drift region (4) below the P-type base region (5);
and a super-junction N column (13) is also arranged between the super-junction P columns (12).
The middle position of the upper surface of the N-drift region (4) further comprises: a grid electrode (8) and a grid dielectric layer (9) which are arranged up and down.
The doping concentration of the P-type buried layer (11) is greater than that of the P-type base region (5).
The N + emission region (6) is formed by adopting an N-type wide bandgap semiconductor material;
the N-type wide bandgap semiconductor material is SiC, GaAs or GaN.
The junction depth of the super junction P column (12) is less than or equal to that of the super junction N column (13);
the doping concentration of the super junction P column (12) is 1 x 1015cm-3～1×1016cm-3；
The doping concentration of the super junction N column (13) is 5 multiplied by 1012cm-3～2×1016cm-3。
The first emitter (71) and the second emitter (72) are made of the same metal or different metals.
In another aspect, the present invention further provides a method for manufacturing an insulated gate bipolar transistor, including:
forming P-type base regions (5) on two sides of the upper surface of the N-drift region (4);
forming a P-type buried layer (11) in the P-type base region (5);
and an N + emitter region (6) is formed on the upper surface of the P-type base region (5) above the P-type buried layer (11) and at a set distance from the outer side of the P-type base region (5).
Form P type base region (5) in N-drift region (4) upper surface both sides, include:
and forming P-type base regions (5) on two sides of the upper surface of the N-drift region (4) by sequentially adopting a thermal oxidation process, a gluing process, a photoetching process, an ion injection process and an annealing process.
Form P type buried layer (11) in P type base region (5) inside, include:
and forming a P-type buried layer (11) in the P-type base region (5) by sequentially adopting a photoetching process and an ion implantation process.
Form N + emitter region (6) above P type buried layer (11) and apart from the upper surface of P type base region (5) that P type base region (5) outside has the setting distance, include:
forming a groove on the upper surface of the P-type base region (5) which is above the P-type buried layer (11) and has a set distance from the outer side of the P-type base region (5) by sequentially adopting a gluing process, a photoetching process and an etching process;
filling N-type wide bandgap semiconductor material in the groove by adopting a filling process;
and forming an N + emission region (6) at the position filled with the N-type wide bandgap semiconductor material by adopting an ion implantation process.
The filling process adopts a deposition process or a process combining ion implantation and annealing.
The N-type wide bandgap semiconductor material is SiC, GaAs or GaN.
After an N + emitter region (6) is formed on the upper surface of the P-type base region (5) above the P-type buried layer (11) and having a set distance from the outer side of the P-type base region (5), the method further comprises the following steps:
forming a gate dielectric layer (9) on the upper surface of the N-drift region (4) by adopting a thermal oxidation process;
and forming a grid electrode (8) on the upper surface of the grid dielectric layer (9) by adopting a deposition process.
After the gate (8) is formed on the upper surface of the gate dielectric layer (9) by adopting a deposition process, the method further comprises the following steps:
depositing front metal on the upper surface of the N + emitter region (6) and the upper surface of the outer side of the P-type base region (5) by adopting a metal material;
and respectively annealing the front metal on the upper surface of the N + emitter region (6) and the front metal on the upper surface of the outer side of the P-type base region (5) by sequentially adopting a photoetching process, an etching process and an annealing process to form a first emitter (71) and a second emitter (72).
Before forming the P-type base region (5) on two sides of the upper surface of the N-drift region (4), the method further comprises the following steps:
and a super-junction P column (12) is formed at the inner edge position of the N-drift region (4) below the P-type base region (5) by sequentially adopting an etching process and an epitaxial process, and a super-junction N column (13) is formed between the super-junction P columns (12) by sequentially adopting the etching process and the epitaxial process.
The technical scheme provided by the invention has the following beneficial effects:
the insulated gate bipolar transistor provided by the invention comprises an N-drift region (4), a P-type base region (5), a P-type buried layer (11) and an N + emitter region (6); the P-type base region (5) is positioned on two sides of the upper surface of the N-drift region (4), the N + emitter region (6) is positioned on the upper surface of the P-type base region (5), and a set distance is reserved between the N + emitter region and the outer side of the P-type base region (5); the P-type buried layer (11) is positioned in the P-type base region (5) below the N + emitter region (6), and the latch-up effect of the insulated gate bipolar transistor is effectively inhibited by arranging the P-type buried layer (11) in the P-type base region (5), so that the insulated gate bipolar transistor has better robustness;
in the invention, Schottky contact is formed between the first emitter and the P-type base region, ohmic contact is formed between the second emitter and the N + emitter region, the first emitter and the second emitter can be made of the same metal or different metals, the Schottky contact can form a hole barrier, and holes hardly cross the barrier, so that the carrier concentration on the surface of the insulated gate bipolar transistor can be improved, the distribution of carriers in a drift region of the insulated gate bipolar transistor is further improved, the conductance modulation effect is greatly enhanced, and the conduction voltage drop of the insulated gate bipolar transistor is reduced;
according to the invention, Schottky contact formed between the first emitter and the P-type base region can form a hole barrier, and holes can be blocked near the drift region, so that the carrier concentration in the drift region is increased, and the distribution of carriers in the drift region of the insulated gate bipolar transistor is further improved, thereby enhancing the conductivity modulation effect and reducing the conduction voltage drop;
the P-type buried layer can reduce parasitic resistance formed by the P-type base region, reduce voltage drop formed by hole current in the P-type base region, further inhibit dynamic latch possibly generated by the insulated gate bipolar transistor and improve the high-current turn-off capability of the insulated gate bipolar transistor;
the N + emitter region (6) is formed by adopting an N-type wide bandgap semiconductor material, a special-shaped heterojunction is formed on the junction surface between the N + emitter region 6 and the P-type base region 5, the introduction of the special-shaped heterojunction enables the conduction voltage drop of the PN junction between the N + emitter region 6 and the P-type base region 5 to be greatly increased, the latch-up resistance of the insulated gate bipolar transistor is improved, the negative influence caused by Schottky contact is reduced, and the forward conduction characteristic of the insulated gate bipolar transistor can be further improved;
according to the invention, the threshold voltage of the insulated gate bipolar transistor and the height of a hole barrier formed by the Schottky contact can be adjusted by adjusting the doping concentration of the P-type base region, so that the influence of the Schottky contact on the threshold voltage of the insulated gate bipolar transistor is reduced.
The preparation method of the insulated gate bipolar transistor provided by the invention has the advantages of simple and controllable process and strong compatibility with the existing process.
Drawings
Fig. 1 is a structural view of an insulated gate bipolar transistor including a P-type buried layer in an embodiment of the present invention;
fig. 2 is a structural view of an insulated gate bipolar transistor including a P-type buried layer, a super junction P column, and a super junction N column in an embodiment of the present invention;
FIG. 3 is a band diagram after forming a heterojunction in an embodiment of the invention;
FIG. 4 is a flow chart of a method of fabricating an insulated gate bipolar transistor according to an embodiment of the present invention;
in the figure, 1, a collector, 2, a P + collector region, 3, an N-type field stop layer, 4, an N-drift region, 5, a P-type base region, 6, an N + emitter region, 7, an emitter, 71, a first emitter, 72, a second emitter, 8, a grid, 9, a grid dielectric layer, 11, a P-type buried layer and 12 are super-junction P columns, and 13 is a super-junction N column.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
Example 1
Embodiment 1 of the present invention provides an insulated gate bipolar transistor, as shown in fig. 1, including an N-drift region 4, a P-type base region 5, a P-type buried layer 11, and an N + emitter region 6;
the P-type base region 5 is positioned on two sides of the upper surface of the N-drift region 4, the N + emitter region 6 is positioned on the upper surface of the P-type base region 5, and a set distance is reserved between the N + emitter region and the outer side of the P-type base region 5;
the P-type buried layer 11 is positioned inside the P-type base region 5 below the N + emitter region 6.
In the insulated gate bipolar transistor provided in embodiment 1 of the present invention, the upper surface of the N + emitter region 6 and the upper surface of the outer side of the P-type base region 5 are further provided with an emitter 7.
The emitter 7 includes a first emitter 71 and a second emitter 72 connected to each other;
the first emitter 71 is positioned on the outer upper surface of the P-type base region 5 and forms schottky contact with the P-type base region 5;
the second emitter 72 is located on the upper surface of the N + emitter region 6 and is in contact connection with a portion of the N + emitter region 6, forming an ohmic contact.
The first emitter 71 and the second emitter 72 are made of the same metal or different metals, and the schottky contact can form a hole barrier, and holes hardly cross the barrier, so that the carrier concentration on the surface of the insulated gate bipolar transistor can be improved, the carrier distribution in the drift region of the insulated gate bipolar transistor can be further improved, the conductance modulation effect can be greatly enhanced, and the conduction voltage drop of the insulated gate bipolar transistor is reduced.
As shown in fig. 2, in the insulated gate bipolar transistor provided in embodiment 1 of the present invention, a super junction P column 12 is further disposed at an inner edge position of the N-drift region 4 below the P-type base region 5;
and a super-junction N column 13 is also arranged between the super-junction P columns 12.
In the insulated gate bipolar transistor provided in embodiment 1 of the present invention, the middle position of the upper surface of the N — drift region 4 further includes: the grid 8 and the grid dielectric layer 9 which are arranged up and down, namely the grid 8, are positioned on the upper surface of the grid dielectric layer 9;
the gate dielectric layer 9 is located in the middle of the upper surface of the N-drift region 4, and the N-drift region 4, the P-type base region 5 between the N-drift region 4 and the N + emitter region 6 and a part of the N + emitter region 6 are sequentially covered on two sides of the gate dielectric layer from inside to outside.
The gate 8 in embodiment 1 of the present invention may be a metal gate or a polysilicon gate.
The doping concentration of the P-type buried layer 11 is greater than that of the P-type base region 5.
The N + emission region 6 is formed by adopting an N-type wide bandgap semiconductor material; the N-type wide bandgap semiconductor material is SiC, GaAs or GaN. The forbidden bandwidth of the filling material of the N + emitter region 6 is larger than that of the semiconductor material of the P-type base region 5, and the rest parts can be made of the same material or different material combinations.
The junction depth of the super junction P column 12 is less than or equal to that of the super junction N column 13; the doping concentration of the super-junction P column 12 and the super-junction N column 13 meets the charge balance requirement, and the doping concentration of the super-junction P column 12 is 1 multiplied by 1015cm-3～1×1016cm-3(ii) a The doping concentration of the super junction N column 13 is 5 x 1012cm-3～2×1016cm-3。
The doping concentration of the N-drift region 4 is 5 x 1012cm-3～2×1016cm-3The thickness is 60 to 700 μm, and the width is 10 to 100 μm;
the doping concentration of the P-type base region 5 is 3 multiplied by 1016cm-3～2×1017cm-3The doping depth is 0.5-5 μm;
n + hairThe doping concentration of the emitter region 6 is 5X 1018cm-3～1×1020cm-3The doping depth is 0.2-0.5 μm.
The insulated gate bipolar transistor provided in embodiment 1 of the present invention further includes a collector 1, a P + collector region 2, and an N-type field stop layer 3, which are sequentially disposed from bottom to top;
the collector 1, the P + collector region 2 and the N-type field stop layer 3 are all located on the back of the N-drift region 4.
The thickness of the gate dielectric layer 9 is 20-120 nm;
the thickness of the grid 8 is 0.5-1.5 μm;
the doping concentration of the N-type electric field stop layer 3 is 5X 1015cm-3～5×1017cm-3The thickness of the film is 5 to 20 μm;
the doping concentration of the P + collector region 2 is 1 multiplied by 1017cm-3～1×1019cm-3The thickness is 0.5 to 5 μm.
The principle of embodiment 1 of the present invention will be described in detail below by taking only an N-channel planar IGBT as an example, and in the description of the principle, the one having a smaller forbidden band width will be referred to as a narrow-bandgap semiconductor (with respect to the other one), and the other having a larger forbidden band width will be referred to as a wide-bandgap semiconductor (with respect to the other one). The operating principle of the insulated gate bipolar transistor provided in embodiment 1 of the present invention is as follows:
when the grid 8 is connected with a high potential higher than the threshold voltage of the insulated gate bipolar transistor, the collector 1 is connected with a high potential, and the emitter 7 is connected with a low potential, the insulated gate bipolar transistor works in a conducting state, the P + collector region 2 injects holes into the N-drift region 4, the N + emitter region 6 injects electrons into the N-drift region 4, and the existence of electron-hole pairs enables a conductance modulation effect to occur in the drift region. Meanwhile, as the first emitter 71 and the P-type base region form schottky contact, the potential of the P-type base region 5 is increased due to the schottky contact, the accumulation of surface holes is enhanced, the carrier distribution of the drift region is improved, and the forward conduction voltage drop of the insulated gate bipolar transistor is reduced. Because of the existence of the N-type wide bandgap semiconductor which forms a heterojunction with the P-type narrow bandgap semiconductor, when two semiconductor materials are in close contact to form the heterojunction, because the Fermi level of the N-type wide bandgap semiconductor material is higher than that of the P-type narrow bandgap semiconductor material, electrons flow from the former to the latter, causing the upward bending of the energy band of the N-type wide bandgap semiconductor material (i.e. Delta Ec in figure 3), the downward bending of the energy band of the P-type narrow bandgap semiconductor material (i.e. Delta Ev in figure 3), figure 3 is an energy band diagram after the heterojunction is formed, in figure 3, Delta Ec is the valence band variation of N-SiC, Delta Ev is the conduction band variation of N-SiC, and Ef is the Fermi level, so that positive charges are accumulated on one side and negative charges are accumulated on the other side of the N-type wide bandgap semiconductor material, and the electric field direction thereof is directed from one side of the N-type wide bandgap semiconductor material to one side of the P-type narrow bandgap semiconductor material, thereby causing the heterojunction to form a hole barrier. The heterojunction can increase the turn-on voltage of a PN junction between the N + emitter region 6 and the P-type base region 5, so that the latch-up resistance of the insulated gate bipolar transistor is improved, the influence of Schottky contact on the firmness of the insulated gate bipolar transistor can be effectively reduced, and the compromise characteristics of forward conduction voltage drop and turn-off loss of the insulated gate bipolar transistor are improved.
Example 2
Embodiment 2 of the present invention provides a method for manufacturing an insulated gate bipolar transistor, where a specific flowchart is shown in fig. 4, and the specific process is as follows:
s101: forming P-type base regions 5 on two sides of the upper surface of the N-drift region 4;
s102: forming a P-type buried layer 11 in the P-type base region 5;
s103: and an N + emitter region 6 is formed on the upper surface of the P-type base region 5 which is above the P-type buried layer 11 and has a set distance from the outer side of the P-type base region 5.
Forming P-type base regions 5 on two sides of the upper surface of the N-drift region 4, including:
and forming the P-type base regions 5 on two sides of the upper surface of the N-drift region 4 by sequentially adopting a thermal oxidation process, a gluing process, a photoetching process, an ion injection process and an annealing process.
Forming a P-type buried layer 11 inside the P-type base region 5, including:
and forming a P-type buried layer 11 inside the P-type base region 5 by sequentially adopting a photoetching process and an ion implantation process.
An N + emitter region 6 is formed on the upper surface of the P-type base region 5 above the P-type buried layer 11 and having a set distance from the outer side of the P-type base region 5, and includes:
forming a groove on the upper surface of the P-type base region 5 which is above the P-type buried layer 11 and has a set distance from the outer side of the P-type base region 5 by sequentially adopting a gluing process, a photoetching process and an etching process;
filling N-type wide bandgap semiconductor material in the groove by adopting a filling process;
and forming an N + emission region 6 at the position filled with the N-type wide bandgap semiconductor material by adopting an ion implantation process.
The filling process adopts a deposition process or a process combining ion implantation and annealing.
After forming the N + emitter region 6 on the upper surface of the P-type base region 5 above the P-type buried layer 11 and having a set distance from the outside of the P-type base region 5, the method further includes:
forming a gate dielectric layer 9 on the upper surface of the N-drift region 4 by adopting a thermal oxidation process;
and forming a grid electrode 8 on the upper surface of the grid dielectric layer 9 by adopting a deposition process.
After the gate 8 is formed on the upper surface of the gate dielectric layer 9 by using a deposition process, the method further includes:
adopting a metal material to deposit front metal on the upper surface of the N + emitter region 6 and the upper surface of the outer side of the P-type base region 5;
and respectively annealing the front metal on the upper surface of the N + emitter region 6 and the front metal on the upper surface of the outer side of the P-type base region 5 by sequentially adopting a photoetching process, an etching process and an annealing process to form a first emitter 71 and a second emitter 72.
Before forming the P-type base region 5 on both sides of the upper surface of the N-drift region 4, the method further includes:
and forming super-junction P columns 12 at the inner edge positions of the N-drift region 4 below the P-type base region 5 by sequentially adopting an etching process and an epitaxial process, and forming super-junction N columns 13 between the super-junction P columns 12 by sequentially adopting the etching process and the epitaxial process.
Before forming the P-type base region 5 on both sides of the upper surface of the N-drift region 4, the method further includes:
and sequentially adopting an ion implantation process and an annealing process to form an N-type field stop layer 3 on the back surface of the N-drift region 4.
After respectively annealing the front metal on the upper surface of the N + emitter region 6 and the front metal on the upper surface of the outer side of the P-type base region 5 by sequentially adopting a photoetching process, an etching process and an annealing process to form a first emitter 71 and a second emitter 72, the method further comprises the following steps:
forming a P + collector region 2 on the back of the N-type field stop layer 3 by sequentially adopting an ion implantation process and an annealing process;
and forming a collector electrode 1 on the back of the P + collector region 2 by sequentially adopting a deposition process and an annealing process.
The specific process of the preparation method of the insulated gate bipolar transistor provided by the embodiment 2 of the invention is as follows:
1. forming an N-type field stop layer 3 on the back surface of the N-drift region 4 by sequentially adopting an ion implantation process and an annealing process;
2. sequentially adopting an etching process and an epitaxial process to form a super-junction P column 12 at the inner edge position of the N-drift region 4 below the P-type base region 5, and simultaneously sequentially adopting the etching process and the epitaxial process to form a super-junction N column 13 between the super-junction P columns 12;
3. forming P-type base regions 5 on two sides of the upper surface of the N-drift region 4 by sequentially adopting a thermal oxidation process, a gluing process, a photoetching process, an ion injection process and an annealing process;
4. forming a P-type buried layer 11 inside the P-type base region 5 by sequentially adopting a photoetching process and an ion implantation process;
5. forming an N + emitter region 6 on the upper surface of the P-type base region 5 and above the P-type buried layer 11, specifically: forming a groove on the upper surface of the P-type base region 5 which is above the P-type buried layer 11 and has a set distance from the outer side of the P-type base region 5 by sequentially adopting a gluing process, a photoetching process and an etching process; filling N-type wide bandgap semiconductor material in the groove by adopting a filling process; forming an N + emission region 6 at the position filled with the N-type wide bandgap semiconductor material by adopting an ion implantation process;
6. forming a gate dielectric layer 9 on the upper surface of the N-drift region 4 by adopting a thermal oxidation process;
7. forming a grid 8 on the upper surface of the grid dielectric layer 9 by adopting a deposition process;
8. adopting a metal material to deposit front metal on the upper surface of the N + emitter region 6 and the upper surface of the outer side of the P-type base region 5; then respectively annealing the front metal on the upper surface of the N + emitter region 6 and the front metal on the upper surface of the outer side of the P-type base region 5 by sequentially adopting a photoetching process, an etching process and an annealing process to form a first emitter 71 and a second emitter 72;
9. forming a P + collector region 2 on the back of the N-type field stop layer 3 by sequentially adopting an ion implantation process and an annealing process;
10. and forming a collector electrode 1 on the back of the P + collector region 2 by sequentially adopting a deposition process and an annealing process.
For convenience of description, each part of the above apparatus is separately described as being functionally divided into various modules or units. Of course, the functionality of the various modules or units may be implemented in the same one or more pieces of software or hardware when implementing the present application.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Finally, it should be noted that: the above embodiments are only intended to illustrate the technical solution of the present invention and not to limit the same, and a person of ordinary skill in the art can make modifications or equivalent substitutions to the specific embodiments of the present invention with reference to the above embodiments, and any modifications or equivalent substitutions which do not depart from the spirit and scope of the present invention are within the protection scope of the present invention as claimed in the appended claims.
Claims (18)
1. An insulated gate bipolar transistor is characterized by comprising an N-drift region (4), a P-type base region (5), a P-type buried layer (11) and an N + emitter region (6);
the P-type base region (5) is positioned on two sides of the upper surface of the N-drift region (4), the N + emitter region (6) is positioned on the upper surface of the P-type base region (5), and a set distance is reserved between the N + emitter region and the outer side of the P-type base region (5);
the P-type buried layer (11) is positioned in the P-type base region (5) below the N + emitter region (6).
2. The insulated gate bipolar transistor according to claim 1, characterized in that the upper surface of the N + emitter region (6) and the upper surface outside the P-type base region (5) are further provided with an emitter (7).
3. The insulated gate bipolar transistor according to claim 2, wherein the emitter (7) comprises a first emitter (71) and a second emitter (72) connected to each other;
the first emitter (71) is positioned on the upper surface of the outer side of the P-type base region (5) and forms Schottky contact with the P-type base region (5);
the second emitter (72) is positioned on the upper surface of the N + emission region (6) and is in contact connection with a part of the N + emission region (6) to form ohmic contact.
4. The insulated gate bipolar transistor according to claim 1, characterized in that a super junction P column (12) is further arranged at the inner edge position of the N-drift region (4) below the P-type base region (5);
and a super-junction N column (13) is also arranged between the super-junction P columns (12).
5. The insulated gate bipolar transistor according to claim 1, wherein the upper surface of the N-drift region (4) in a middle position further comprises: a grid electrode (8) and a grid dielectric layer (9) which are arranged up and down.
6. The insulated gate bipolar transistor according to claim 1, characterized in that the doping concentration of the P-type buried layer (11) is greater than the doping concentration of the P-type base region (5).
7. The insulated gate bipolar transistor according to claim 1, wherein the N + emitter region (6) is formed using an N-type wide bandgap semiconductor material;
the N-type wide bandgap semiconductor material is SiC, GaAs or GaN.
8. The insulated gate bipolar transistor according to claim 1, wherein a junction depth of the super junction P column (12) is equal to or less than a junction depth of a super junction N column (13);
the doping concentration of the super junction P column (12) is 1 x 1015cm-3～1×1016cm-3；
The doping concentration of the super junction N column (13) is 5 multiplied by 1012cm-3～2×1016cm-3。
9. The insulated gate bipolar transistor according to claim 3, wherein the first emitter (71) and the second emitter (72) are made of the same metal or different metals.
10. A method for manufacturing an insulated gate bipolar transistor, comprising:
forming P-type base regions (5) on two sides of the upper surface of the N-drift region (4);
forming a P-type buried layer (11) in the P-type base region (5);
and an N + emitter region (6) is formed on the upper surface of the P-type base region (5) above the P-type buried layer (11) and at a set distance from the outer side of the P-type base region (5).
11. The method for manufacturing the insulated gate bipolar transistor according to claim 10, wherein the forming of the P-type base regions (5) on two sides of the upper surface of the N-drift region (4) comprises:
and forming P-type base regions (5) on two sides of the upper surface of the N-drift region (4) by sequentially adopting a thermal oxidation process, a gluing process, a photoetching process, an ion injection process and an annealing process.
12. The method for manufacturing an insulated gate bipolar transistor according to claim 10, wherein the forming of the P-type buried layer (11) inside the P-type base region (5) comprises:
and forming a P-type buried layer (11) in the P-type base region (5) by sequentially adopting a photoetching process and an ion implantation process.
13. The method for manufacturing an insulated gate bipolar transistor according to claim 10, wherein the forming an N + emitter region (6) on the upper surface of the P-type base region (5) above the P-type buried layer (11) and having a set distance from the outside of the P-type base region (5) comprises:
forming a groove on the upper surface of the P-type base region (5) which is above the P-type buried layer (11) and has a set distance from the outer side of the P-type base region (5) by sequentially adopting a gluing process, a photoetching process and an etching process;
filling N-type wide bandgap semiconductor material in the groove by adopting a filling process;
and forming an N + emission region (6) at the position filled with the N-type wide bandgap semiconductor material by adopting an ion implantation process.
14. The method of manufacturing an insulated gate bipolar transistor according to claim 13, wherein the filling process employs a deposition process or a combined ion implantation and annealing process.
15. The method of manufacturing an insulated gate bipolar transistor according to claim 13, wherein the N-type wide bandgap semiconductor material is SiC, GaAs, or GaN.
16. The method for manufacturing an insulated gate bipolar transistor according to claim 10, wherein after forming the N + emitter region (6) on the upper surface of the P-type base region (5) above the P-type buried layer (11) and having a set distance from the outside of the P-type base region (5), the method further comprises:
forming a gate dielectric layer (9) on the upper surface of the N-drift region (4) by adopting a thermal oxidation process;
and forming a grid electrode (8) on the upper surface of the grid dielectric layer (9) by adopting a deposition process.
17. The method for manufacturing an insulated gate bipolar transistor according to claim 16, wherein after the forming the gate electrode (8) on the upper surface of the gate dielectric layer (9) by using the deposition process, the method further comprises:
depositing front metal on the upper surface of the N + emitter region (6) and the upper surface of the outer side of the P-type base region (5) by adopting a metal material;
and respectively annealing the front metal on the upper surface of the N + emitter region (6) and the front metal on the upper surface of the outer side of the P-type base region (5) by sequentially adopting a photoetching process, an etching process and an annealing process to form a first emitter (71) and a second emitter (72).
18. The method for manufacturing the insulated gate bipolar transistor according to claim 10, wherein before forming the P-type base regions (5) on both sides of the upper surface of the N-drift region (4), the method further comprises:
and a super-junction P column (12) is formed at the inner edge position of the N-drift region (4) below the P-type base region (5) by sequentially adopting an etching process and an epitaxial process, and a super-junction N column (13) is formed between the super-junction P columns (12) by sequentially adopting the etching process and the epitaxial process.
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