CN105161420A - Method of manufacturing transverse MOSFET device - Google Patents

Method of manufacturing transverse MOSFET device Download PDF

Info

Publication number
CN105161420A
CN105161420A CN201510410002.2A CN201510410002A CN105161420A CN 105161420 A CN105161420 A CN 105161420A CN 201510410002 A CN201510410002 A CN 201510410002A CN 105161420 A CN105161420 A CN 105161420A
Authority
CN
China
Prior art keywords
conductive type
type semiconductor
layer
dielectric
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201510410002.2A
Other languages
Chinese (zh)
Other versions
CN105161420B (en
Inventor
罗小蓉
刘建平
张彦辉
谭桥
尹超
周坤
魏杰
阮新亮
李鹏程
张波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Electronic Science and Technology of China
Original Assignee
University of Electronic Science and Technology of China
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Electronic Science and Technology of China filed Critical University of Electronic Science and Technology of China
Priority to CN201510410002.2A priority Critical patent/CN105161420B/en
Publication of CN105161420A publication Critical patent/CN105161420A/en
Application granted granted Critical
Publication of CN105161420B publication Critical patent/CN105161420B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66704—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

The invention belongs to the semiconductor technical field and specifically relates to a groove type transverse MOSFET device manufacturing method. The method mainly comprises the following steps of making injected ions and silicon react to form a U type dielectric layer through technical steps of deep groove etching, inclined ion injection, high-temperature annealing, epitaxy, etc.; making a monocrystalline silicon layer reserved on the surface of the dielectric layer; acquiring a monocrystalline silicon semiconductor layer for device manufacturing on the surface of the monocrystalline silicon layer through epitaxial technologies; providing a monocrystalline silicon layer of a device active region and achieving technical manufacturing of the groove type transverse semiconductor device. The method has the following advantages that a monocrystalline silicon material can be acquired on the dielectric layer film; and defects caused by the polysilicon serving as the active region and characterized by large leakage current, low breakdown voltage and bad technical repeatability, etc. can be prevented.

Description

A kind of manufacture method of lateral MOSFET device
Technical field
The invention belongs to semiconductor technology, relate to MOSFET (MetalOxideSemiconductorfieldeffecttransistor specifically, metal-oxide semiconductor fieldeffect transistor) device, the particularly manufacture method of LDMOS (LateralDouble-diffusionMetalOxideSemiconductorfieldeffec ttransistor, lateral double diffused metal-Oxide-Semiconductor Field effect transistor) device.
Background technology
Two key parameters of power MOSFET are withstand voltage (BV) and conduction resistance (R on.sp).Can improve withstand voltage by increasing drift region length and reducing drift doping concentration, but these two methods all can the conduction resistance of increased device.In traditional power MOSFET, conduction resistance R on, spaccording to the relational expression R with withstand voltage BV on, sp∝ BV 2.5sharply increase, this contradictory relation seriously constrains the development of power device.
In order to alleviate the contradictory relation between withstand voltage and conduction resistance, trench structure is introduced in power device.Compared to conventional MOS FET, slot type power MOS FET can improve withstand voltage effectively, reduces conduction resistance; Meanwhile, after introducing trench structure, lateral device dimensions reduces, and conduction resistance reduces further, and chip integration improves greatly.In view of these advantages, it is popular that slot type power device becomes research.
The technique such as etching, extension, deposit, ion implantation is all the general procedure in semiconductor technology.Compared to single crystal silicon device, it is little to there is forward current in polycrystalline silicon device, the shortcoming that reverse leakage current is large, and therefore, polycrystalline silicon device is seldom applied.But what obtain at silica surface deposit silicon material is all polysilicon.SIMOX technique is a kind of technology preparing SOI material, by injecting oxonium ion at semiconductor surface, after high annealing, the pasc reaction of oxonium ion and surrounding forms silicon dioxide, surface still remains with one deck monocrystalline silicon on silica, and this layer of monocrystalline silicon quality very well (as shown in Figure 1).At present, silicon-on-insulator can be prepared by technology such as bonding, the isolation of note oxygen, smart peelings, but these technology are all for material preparatory phase, are difficult to obtain monocrystalline silicon at silica surface in subsequent technique.
Summary of the invention
To be solved by this invention, be exactly for the problems referred to above, propose a kind of manufacture method of grooved lateral MOSFET device.
For achieving the above object, the present invention adopts following technical scheme:
A manufacture method for lateral MOSFET device, is characterized in that, comprises the following steps:
The first step: preparation SOI material base; Described SOI material base comprises substrate 1, be positioned at the dielectric buried layer 2 of substrate 1 upper surface and be positioned at the first conductive type semiconductor active layer 3 of dielectric buried layer 2 upper surface;
Second step: adopt etching technics, etch the first groove in the first conductive type semiconductor active layer 3;
3rd step: adopt ion implantation technology, injects ion in the first conductive type semiconductor active layer 3 of the first trenched side-wall and bottom, after annealing, form gate dielectric layer 6; Between described gate dielectric layer 6 and the first groove, there is U-shaped monocrystalline silicon active layer 31;
4th step: adopt epitaxial growth technology, U-shaped monocrystalline silicon active layer 31 grows the first conduction type single-crystal semiconductor layer 7, and described first conduction type single-crystal semiconductor layer 7 fills up the first groove;
5th step: adopt etching technics, etch the second groove in the first conduction type single-crystal semiconductor layer 7;
6th step: fill dielectric and form dielectric groove 8 in the second groove;
7th step: adopt ion implantation technology, inject the second conductive type semiconductor impurity in the first conduction type single-crystal semiconductor layer 7 between gate dielectric layer 6 and dielectric groove 8 side sidewall and form the second conductive type semiconductor tagma 9;
8th step: adopt etching technics, etching gate dielectric layer 6, away from the first conductive type semiconductor active layer 3 of the second side, side, conductive type semiconductor tagma 9, forms the 3rd groove;
9th step: adopt ion implantation technology, inject the first conductive type semiconductor impurity in the second conductive type semiconductor tagma 9 near gate dielectric layer 6 side and form the first conductive type semiconductor heavy doping source region 101; The first conduction type single-crystal semiconductor layer 7 upper strata between gate dielectric layer 6 and dielectric groove 8 opposite side sidewall is injected the first conductive type semiconductor impurity and is formed the first conductive type semiconductor heavy doping drain region 102; In the first conductive type semiconductor active layer 3 of the 3rd beneath trenches, inject the first conductive type semiconductor impurity form the first cut-off region, conductive type semiconductor field 11;
Tenth step: adopt epitaxy technique, fill the second conductive type semiconductor contact zone 12 in the 3rd groove;
11 step: adopt ion implantation technology, the second upper strata, conductive type semiconductor tagma 9 between the first conductive type semiconductor heavy doping source region 101 and dielectric groove 8 is injected the second conductive type semiconductor impurity and is formed the second conductive type semiconductor heavy doping body contact zone 132, injects the second conductive type semiconductor impurity form the second conductive type semiconductor heavy doping grid end ohmic contact regions 131 on the first conductive type semiconductor active layer 3 upper strata near the first conductive type semiconductor heavy doping source region 101;
12 step: make source metal in the first conductive type semiconductor heavy doping source region 101 and the second conductive type semiconductor heavy doping body contact zone 132 upper surface, make drain metal in the first conductive type semiconductor heavy doping drain region 102 and the second conductive type semiconductor contact zone 12 upper surface, make gate metal at the second conductive type semiconductor heavy doping grid end ohmic contact regions 131 upper surface.
Further, in above-mentioned steps, the first conduction type doping and the second conduction type adulterate is two kinds of contrary doping.When the first conduction type is doped to N-type doping, then the second conduction type is doped to the doping of P type; Accordingly, when the first conduction type is doped to the doping of P type, then the second conduction type is doped to N-type doping.
Further, described in 3rd step, ion implantation technology is angled ion implantation process, and refer to that there is angle in the direction of ion implantation and active layer 3 surface normal direction, concrete angle depends on the depth-to-width ratio of the first groove, first groove depth-to-width ratio is larger, and angle-tilt ion implant angle is less; For ensureing that oxonium ion is all injected in the first trenched side-wall and bottom, need in injection process to rotate silicon chip.
Further, the ion injected in the 3rd step is oxonium ion, Nitrogen ion or oxygen nitrogen hybrid ionic.
Further, when filling dielectric 8 in the 6th step in the first groove, the mode of heat growth or deposit is adopted to carry out; The medium that the mode of deposit grows is fine and close not as good as the medium of heat growth, can select high temperature density, dielectric is thicker in the second groove, adopt the mode of repeatedly deposit to fill.
Further, the dielectric 8 of filling in the 6th step can for silicon dioxide or dielectric coefficient be lower than the dielectric of silicon dioxide or two kinds and above medium increasing gradually of dielectric coefficient from top to bottom.
Adopt dielectric coefficient from top to bottom two kinds and above medium can regulate electric field better, obtain higher puncture voltage.
Beneficial effect of the present invention is, can obtain single crystal silicon material, then obtain single crystal silicon device at U-shaped dielectric layer surface, avoids that the leakage current that polysilicon brings as active area is large, breakdown potential is forced down and the deficiency such as process repeatability difference; Do not need complicated mask simultaneously.Device application prepared by this method significantly can alleviate the contradictory relation between withstand voltage and conduction resistance on MOS control device.
Accompanying drawing explanation
Fig. 1 is SIMOX technology schematic diagram;
Wherein, Fig. 1 (a) is by injecting oxonium ion schematic diagram at semiconductor surface; Fig. 1 (b) forms silicon dioxide for the pasc reaction of oxonium ion and surrounding, and surface still remains with the structural representation of one deck monocrystalline silicon on silica;
Fig. 2 is the generalized section of the SOI material adopted in manufacturing process flow of the present invention;
Fig. 3 is the generalized section etching formation first groove in manufacturing process flow of the present invention;
Fig. 4 is the generalized section that oxonium ion is injected in manufacturing process flow medium dip of the present invention;
Fig. 5 is the generalized section forming oxide layer in manufacturing process flow of the present invention after high annealing;
Fig. 6 is the generalized section of the monocrystalline silicon layer of epitaxial growth first conduction type in manufacturing process flow of the present invention;
Fig. 7 is that in manufacturing process flow of the present invention, semiconductor surface carries out the generalized section after planarization;
Fig. 8 is the generalized section etching formation second groove in manufacturing process flow of the present invention;
Fig. 9 is the generalized section of filling dielectric in manufacturing process flow of the present invention in the second groove;
Figure 10 carries out the generalized section after planarization to dielectric surface in manufacturing process flow of the present invention;
Figure 11 is that manufacturing process flow intermediate ion of the present invention injects the generalized section forming tagma;
Figure 12 is the generalized section etching formation the 3rd groove in manufacturing process flow of the present invention;
Figure 13 is that manufacturing process flow intermediate ion of the present invention injects the first conductive type impurity formation source, misses the generalized section of contact area and cut-off region, field;
Figure 14 is extension second conductive type semiconductor district generalized section in manufacturing process flow of the present invention;
Figure 15 is the generalized section in manufacturing process flow of the present invention after second conductive type semiconductor district planarization;
Figure 16 is the generalized section that manufacturing process flow intermediate ion of the present invention injects the second conductive type impurity organizator contact zone and grid end ohmic contact regions;
Figure 17 is each electrode preparation and surface passivation technology in manufacturing process flow of the present invention, forms the generalized section of complete device;
Figure 18 is deposit Si in manufacturing process flow of the present invention 3n 4layer also removes the 3rd flute surfaces Si 3n 4the generalized section of layer.
Figure 19 is the generalized section of the medium of the second trench fill two kinds of different dielectric coefficients in manufacturing process flow of the present invention.
Embodiment
Below in conjunction with accompanying drawing, describe technical scheme of the present invention in detail:
Embodiment 1
In this example, the manufacturing process of lateral MOS FT device is as follows:
Prepare material: SOI material (as shown in Figure 2) comprises substrate layer 1, dielectric buried layer 2 and active layer 3 from bottom to top, and wherein the conduction type of substrate layer 1 is not limit, and the conduction type of active layer 3 is the first conduction type:
Step 1: form the first groove.Adopt thermal oxidation technology in described active layer 3 superficial growth layer of oxide layer 41, at described oxide layer 41 surface deposition Si 3n 4layer 51, according to photoetching window, etches Si successively 3n 4layer 51, oxide layer 41 and active layer 3 to set depth, form the first groove (as shown in Figure 3);
Step 2: form dielectric layer in active layer inside, and leave monocrystalline silicon in the inner side of dielectric layer.Forming gate dielectric layer adopts angled ion implantation process to inject oxonium ion, by adjustment implant angle, makes the first trenched side-wall and bottom described in step 1 all inject oxonium ion (as shown in Figure 4); With after annealing, make the oxonium ion of injection and the pasc reaction of surrounding form insulating medium layer, this is the gate dielectric layer 6 of the U-shaped grid of this device, and U-shaped monocrystalline silicon active layer 31 is left in the inner side of described gate dielectric layer 6, and the damage that ion implantation causes is repaired in annealing simultaneously; Then a small amount of dielectric (as shown in Figure 5) that monocrystalline silicon active layer 31 surface stays is removed;
Step 3: epitaxial growth single-crystal semiconductor layer.At the first conduction type single-crystal semiconductor layer 7 of monocrystalline silicon active layer 31 Epitaxial growth setting concentration, until it fills up the first groove (as shown in Figure 6) described in step 1;
Step 4: planarization single-crystal semiconductor layer.With Si 3n 4layer 51 carries out planarization as the first conduction type single-crystal semiconductor layer 7 of stop layer to step 3 extension, removes Si subsequently 3n 4layer 51 and surface oxide layer 41 (as shown in Figure 7);
Step 5: form the second groove.Adopt thermal oxidation technology in the silicon face growth layer of oxide layer 42 after step 4 planarization, at described oxide layer 42 surface deposition Si 3n 4layer 52, according to photoetching window, etches Si successively 3n 4layer 52, oxide layer 42 and the first conduction type single-crystal semiconductor layer 7 to set depth, form the second groove (as shown in Figure 8);
Step 6: fill dielectric in the second groove.Fill dielectric 8, until it fills up the second groove (as shown in Figure 9) described in step 5;
Step 7: planarization insulating medium layer.With Si 3n 4layer 52 carries out planarization as stop layer to the dielectric 8 that step 6 is filled, and removes Si subsequently 3n 4layer 52 and surface oxide layer 42 (as shown in Figure 10);
Step 8: form tagma.Adopt thermal oxidation technology in silicon face growth layer of oxide layer 43, as the pre-oxygen layer of ion implantation, the side surface ion between gate dielectric layer 6 and dielectric groove 8 injects and formation second conductivity type body region 9 (as shown in figure 11) of annealing;
Step 9: form the 3rd groove.According to photoetching window, on active layer 3 surface of U-shaped grid away from side, tagma, etching oxidation layer 43, active layer 3 to set depth successively, forms the 3rd groove (as shown in figure 12);
Step 10: form source, drain region and cut-off region, field.Adopt thermal oxidation technology in silicon face growth layer of oxide layer 44, as the pre-oxygen layer of ion implantation, the surface ion in the second conductivity type body region 9 near gate medium 6 side injects formation first conduction type heavy doping source region 101; Between U-shaped gate medium 6 and media slot 8, inject formation first conduction type heavy doping drain region 102 away from semiconductor layer 7 surface ion of side, tagma 9 simultaneously; The first cut-off region, conduction type field 11 (as shown in figure 13) is formed in described 3rd flute surfaces ion implantation;
Step 11: extension second conductive type semiconductor district.According to photoetching window, the oxide layer 44 of etching the 3rd flute surfaces, the second conductive type semiconductor contact zone 12 of the concentration of extension setting subsequently, until it fills up the 3rd groove (as shown in figure 14);
Step 12: surface media is also removed by planarization second conductive type semiconductor district.(as shown in figure 15);
Step 13: organizator contact zone and grid termination contact area.Adopt thermal oxidation technology in silicon face growth layer of oxide layer 45, as the pre-oxygen layer of ion implantation, tagma 9 surface ion between the first conduction type heavy doping source region 101 and dielectric groove 8 injects formation second conduction type heavy doping body contact zone 132; Inject formation second conduction type heavy doping grid end ohmic contact regions 131 (as shown in figure 16) at active layer 3 surface ion near heavy doping source region 101 simultaneously;
Step 14: each electrode preparation and surface passivation, after device completes, the common metal exit of the first conduction type heavy doping source region 10a and the second conduction type heavy doping body contact zone 132 is as source S, the common metal exit of the first conduction type heavy doping drain region 102 and the second conductive type semiconductor contact zone 12 is as drain D, and the metal exit of the second conduction type grid end ohmic contact regions 13a is as grid G (as shown in figure 17).
Embodiment 2
The place that this example is different from embodiment 1 is, step 2 inject ion can be oxonium ion, Nitrogen ion or other can react with active layer material the ion forming insulating medium layer; The gate dielectric layer 6 of described ion and pasc reaction gained can be silicon dioxide, silicon nitride or other dielectrics.
Embodiment 3
The place that this example is different from embodiment 1 is, when step 6 fills dielectric 8 in the second groove, adopts the mode of heat growth or deposit to carry out; The medium that the mode of deposit grows is fine and close not as good as the medium of heat growth, can select high temperature density, dielectric is thicker in the first groove, adopt the mode of repeatedly deposit to fill.
Embodiment 4
The place that this example is different from embodiment 1 is, increases step 10 between step 10 and 11 ': at oxide layer 44 surface deposition Si 3n 4layer 54, and etch the Si of the 3rd flute surfaces 3n 4layer (as shown in figure 18).
Embodiment 5
The place that this example is different from embodiment 1 is, step 6 dielectric 8 of filling can for silicon dioxide or dielectric coefficient be lower than the dielectric of silicon dioxide or two kinds and above medium (as shown in figure 19) increasing gradually of K value from top to bottom.
Adopt dielectric coefficient from top to bottom two kinds and above medium can regulate electric field better, obtain higher puncture voltage.

Claims (5)

1. a manufacture method for lateral MOSFET device, is characterized in that, comprises the following steps:
The first step: preparation SOI material base; Described SOI material base comprises substrate (1), be positioned at the dielectric buried layer (2) of substrate (1) upper surface and be positioned at the first conductive type semiconductor active layer (3) of dielectric buried layer (2) upper surface;
Second step: adopt etching technics, etch the first groove in the first conductive type semiconductor active layer (3);
3rd step: adopt ion implantation technology, injects ion in the first conductive type semiconductor active layer (3) of the first trenched side-wall and bottom, after annealing, form gate dielectric layer (6); There is between described gate dielectric layer (6) and the first groove U-shaped monocrystalline silicon active layer (31);
4th step: adopt epitaxial growth technology, at upper growth first conduction type single-crystal semiconductor layer (7) of U-shaped monocrystalline silicon active layer (31), described first conduction type single-crystal semiconductor layer (7) fills up the first groove;
5th step: adopt etching technics, etch the second groove in the first conduction type single-crystal semiconductor layer (7);
6th step: fill dielectric and form dielectric groove (8) in the second groove;
7th step: adopt ion implantation technology, injects the second conductive type semiconductor impurity in the first conduction type single-crystal semiconductor layer (7) between gate dielectric layer (6) and dielectric groove (8) side sidewall and forms the second conductive type semiconductor tagma (9);
8th step: adopt etching technics, etching gate dielectric layer (6), away from the first conductive type semiconductor active layer (3) of the second conductive type semiconductor tagma (9) side, side, forms the 3rd groove;
9th step: adopt ion implantation technology, injects the first conductive type semiconductor impurity in the second conductive type semiconductor tagma (9) near gate dielectric layer (6) side and forms the first conductive type semiconductor heavy doping source region (101); The first conduction type single-crystal semiconductor layer (7) upper strata between gate dielectric layer (6) and dielectric groove (8) opposite side sidewall is injected the first conductive type semiconductor impurity and is formed the first conductive type semiconductor heavy doping drain region (102); The first cut-off region, conductive type semiconductor field (11) is formed at the first conductive type semiconductor active layer (3) surface imp lantation first conductive type semiconductor impurity of the 3rd beneath trenches;
Tenth step: adopt epitaxy technique, fill the second conductive type semiconductor contact zone (12) in the 3rd groove;
11 step: adopt ion implantation technology, the second conductive type semiconductor tagma (9) upper strata between the first conductive type semiconductor heavy doping source region (101) and dielectric groove (8) is injected the second conductive type semiconductor impurity and formed the second conductive type semiconductor heavy doping body contact zone (132); Inject the second conductive type semiconductor impurity on the first conductive type semiconductor active layer (3) upper strata near the first conductive type semiconductor heavy doping source region (101) and form the second conductive type semiconductor heavy doping grid end ohmic contact regions (131);
12 step: make source metal with the second conductive type semiconductor heavy doping body contact zone (132) upper surface in the first conductive type semiconductor heavy doping source region (101), make drain metal in the first conductive type semiconductor heavy doping drain region (102) with the second conductive type semiconductor contact zone (12) upper surface, make gate metal at the second conductive type semiconductor heavy doping grid end ohmic contact regions (131) upper surface.
2. the manufacture method of a kind of lateral MOSFET device according to claim 1, is characterized in that, the ion that the 3rd step is injected is oxonium ion or Nitrogen ion or oxygen nitrogen hybrid ionic.
3. the manufacture method of a kind of lateral MOSFET device according to claim 1, is characterized in that, the dielectric (8) that described 6th step is filled is silicon dioxide.
4. the manufacture method of a kind of lateral MOSFET device according to claim 1, is characterized in that, the dielectric (8) that described 6th step is filled is the dielectric of dielectric coefficient lower than silicon dioxide.
5. the manufacture method of a kind of lateral MOSFET device according to claim 1, is characterized in that, the dielectric (8) that described 6th step is filled is made up of the multilayer insulation medium that dielectric coefficient increases gradually from top to bottom.
CN201510410002.2A 2015-07-13 2015-07-13 A kind of manufacture method of lateral MOSFET device Expired - Fee Related CN105161420B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510410002.2A CN105161420B (en) 2015-07-13 2015-07-13 A kind of manufacture method of lateral MOSFET device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510410002.2A CN105161420B (en) 2015-07-13 2015-07-13 A kind of manufacture method of lateral MOSFET device

Publications (2)

Publication Number Publication Date
CN105161420A true CN105161420A (en) 2015-12-16
CN105161420B CN105161420B (en) 2017-10-13

Family

ID=54802239

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510410002.2A Expired - Fee Related CN105161420B (en) 2015-07-13 2015-07-13 A kind of manufacture method of lateral MOSFET device

Country Status (1)

Country Link
CN (1) CN105161420B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111162122A (en) * 2019-12-23 2020-05-15 广东美的白色家电技术创新中心有限公司 Transverse power device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012094780A1 (en) * 2011-01-10 2012-07-19 电子科技大学 Soi lateral mosfet device and integrated circuit thereof
CN102969355A (en) * 2012-11-07 2013-03-13 电子科技大学 Silicon on insulator (SOI)-based metal-oxide-semiconductor field-effect transistor (PMOSFET) power device
US20130193509A1 (en) * 2010-05-17 2013-08-01 University Of Electronic Science And Technology Of China Soi lateral mosfet devices
CN103904124A (en) * 2014-04-10 2014-07-02 电子科技大学 SOI groove type LDMOS device with U-shaped extension gate
CN104253050A (en) * 2014-04-10 2014-12-31 电子科技大学 Manufacturing method of groove type transverse MOSFET (metal oxide semiconductor field effect transistor) device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130193509A1 (en) * 2010-05-17 2013-08-01 University Of Electronic Science And Technology Of China Soi lateral mosfet devices
WO2012094780A1 (en) * 2011-01-10 2012-07-19 电子科技大学 Soi lateral mosfet device and integrated circuit thereof
CN102969355A (en) * 2012-11-07 2013-03-13 电子科技大学 Silicon on insulator (SOI)-based metal-oxide-semiconductor field-effect transistor (PMOSFET) power device
CN103904124A (en) * 2014-04-10 2014-07-02 电子科技大学 SOI groove type LDMOS device with U-shaped extension gate
CN104253050A (en) * 2014-04-10 2014-12-31 电子科技大学 Manufacturing method of groove type transverse MOSFET (metal oxide semiconductor field effect transistor) device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111162122A (en) * 2019-12-23 2020-05-15 广东美的白色家电技术创新中心有限公司 Transverse power device
CN111162122B (en) * 2019-12-23 2023-02-24 广东美的白色家电技术创新中心有限公司 Transverse power device

Also Published As

Publication number Publication date
CN105161420B (en) 2017-10-13

Similar Documents

Publication Publication Date Title
KR101632938B1 (en) Semiconductor trench structure having a sealing plug and method
CN101872724A (en) Manufacturing method of super junction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor)
CN107316899B (en) Semi-super junction device and manufacturing method thereof
CN104716177B (en) A kind of manufacture method for the radio frequency LDMOS device for improving electric leakage
CN101019235A (en) Vertical semiconductor devices and methods of manufacturing such devices
CN102044563A (en) LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method thereof
TW200941593A (en) Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands
CN105161533A (en) Silicon carbide VDMOS device and manufacturing method
US7977192B2 (en) Fabrication method of trenched metal-oxide-semiconductor device
CN104253050B (en) A kind of manufacture method of grooved lateral MOSFET device
CN102945799B (en) Method for manufacturing longitudinal power semiconductor device
CN104952929A (en) SiC VDMOS (vertical double-diffused metal oxide semiconductor) device and manufacturing method thereof
CN100414714C (en) MOS transistor with partial depletion SOI structure and producing method thereof
CN105304693A (en) LDMOS device manufacturing method
CN102054702A (en) Method for manufacturing groove power MOSFET device
CN101877314A (en) Method for manufacturing thick oxide layer at bottom of groove
CN103681859A (en) A silicon carbide semiconductor device and a manufacturing method thereof
CN104157690B (en) Strain NLDMOS device with groove structure and manufacturing method thereof
US7999311B2 (en) Semiconductor device
CN105161420A (en) Method of manufacturing transverse MOSFET device
CN103681278B (en) The forming method of a kind of PMOS source leakage
TWI460823B (en) Methods for fabricating trench metal oxide semiconductor field effect transistors
CN209374448U (en) A kind of power device chip
CN102751199B (en) Manufacturing method for groove type semiconductor power device
CN108110056A (en) Vertical bilateral diffusion field-effect tranisistor and preparation method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20171013

Termination date: 20200713

CF01 Termination of patent right due to non-payment of annual fee