CN101257047A - High pressure resistant lateral direction bilateral diffusion MOS transistor - Google Patents
High pressure resistant lateral direction bilateral diffusion MOS transistor Download PDFInfo
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- CN101257047A CN101257047A CNA200810103337XA CN200810103337A CN101257047A CN 101257047 A CN101257047 A CN 101257047A CN A200810103337X A CNA200810103337X A CN A200810103337XA CN 200810103337 A CN200810103337 A CN 200810103337A CN 101257047 A CN101257047 A CN 101257047A
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Abstract
The present invention discloses a transversal bilateral diffusion MOS transistor with high pressure resistant, which belongs to micro-electronics semi-conductor device field. The device includes a gate region, a source area, a drain region, a tagma, a gate medium and a drift region, the setting drift region is placed between the tagma and the drain region, and the doping type is opposite to the tagma, an insulating medium region and a doping region which is opposite to the doping type of the drift region are equipped in the drift region, and the doping concentration of the doping region is higher than that of the drift region, the doping region is adjacent to the tagma, however the insulating medium region is adjacent to the drain region. Because the insulating medium region and the doping region are inducted into the drift region at the same time, the effective depth of the drift region is reduced effectively to make the electric field more uniform and increase the equivalent length of the drift region, the resistant high Voltage characteristic of the transversal bilateral diffusion MOS transistor device of the present invention is good.
Description
Technical field
The invention relates to lateral direction bilateral diffusion MOS transistor in the semiconductor microelectronics devices field, be specifically related to the lateral direction bilateral diffusion MOS transistor of a kind of suitable high-tension circuit or radio-frequency (RF) power amplifier circuit.
Background technology
(lateral double-diffused MOS transistor LDMOS), is a kind of MOS device of lightly doped drain to lateral direction bilateral diffusion MOS transistor.Compare with common MOS device, LDMOS has long light doping section at drain terminal, is called the drift region, and the doping content of this part structure is 10 usually
16Cm
-3Magnitude.The LDMOS structure is born higher voltage by the drift region just and is fallen.Because the LDMOS technology has simple, reliable, ripe characteristics, and good RF performance, simultaneously because the manufacturing process of ldmos transistor can be compatible fully with existing standard CMOS process,, reduce manufacturing cost so be easy to realize integrated on a large scale with the low voltage CMOS circuit.It can be applied to various types of power circuits.
Along with the development of radio frequency integrated circuit, radio-frequency devices is at wireless telecommunications such as individual/family wireless communication apparatus, aspects such as mobile communication equipment or even military radar, and the concern that is subjected to is more and more, and demand is also increasing.In the receive-transmit system of radio circuit, power amplifier is a very important part.And power amplifier requires to handle bigger signal usually, and requires good stability, and this needs good high-voltage resistance capability and reliability with regard to the core parts that require circuit.Usually, the core devices of this part circuit need adopt special material, and complex process involves great expense, and is unfavorable for integrated with other circuit.Therefore, it is simple to press for a kind of technology, cheap and be easy to integrated radio-frequency power device and satisfy the demand in market.Horizontal dual pervasion field effect transistor, by near the drain region of metal-oxide semiconductor fieldeffect transistor (MOSFET), adding low-doped drift region, can reduce the maximum field in the device, improve the high-voltage resistance capability of device, thereby, at the wireless radiofrequency communication system, especially in the radio-frequency power amplifier, advantages such as that the LDMOS structure has is high pressure resistant, device performance stable, the linearity is good also enjoy and pay attention to and application.
Therefore, how further to optimize lateral direction bilateral diffusion MOS transistor, improve the device high voltage performance, the present just difficult point and the focus of LDMOS area research in the world.
Summary of the invention
The present invention is directed to the problems of the prior art, a kind of high voltage bearing lateral direction bilateral diffusion MOS transistor is provided.
Technical scheme of the present invention is:
A kind of high voltage bearing lateral direction bilateral diffusion MOS transistor, comprise grid region, source region, drain region, tagma, gate medium and drift region, described drift region is between tagma and drain region, doping type is opposite with the tagma, it is characterized in that, is provided with a dielectric district and a doped region opposite with the drift region doping type in described drift region, and, the doping content of described doped region is than the doping content height of drift region, and described doped region is near the tagma, and described dielectric district is near the drain region.
The upper surface flush of described doped region and described drift region, the upper surface in described dielectric district is not less than the upper surface of described drift region, and the degree of depth in described doped region and described dielectric district is no more than the degree of depth of described drift region.
The lateral length value scope of described drift region is 10nm to 50 μ m, and its vertical depth value scope is 10nm to 10 μ m, and its doping content span is 10
12To 10
19Cm
-3
Described dielectric district can adopt dielectric constant to be lower than the material of silicon, as silica, and silicon nitride etc. or form by several dielectric materials, its lateral length value scope is 10nm to 10 μ m, its vertical depth value scope is 10nm to 10 μ m.
Described doped region, its lateral length value scope is 10nm to 10 μ m, and its vertical depth value scope is 10nm to 10 μ m, and the impurity concentration scope is 10
12To 10
21Cm
-3
Compared with prior art, the invention has the beneficial effects as follows:
In the drift region, introduce the doped region B of different doping types, its purpose is, introduce vertical internal electric field, impurity in the current drift district of drift region is exhausted, make the transverse electric field of drift region even as far as possible, thereby improve transistorized puncture voltage, perhaps allow to guaranteeing under the constant situation of puncture voltage, by the doping content of increase drift region, thus the switch resistance of reduction device.The effect of introducing dielectric district A in the drift region is, by introducing different materials, electric field is suddenlyd change in the drift region, and is reduced near the electric field of PN junction of the maximum field of drift region, especially drift region and tagma formation as far as possible.By in the drift region, introducing the low dielectric district of permittivity ratio silicon materials, can make electric field strength bigger in the dielectric district, power line is more concentrated, more drain terminal electromotive force will drop to the dielectric district, thereby can reduce the electric field strength of doped region, also help improving the puncture voltage of device.Therefore, introduce dielectric district A and doped region B simultaneously in the drift region, help reducing the effective depth of drift region, make electric field more even, and increased the equivalent length of drift region, these effects all will help improving the voltage-resistent characteristic of device.
Description of drawings
Fig. 1 is the generalized section of the horizontal proliferation field effect transistor structure introduced among the present invention.Among the figure: the 1-grid region, 2-grid side wall, 3-gate medium district, the 4-source region, the 5-drain region, the drift region that 6-is low-doped, 7-tagma (or substrate zone), and 8-and the opposite doped region of 6 district's doping types, 9-insulating medium layer district, the 10-body is drawn doped region;
Fig. 2 is based on the n-type LDMOS generalized section of structure of the present invention.Among the figure: 11-draws in the grid region, and draw in 12-source region and tagma, and 13-draws in the drain region, 14-tagma, 15-substrate, 16-p type doped region, 17-dielectric area, 18-n type doped region;
Fig. 3 adopts standard technology to prepare the process schematic diagram of LDMOS.Among the figure: 20-substrate, 21-LDMOS drift region, 22-STI isolated area, 23-tagma, 24-gate dielectric layer, 25-grid region, 26-grid side wall district, 27-N
+Doping source region, 28-N
+Doped drain, 29-P
+Doped region, 30-body draw-out area.
The characteristic of whether introducing medium and doped region in Fig. 4 LDMOS structure drift region compares.Obviously, in the drift region, introduce doped region and dielectric area simultaneously, its high voltage performance can be improved significantly.
Embodiment
Below in conjunction with the drawings and specific embodiments the present invention is described in further detail:
Provided the core of field effect transistor of the present invention in Fig. 1 structure.The most of LDMOS structure with routine of its structure is identical, and its main special feature is, has introduced different doped region 8 and the dielectric districts 9 of doping type in low-doped drift region 6.Usually, the doping content in the doped region 8 is than high in the drift region 6.Dielectric district 9 optimizes the low insulating material of permittivity ratio silicon materials that adopts, such as silica, silicon nitride etc.Because the electric current of device need flow through in drift region 6, so the degree of depth in doped region 8 and dielectric district 9 does not all surpass drift region 6.The upper surface flush of doped region 8 and drift region 6, the upper surface in dielectric district 9 is not less than the upper surface of described drift region, and in addition, it is more low-doped that employing is optimized in drift region 6, to improve the high-voltage resistance capability of device.Drift region 6 both can be even doping, also can optimize and adopt doping content 5 gradual doping that progressively descend to tagma 7 from the drain region.In addition, body is drawn doped region 10 and is optimized the higher concentration of employing, the body potential when working to reduce volume resistance and stabilizing device.
Based on structure of the present invention, can realize n-type LDMOS and p-type LDMOS device.Shown in Fig. 2 based on n-type LDMOS device of the present invention.Wherein in tagma 14, body draw-out area 12 and doped region 16, all adopt p-type conductive type impurity to mix, and the doping impurity of n-type conduction type is all adopted in source region, drain region and tagma.Accordingly, for the p device, the dopant type in each district is opposite with n-type LDMOS.
This n-type LDMOS device can utilize standard CMOS process to realize, relevant preparation process as shown in Figure 3.
During the preparation beginning, adopt the backing material identical with conventional MOS;
At first, when adopting the trap injection technology of standard technology flow process, carry out low-doped, the drift region of the LDMOS device of formation;
Next, utilize in the STI isolation technology in the standard technology,, introduce the STI dielectric area, obtain structure shown in Fig. 3 (a) in the drift region of the LDMOS device that will form by the domain of active area;
Next carry out channel region injection and grid region and form technology, LDMOS structure and conventional MOS structure are identical, haply, be followed successively by raceway groove injection and threshold value adjustment and inject, form gate dielectric layer, deposit and etching grid material, form grid, low-doped formation LDD district, and LDMOS only carries out LDD doping injection at the source end, form side wall, obtain the structure shown in Fig. 3 (b);
Next, LDMOS is carried out the source leak injection, form the structure shown in Fig. 3 (c);
Then, in standard technology, the source-drain area of PMOS is mixed when injecting, form the body draw-out area of N type LDMOS and the high-doped zone in the drift region respectively; Form the structure shown in Fig. 3 (d);
In the technological process of back, the MOS structure of LDMOS structure and routine is just the same.Successively carry out: silication is leaked wherein in the source, the not silication of drift region of LDMOS, deposit separator, lithography fair lead; Depositing metal, the photoetching lead-in wire; Passivation, or the like.
Fig. 4 has compared undoped region and dielectric area in the drift region, has only introduced dielectric area and introduce dielectric area simultaneously and the device property of three kinds of LDMOS structures of doped region.The drain terminal electric current means that along with gate voltage is smooth more device can be operated in the inclined to one side value of high more voltage down among the figure.As can be seen, in the drift region of LDMOS, introduce dielectric area and doped region simultaneously, the puncture voltage of device is significantly improved.
LDMOS concrete structure of the present invention is provided among the embodiment, and wherein the design parameter of dielectric district in drift region and the drift region and doped region can specifically adopt:
The lateral length value scope of drift region is 10nm to 50 μ m, and its vertical depth value scope is 10nm to 10 μ m, and its doping content span is 10
12To 10
19Cm
-3
In addition, the dielectric district can adopt dielectric constant to be lower than the material of silicon, as silica, and silicon nitride etc. or form by several dielectric materials, its lateral length value scope is 10nm to 10 μ m, its vertical depth value scope is 10nm to 10 μ m.
In addition, doped region, its lateral length value scope is 10nm to 10 μ m, and its vertical depth value scope is 10nm to 10 μ m, and the impurity concentration scope is 10
12To 10
21Cm
-3
More than by specific embodiment LDMOS provided by the present invention has been described, it will be understood by those of skill in the art that in the scope that does not break away from essence of the present invention, can make certain deformation or modification to the present invention.
Claims (9)
1, a kind of high voltage bearing lateral direction bilateral diffusion MOS transistor, comprise grid region, source region, drain region, tagma, gate medium and drift region, described drift region is between tagma and drain region, doping type is opposite with the tagma, it is characterized in that, is provided with a dielectric district and a doped region opposite with the drift region doping type in described drift region, and, the doping content of described doped region is than the doping content height of drift region, and described doped region is near the tagma, and described dielectric district is near the drain region.
2, high voltage bearing lateral direction bilateral diffusion MOS transistor as claimed in claim 1 is characterized in that, the upper surface flush of described doped region and described drift region.
3, high voltage bearing lateral direction bilateral diffusion MOS transistor as claimed in claim 1 or 2 is characterized in that, the upper surface in described dielectric district is not less than the upper surface of described drift region.
4, high voltage bearing lateral direction bilateral diffusion MOS transistor as claimed in claim 1 is characterized in that, the lateral length value scope of described drift region is 10nm to 50 μ m.
As claim 1 or 4 described high voltage bearing lateral direction bilateral diffusion MOS transistors, it is characterized in that 5, vertical depth value scope of described drift region is 10nm to 10 μ m, its doping content span is 10
12To 10
19Cm
-3
6, high voltage bearing lateral direction bilateral diffusion MOS transistor as claimed in claim 1 is characterized in that, described dielectric district adopts dielectric constant to be lower than the material of silicon or is made of the combination of materials that two or more dielectric constant is lower than silicon.
As claim 1 or 6 described high voltage bearing lateral direction bilateral diffusion MOS transistors, it is characterized in that 7, the lateral length value scope in described dielectric district is 10nm to 10 μ m, its vertical depth value scope is 10nm to 10 μ m.
8, high voltage bearing lateral direction bilateral diffusion MOS transistor as claimed in claim 1 is characterized in that, the impurity concentration scope of described doped region is 10
12To 10
21Cm
-3
As claim 1 or 8 described high voltage bearing lateral direction bilateral diffusion MOS transistors, it is characterized in that 9, the lateral length value scope of described doped region is 10nm to 10 μ m, its vertical depth value scope is 10nm to 10 μ m.
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| CNA200810103337XA CN101257047A (en) | 2008-04-03 | 2008-04-03 | High pressure resistant lateral direction bilateral diffusion MOS transistor |
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| CN102097482A (en) * | 2010-12-31 | 2011-06-15 | 杭州电子科技大学 | Integrated double longitudinal channel SOI LDMOS (silicon on insulator laterally double diffusion metal oxide semiconductor) device unit |
| CN102214695A (en) * | 2011-05-27 | 2011-10-12 | 上海宏力半导体制造有限公司 | Power MOS (metal oxide semiconductor) device and manufacturing method thereof |
| CN102386131A (en) * | 2010-09-01 | 2012-03-21 | 上海宏力半导体制造有限公司 | Technology for simultaneously realizing drift drain metal oxide semiconductor (DDMOS) drift region and lateral diffused metal oxide semiconductor (LDMOS) drift region |
| CN102420142A (en) * | 2011-06-07 | 2012-04-18 | 上海华力微电子有限公司 | Method for optimizing source leak punchthrough performance of high-pressure LDMOS (lateral double-diffused metal Oxide semiconductor transistor) device |
| CN101958346B (en) * | 2009-07-16 | 2012-07-11 | 中芯国际集成电路制造(上海)有限公司 | Lateral double-diffused metal-oxide semiconductor field effect transistor and manufacturing method thereof |
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| CN102610649A (en) * | 2012-04-10 | 2012-07-25 | 中国科学院微电子研究所 | High-reliability LDMOS power device |
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| WO2012100458A1 (en) * | 2011-01-27 | 2012-08-02 | 北京大学 | High-voltage resistant lateral double-diffused transistor based on nanowire device |
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| CN112825327A (en) * | 2019-11-21 | 2021-05-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN115528117A (en) * | 2022-11-16 | 2022-12-27 | 北京智芯微电子科技有限公司 | Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit |
| CN117317024A (en) * | 2023-11-27 | 2023-12-29 | 北京智芯微电子科技有限公司 | High-switching-characteristic semiconductor device, process, chip and electronic equipment |
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