CN102760771B - For the novel grid structure of RF-LDMOS device - Google Patents
For the novel grid structure of RF-LDMOS device Download PDFInfo
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- CN102760771B CN102760771B CN201210266787.7A CN201210266787A CN102760771B CN 102760771 B CN102760771 B CN 102760771B CN 201210266787 A CN201210266787 A CN 201210266787A CN 102760771 B CN102760771 B CN 102760771B
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Abstract
The invention discloses a kind of novel grid structure for RF-LDMOS device, the present invention covers one deck grid extension layer in traditional grid structure, and (its material can be heavily doped semiconductor, such as polysilicon, or metal silicide or or even metal), the width of grid depends on that the minimum gate of LDMOS is long, this length is ever-reduced along with the reduction of technology characteristics yardstick, but in identical grid width situation, the gate resistance of LDMOS will constantly increase.The present invention adds one deck grid extension layer on grid, and its width can be wider, and it can reduce the gate resistance in identical grid width situation, thus improves power gain.
Description
Technical field
The present invention relates to a kind of technical field of semiconductors, be specifically related to a kind of novel grid structure for RF-LDMOS device.
Background technology
The RF-LDMOS of Si base compares with traditional cmos, and have one section of drift region, this drift region improves the puncture voltage of device.High puncture voltage can improve power output and power density.Current RF-LDMOS is mainly used in S-band, and operating frequency is less than 4GHz.LDMOS has low-down cost, and the excellent linearity.Current people more and more wish the operating frequency range that can improve RF-LDMOS, can be operated in C-band or even K-band.The operating frequency improving RF-LDMOS namely improves Ft and Fmax, mainly contains the method for following two aspects: 1. the resistance reducing drift region, can realize the distribution that a. regulates drift doping concentration here by following two aspects.B. be the length reducing LDMOS drift region.2. reduce grid long.Mainly adopt second method at present.But current grid main material is polysilicon, in order to reduce gate resistance, the method usually adopted is that layer of metal silicide is done in face more on the polysilicon.Along with the continuous reduction that grid are long, grid width is substantially constant, and in order to ensure identical power output, corresponding gate resistance is continuous increase.The increase of gate resistance has had a strong impact on Fmax, reduces power gain.
Summary of the invention
The object of the invention is for the deficiency existing for prior art, provides a kind of novel grid structure for RF-LDMOS device, and it can reduce the gate resistance in identical grid width situation, thus improves power gain.
In order to solve these problems of the prior art, technical scheme provided by the invention is:
A kind of novel grid structure for RF-LDMOS device, comprise RF-LDMOS basic structure, RF-LDMOS basic structure comprises undermost heavy doping substrate zone, the grid be located at the epitaxial loayer on heavy doping substrate zone and be located at above epitaxial loayer, heavy doping source region is provided with in described epitaxial loayer, heavy doping drain region, described heavy doping source region, heavy doping drain region lays respectively at the not homonymy of grid, described heavy doping source region is positioned in described epitaxial loayer, be provided with channel region between heavy doping drain region successively and leak drift region, described channel region and heavy doping source region and leak drift region and contact, the groove that heavy doping connects or fills by conducting objects is provided with between described heavy doping source region and heavy doping substrate, heavy doping in groove or conducting objects contact with heavy doping substrate and heavy doping source region, described leakage drift region contacts with heavy doping drain region, described novel grid structure is positioned at above channel region, described grid are coated with one deck grid extension layer, described grid extension layer contacts with grid.
For technique scheme, inventor also has further Optimized Measures.
As optimization, the described complete covering gate of grid extension layer covered on grid, and extend identical distance to heavy doping source region and heavy doping drain region.
As optimization, the described complete covering gate of grid extension layer covered on grid, and to heavy doping source region extend distance shorter be even zero, to heavy doping drain region extend distance longer.
Further, described grid extension layer is polysilicon or metal silicide or metal.
As optimization, source metal lead wire and drain terminal metal lead wire totally two metal lead wires are provided with above described epitaxial loayer, described source metal lead wire contacts with heavy doping source region and source to be drawn, and described drain terminal metal lead wire contacts with heavy doping drain region and to be drawn by drain terminal.
As optimization, source metal lead wire and drain terminal metal lead wire totally two metal lead wires are provided with above described epitaxial loayer, described source metal lead wire is connected by heavy doping or to contact with heavy doping substrate zone with the groove that conducting objects is filled draws source from the back side, and described drain terminal metal lead wire contacts with heavy doping drain region and to be drawn by drain terminal.
As optimization, between described grid and epitaxial loayer, be provided with the oxide layer for insulating.
As optimization, below described channel region, be provided with heavily doped region, for providing a fixing current potential for channel region.
As optimization, be provided with one deck field plate from grid towards the horizontal direction of leaking drift region, the one end of the field plate that described entirety is stepped covers the top of grid extension layer, and the other end of described field plate has horizontal-extending on leakage drift region.
Relative to scheme of the prior art, advantage of the present invention is:
The present invention covers one deck grid extension layer in traditional grid structure, and (its material can be heavily doped semiconductor, such as polysilicon, or metal silicide or or even metal, the width of grid depends on that the minimum gate of LDMOS is long, this length is ever-reduced along with the reduction of technology characteristics yardstick, but in identical grid width situation, the gate resistance of LDMOS will constantly increase.The present invention adds last layer grid extension layer on grid, and the width of grid extension layer can be wider, can reduce gate resistance like this, effectively improve power gain.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the invention will be further described:
Fig. 1 is the cross-sectional view of traditional LDMOS device;
Fig. 2 is the structural representation of the LDMOS device of the embodiment of the present invention 1;
Fig. 3 is the structural representation of the LDMOS device of the embodiment of the present invention 2;
Fig. 4 is the structural representation of the LDMOS device of the embodiment of the present invention 3;
Fig. 5 is the structural representation of the LDMOS device of the embodiment of the present invention 4;
Fig. 6 is the structural representation of the LDMOS device of the embodiment of the present invention 5
Wherein: 1, RF-LDMOS basic structure; 2, heavy doping substrate; 3, epitaxial loayer; 4, the groove of heavy doping or conducting objects is filled with; 5, drift region is leaked; 6, heavy doping drain region; 7, heavily doped region; 8, heavy doping source region; 9, channel region; 10, oxide layer; 11, drain terminal metal lead wire; 12, source metal lead wire; 13, grid; 14, grid extension layer; 15, field plate; 16, conductive trench; 17, HR-Si substrate.
Embodiment
Below in conjunction with specific embodiment, such scheme is described further.Should be understood that these embodiments are not limited to for illustration of the present invention limit the scope of the invention.The implementation condition adopted in embodiment can do further adjustment according to the condition of concrete producer, and not marked implementation condition is generally the condition in normal experiment.
embodiment 1:
A kind of N-type LDMOS for RF-LDMOS device described by the present embodiment, its structure as shown in Figure 2, it comprises RF-LDMOS basic structure 1, RF-LDMOS basic structure 1 comprises undermost heavy doping substrate 2 district, the grid 13 be located at the epitaxial loayer 3 in heavy doping substrate 2 district and be located at above epitaxial loayer 3, heavy doping source region 8 is provided with in described epitaxial loayer 3, heavy doping drain region 6, described heavy doping source region 8, heavy doping drain region 6 lays respectively at the not homonymy of grid 13, described heavy doping source region 8 is positioned in described epitaxial loayer 3, be provided with channel region 9 between heavy doping drain region 6 successively and leak drift region 5, described channel region 9 and heavy doping source region 8 and leak drift region 5 and contact, the groove 4 that heavy doping connects or fills by conducting objects is provided with between described heavy doping source region 8 and heavy doping substrate 2, heavy doping in groove 4 or conducting objects contact with heavy doping substrate 2 and heavy doping source region 8, described leakage drift region 5 contacts with heavy doping drain region 6.Compared with the traditional LDMOS device structure shown in Fig. 1, distinguishing characteristics of the present invention is that described grid 13 are positioned at above channel region 9, described grid 13 is coated with one deck grid extension layer 14, and described grid extension layer 14 contacts with grid 13.In addition, described grid extension layer 14 covering gate 13 completely covered on grid 13, and extend identical distance to heavy doping source region 8 and heavy doping drain region 6, be provided with the oxide layer 10 for insulating between described grid 13 and epitaxial loayer 3.Described grid extension layer 14 is polysilicon or metal silicide or metal
Source metal lead wire 12 and drain terminal metal lead wire 11 totally two metal lead wires are provided with above described epitaxial loayer 3, described source metal lead wire 12 contacts with heavy doping source region 8 and source to be drawn, source metal lead wire 12 is connected with the groove 4 being filled with heavy doping or conducting objects more simultaneously, source is drawn from heavy doping substrate 2 district, and described drain terminal metal lead wire 11 contacts with heavy doping drain region 6 and to be drawn by drain terminal.
Be provided with heavily doped region 7 below described channel region 9, for providing a fixing current potential for channel region 9, prevent parasitic Bipolar conducting.
embodiment 2:
The basic structure of the present embodiment is identical with embodiment 1, and difference is grid extension layer 14 covering gate 13 completely covered on grid 13, and the distance extended to heavy doping source region 8 is shorter, and the distance extended to heavy doping drain region 6 is longer.It is smaller that the width in such heavy doping source region 8 just can do, and can lower the series resistance of this section of heavy doping source region 8.
embodiment 3:
The basic structure of the present embodiment is identical with embodiment 1, and difference is: cover grid extension layer 14 covering gate 13 completely on grid 13, and the distance extended to heavy doping source region 8 is zero, the distance extended to heavy doping drain region 6 is longer.
To drain terminal extend many, grid extension layer 14 can have the overlapping region of a section very long with leakage drift region 5 below, this overlapping region is equivalent to a field plate.When the Amplitude Ratio of input signal is higher time, grid extension layer 14 has higher forward voltage, and the electronics of a part can be attracted this time to enter Lou drift region 5, and this can reduce the resistance leaking drift region 5, reduces conducting resistance, thus raises the efficiency.And when the Amplitude Ratio of input signal is lower time, grid extension layer 14 has lower forward voltage, or even negative voltage, the first half branch that this time leaks drift region 5 is subject to exhausting of grid extension layer 14.Drift region is subject to exhausting of both direction, and one is from P-Epi, and another one is from grid extension layer 14, can improve puncture voltage like this.
embodiment 4:
The basic structure of the present embodiment is identical with embodiment 1, difference is: be provided with one deck field plate 15 from grid towards the horizontal direction of leaking drift region, the one end of the field plate 15 that described entirety is stepped covers the top of grid extension layer, and the other end of described field plate 15 has horizontal-extending on leakage drift region.
At covering one deck grid extension layer on grid, although can reduce gate resistance like this, improve Fmax, can bring the increase of Cgd like this, high Cgd can affect the power gain of ldmos transistor.Increase one deck field plate 15 in the structure that the present invention is corresponding after, can reduce Cgd, field plate 15 is normally connected with source, can reduce the electric capacity of Cgd like this, thus improves power gain.
embodiment 5:
The basic structure of the present embodiment is identical with embodiment 4, and difference is: substrate adopt be the silicon substrate 17 of high resistant and without epitaxial loayer, the former structure being located at epitaxial loayer is all located in silicon substrate.Utilize HR-Si substrate, source can be drawn by source metal lead wire 12, also can pass through conductive trench 16, get through whole silicon substrate 17, source be drawn from silicon substrate 17 back side.
Above-mentioned example, only for technical conceive of the present invention and feature are described, its object is to person skilled in the art can be understood content of the present invention and implement according to this, can not limit the scope of the invention with this.All equivalent transformations of doing according to Spirit Essence of the present invention or modification, all should be encompassed within protection scope of the present invention.
Claims (4)
1. the novel grid structure for RF-LDMOS device, comprise RF-LDMOS basic structure (1), RF-LDMOS basic structure (1) comprises undermost heavy doping substrate (2) district, be located at the epitaxial loayer (3) in heavy doping substrate (2) district and be located at the grid (13) of epitaxial loayer (3) top, heavy doping source region (8) is provided with in described epitaxial loayer (3), heavy doping drain region (6), described heavy doping source region (8), heavy doping drain region (6) lays respectively at the not homonymy of grid (13), described heavy doping source region (8) is positioned in described epitaxial loayer (3), be provided with channel region (9) between heavy doping drain region (6) successively and leak drift region (5), described channel region (9) and heavy doping source region (8) and leak drift region (5) and contact, it is characterized in that, the groove (4) that heavy doping connects or fills by conducting objects is provided with between described heavy doping source region (8) and heavy doping substrate (2), heavy doping in groove or conducting objects contact with heavy doping substrate (2) and heavy doping source region (8), described leakage drift region (5) contacts with heavy doping drain region (6), described grid (13) are positioned at top, channel region (9), described grid (13) are coated with one deck grid extension layer (14), described grid extension layer (14) contacts with grid (13), described grid extension layer (14) covering gate (13) completely covered on grid (13), and the distance extended to heavy doping source region (8) shorter be even zero, the distance extended to heavy doping drain region (6) is longer, one deck field plate (15) is being provided with towards the horizontal direction of leaking drift region (5) from grid (13), the one end of the field plate (15) that described entirety is stepped covers the top of grid extension layer (14), and the other end of described field plate (15) has horizontal-extending in leakage drift region (5),
The material of described grid extension layer (14) can be heavily doped semiconductor or metal silicide or metal.
2. the novel grid structure for RF-LDMOS device according to claim 1, it is characterized in that, described epitaxial loayer (3) top is provided with source metal lead wire (12) and drain terminal metal lead wire (11) totally two metal lead wires, described source metal lead wire (12) contacts with heavy doping source region (8) and source to be drawn, also can be connected by heavy doping or be connected to heavy doping substrate (2) directly draw with the groove (4) that conducting objects is filled, described drain terminal metal lead wire (11) contacts with heavy doping drain region (6) and to be drawn by drain terminal.
3. the novel grid structure for RF-LDMOS device according to claim 1, is characterized in that, is provided with the oxide layer (10) for insulating between described grid (13) and epitaxial loayer (3).
4. the novel grid structure for RF-LDMOS device according to claim 1, is characterized in that, below, described channel region (9) is provided with heavily doped region (7), for providing a fixing current potential for channel region (9).
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| CN104183632B (en) * | 2014-08-13 | 2017-08-29 | 昆山华太电子技术有限公司 | The self aligned drain terminal field plate structures of RF LDMOS and preparation method |
| CN105448996A (en) * | 2016-01-07 | 2016-03-30 | 昆山华太电子技术有限公司 | RF-LDMOS device structure with improved robustness |
| CN112825332B (en) * | 2019-11-21 | 2024-04-12 | 南通尚阳通集成电路有限公司 | LDMOS device and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000036594A (en) * | 1998-07-17 | 2000-02-02 | Texas Instr Japan Ltd | Semiconductor device and manufacture thereof |
| CN101699630A (en) * | 2009-11-19 | 2010-04-28 | 苏州远创达科技有限公司 | Ldmos power device |
| CN102082174A (en) * | 2009-10-02 | 2011-06-01 | 台湾积体电路制造股份有限公司 | High voltage devices and methods for forming the high voltage devices |
| CN102403208A (en) * | 2010-09-07 | 2012-04-04 | 上海华虹Nec电子有限公司 | Preparation method for grid of RFLDMOS (radio frequency laterally diffused metal oxide semiconductor) device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008210994A (en) * | 2007-02-27 | 2008-09-11 | Nec Electronics Corp | Lateral mosfet and manufacturing method thereof |
| CN101807597B (en) * | 2010-04-02 | 2012-12-05 | 中国电子科技集团公司第五十五研究所 | Autoregistration submicron gate structure and manufacturing method thereof |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000036594A (en) * | 1998-07-17 | 2000-02-02 | Texas Instr Japan Ltd | Semiconductor device and manufacture thereof |
| CN102082174A (en) * | 2009-10-02 | 2011-06-01 | 台湾积体电路制造股份有限公司 | High voltage devices and methods for forming the high voltage devices |
| CN101699630A (en) * | 2009-11-19 | 2010-04-28 | 苏州远创达科技有限公司 | Ldmos power device |
| CN102403208A (en) * | 2010-09-07 | 2012-04-04 | 上海华虹Nec电子有限公司 | Preparation method for grid of RFLDMOS (radio frequency laterally diffused metal oxide semiconductor) device |
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