CN102420142A - Method for optimizing source leak punchthrough performance of high-pressure LDMOS (lateral double-diffused metal Oxide semiconductor transistor) device - Google Patents
Method for optimizing source leak punchthrough performance of high-pressure LDMOS (lateral double-diffused metal Oxide semiconductor transistor) device Download PDFInfo
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Abstract
The invention provides a method used for optimizing the source leak punchthrough performance of a high-pressure LDMOS (lateral double-diffused metal Oxide semiconductor transistor) device. The method comprises the following steps: covering a photoresist layer on a baseplate, forming an opening on the photoresist layer, revealing the baseplate in the opening, and injecting oxygen ions through the opening; removing the photoresist layer covered on the baseplate, carrying out high temperature annealing treatment on the baseplate, and forming a silicon oxide isolated area on the ion injection region, blow the opening, of the baseplate; and injecting ions into the baseplate, forming a P trap and an N-drift region which is near and contacted with the P trap, wherein the silicon oxide isolated area is positioned in the P trap region. In the invention, oxygen ions of a certain concentration are injected through injecting ions into easy punchthrough place between source leaks of the LDMOS device so as to form the silicon oxide isolated area through the high temperature annealing treatment after injection, and the characteristic of silicon oxide is utilized to improve the source leaks punchthrough voltage of the LDMOS device.
Description
Technical field
The present invention relates to the high-voltage LDMOS device in a kind of field of semiconductor manufacture, relate in particular to a kind of method that the break-through performance is leaked in the high-voltage LDMOS device source of optimizing.
Background technology
High-voltage LDMOS (Lateral Double-Diffused MOS Transistors, lateral double-diffused metal-oxide-semiconductor transistor) device is widely used in various chips.The LDMOS device has the high and technology characteristic of simple of operating voltage, and its technology is easy to the CMOS process compatible.
A kind of high-voltage LDMOS device and manufacturing approach thereof in Chinese patent CN101783295A, have been disclosed; Its manufacturing comprises: in P type lining is low, carry out trap and inject to form N trap and P trap; In the P trap, be deposited with the source region separator, and the said P trap of etching is to be formed with the source region groove at active area.Remove the active area isolation layer, in the active area groove, insert insulant.With first dopant dose and first implant energy active area is carried out N type foreign ion and inject, with second dopant dose and second implant energy active area is carried out N type foreign ion and inject to form the drift region.Deposit and etching high pressure gate spacer are to form the high pressure grid region.The growth high voltage grid oxidation layer in the high pressure grid region is removed the high pressure barrier and is left, and deposit and etch polysilicon are to form grid above high voltage grid oxidation layer.
In Chinese patent CN101969074A, disclose a kind of high-voltage LDMOS device, this LDMOS device comprises substrate, is positioned at the epitaxial loayer on the substrate, is positioned at the drift region on the epitaxial loayer, is positioned at the drain region and the source region at LDMOS device two ends.The lower surface of wherein on the interface of substrate and epitaxial loayer, being close to the drift region has at least one pair of the n type semiconductor region and the p type semiconductor region of alternately arranging; N type semiconductor region and p type semiconductor region are close to arrangement and are formed horizontal PN junction each other, and p type semiconductor region and drift region form PN junction longitudinally simultaneously.
In the LDMOS structure; Because the junction depth of N drift region is very dark, cause by drain electrode very serious induced barrier reduce effect (Drain induction barrier lower, DIBL); The source leakage break-through that this just is very easy to cause device makes device be not easy control.Improve the grid length of the punch through voltage increase commonly used device between the device source leakage and improve P trap doping content.But improving LDMOS source leakage punch through voltage simultaneously, also can produce bad influence, as increasing the problem of area of chip, influence economize on electricity appearance and joint leakage current and so on.Along with development of semiconductor,, then will accelerate the application and the development of LDMOS device if can solve the problem of punch through voltage between the leakage of raising source.
Summary of the invention
The object of the invention is to provide a kind of method that the break-through performance is leaked in the high-voltage LDMOS device source of optimizing, and punch through voltage between effectively leak in the raising source has also been avoided the influence that increases area of chip and economize on electricity is held.
In order to realize that above-mentioned purpose provides a kind of high-voltage LDMOS device optimization source to leak the method for break-through performance; It is characterized in that: on substrate, cover a photoresist layer; On photoresist layer, open an opening; In opening, expose substrate, inject ion from opening part and form the not ion implanted region territory on contact substrate surface; Remove the photoresist layer that covers on the substrate, substrate is carried out The high temperature anneal, the ion implanted region territory in the substrate under the opening forms the silicon dioxide isolated area; In substrate, inject the ion of P type and N type respectively, form P trap and vicinity respectively and contact the N-drift region of P trap, the silicon dioxide isolated area is positioned at the P well area; In P trap and N-drift region, carry out N type ion respectively and inject to form N type heavily doped region, N type heavily doped region that is provided with in the N-drift region and N-drift region constitute the drain region of LDMOS device, and the N type heavily doped region that forms in the P trap constitutes the source area of LDMOS device; The position at silicon dioxide isolated area place is in the P trap between the N type heavily doped region and N-drift region; Generate gate oxide and polysilicon gate above the P well area in the P trap between N type heavily doped region and the N-drift region.
The present invention provides in the method for a kind of high-voltage LDMOS device optimization source leakage break-through performance, and silicon dioxide is introduced in the place of break-through easily between leak in the source, thereby improves the punch through voltage between the device source leakage.Inject oxonium ion in the pairs of openings, the silicon in the substrate is partly changed into silicon dioxide.The oxygen ion concentration that injects is preferably 1 * 10
18~ 3 * 10
18/ cm
2
The The high temperature anneal process of mentioning in the above comprises following: earlier substrate is warming up to 900 ~ 1100 ℃, and kept this temperature 0.5 ~ 2 hour, continue to be warming up to 1200 ~ 1300 ℃ afterwards, be cooled to room temperature after the silicon dioxide isolated area to be formed.Through high annealing, repair the damage that causes owing to the substrate of oxonium ion injection before, and the silicon dioxide that forms before making changes into the silicon dioxide isolated area.Preferably, in high-temperature annealing process, earlier the substrate annealing temperature is increased to 1000 ℃, and kept this temperature 1 hour, after the substrate annealing temperature is heightened to 1200 ℃, kept this temperature 3 hours.
Another object of the present invention is to provide a kind of LDMOS device of being made by said method; This device comprises: in P type substrate, the N-drift region is set; On limit, N-drift region, the P trap is set; In the P trap near the N-drift region, the silicon dioxide isolated area is set, N type heavily doped region that is provided with in the said N-drift region and N-drift region constitute the drain region, in the P trap, are formed with the source area of N type heavily doped region; And be provided with gate oxide and polysilicon gate above N type heavily doped region that in the P trap, is provided with and the P well area between the N-drift region, be used to improve the punch through voltage between the device source leakage in the silicon dioxide isolated area between source area and the N drift region.
The method of high-voltage LDMOS device optimization provided by the invention source leakage break-through performance is punch through voltage between the leakage of raising source effectively, reduces drain-induced barrier reduction effect to occur, makes device be controlled easily.
Description of drawings
Fig. 1 carries out oxonium ion to substrate in the optimization of the present invention source leakage break-through performance methodology to inject sketch map.
Fig. 2 forms silicon dioxide isolated area sketch map in the substrate in the optimization of the present invention source leakage break-through performance methodology.
Fig. 3 is that the sketch map that forms P trap and N-drift region in the break-through performance methodology is leaked in optimization of the present invention source.
Fig. 4 is the high-voltage LDMOS device of break-through performance methodology manufacturing is leaked in the present invention through the optimization source a structural representation.
Embodiment
The present invention provides a kind of method that the break-through performance is leaked in the high-voltage LDMOS device source of optimizing.
On substrate, cover a photoresist layer, on photoresist layer, open an opening, in opening, expose substrate, inject ion from opening part and form the not ion implanted region territory on contact substrate surface; Remove the photoresist layer that covers on the substrate, substrate is carried out The high temperature anneal, the ion implanted region territory in the substrate under the opening forms the silicon dioxide isolated area; Substrate is injected ion, form P trap and vicinity and contact the N-drift region of P trap, the silicon dioxide isolated area is arranged in P well area (the silicon dioxide isolated area has the surface that a degree of depth does not promptly contact the P trap yet at the P trap at this moment).In P trap and N-drift region, carry out ion afterwards respectively and inject formation N type heavily doped region, N type heavily doped region that is provided with in the N-drift region and N-drift region constitute the drain region of LDMOS device, the N type heavily doped region formation source area that forms in the P trap; Make the position at silicon dioxide isolated area place be in the P trap between the N type heavily doped region and N-drift region (but not contacting P trap, N-drift region) when wherein, implanting N type heavily doped region in the P trap; Generate gate oxide and polysilicon gate above the P well area in the P trap between N type heavily doped region and the N-drift region.
Carry out follow-up preparation technology to accomplish the LDMOS preparation of devices, owing to this follow-up preparation flow is known by those skilled in the art, so repeat no more according to the common preparation flow of LDMOS device afterwards.
Usually can adopt the grid that increase device doping content mode long and raising P trap to improve the LDMOS source and leak punch through voltage, but this will certainly bring bad influence, increases chip area, influence economize on electricity appearance and joint leakage current like needs.Of the present inventionly focus in the channel region of LDMOS device forming a silicon dioxide isolated area, this silicon dioxide isolated area is being used to improve the punch through voltage of device source between leaking between source area and the drain region.In common LDMOS device architecture; Because the junction depth of N drift region is very dark, it is very serious that drain-induced barrier reduces effect, is very easy to cause the source leakage break-through of device; Make device be not easy control, silicon dioxide isolated area provided by the present invention has then well overcome the problems referred to above.
For improving LDMOS device withstand voltage performance, to being provided with a resistive formation between the drain region, be called drift region (drift claims lightly doped drain again) at active area.Introduce silicon dioxide wherein through the ion injection mode drift region of break-through easily between device source is leaked, and the silicon dioxide isolated area of formation can be born high voltage.
In the face of the method for the break-through performance is leaked in high-voltage LDMOS device optimization of the present invention source through concrete embodiment explains further details, so that better understand the present invention, but following embodiment does not limit the scope of the invention down.
In one embodiment:
As shown in Figure 1, on substrate 1, cover a photoresist layer 3 earlier, on photoresist layer 3, carry out photoetching process and form an opening, expose substrate 1 in the bottom of opening.From the opening part implantation concentration that exposes substrate is 1 * 10
18/ cm
2Oxonium ion, oxonium ion changes into silicon dioxide 2 with opening lower substrate intermediate ion injection zone after getting into substrate after follow-up The high temperature anneal, wherein the ion implanted region territory has certain degree of depth in P type substrate.As shown in Figure 2, remove the photoresist layer 3 that covers on the substrate after, substrate 1 is carried out The high temperature anneal, repair since before inject oxonium ion and substrate caused damage.Substrate is warming up to 1000 ℃ earlier, and kept this temperature 1 hour; Continue afterwards to be warming up to 1200 ℃, kept this temperature 3 hours, be cooled to room temperature after the formation silicon dioxide isolated area.Ion implanted region territory in substrate forms the silicon dioxide isolated area.As shown in Figure 3; Substrate is re-injected ion; Thereby form P trap and N-drift region, the silicon dioxide isolated area that before forms is positioned at the P well area, and the silicon dioxide isolated area has certain distance from the surface of P trap; Also be the surface that the silicon dioxide isolated area does not contact the P trap, to form current channel below the grid in the P trap.
Known processing procedure according to the LDMOS device is processed into required high-voltage LDMOS device with substrate afterwards, and device architecture is as shown in Figure 4.
The structure of high-voltage LDMOS device comprises: in P type substrate, N-drift region 5 is set, the P well region 4 of contact N-drift region 5 is set on 5 limits, N-drift region, in the P well region 4 near N-drift region 5, silicon dioxide isolated area 2 is set.The N+ doping source region contact source metal aluminium that is provided with in the P well region 4.Grid oxic horizon is formed on N+ doping source region that is provided with in the P well region 4 and the end face that drains the P well region 4 between the drift region 5.Therefore, the passage that forms in the body through grid 7 and grid oxic horizon below, the electric current between grid 7 Controlling Source polar regions and the drain electrode drift region plays a lateral MOS device.Drain-drift region 5 is created on field oxide 6 belows, is covered by bpsg layer, also can select for use passivation layer to cover.Pass passivation layer and bpsg layer, etching drain electrode joint opening makes the top-side drain metallic aluminium through the contact of the N+ doped region in the joint N-drift region 5 drain electrode N-drift region 5, reduces contact resistance.As shown in Figure 4, gate oxide below the grid 7 of step shape and field oxide 6 can form through diverse ways.These methods comprise growth or deposition oxide, from channel region or utilize the LOCOS type etching of oxidate technology.The grid 7 of step shape has long grid length, and the grid 7 of step shape is electric current flowing between the drain electrode below passage and gate oxide and the field oxide 6, and necessary connection is provided, and reduces gate leakage capacitance.
In another embodiment:
As shown in Figure 1, on substrate 1, cover a photoresist layer 3 earlier, on photoresist layer 3, carry out photoetching process and form an opening, expose substrate 1 in the bottom of opening.From the opening part implantation concentration that exposes substrate is 3 * 10
18/ cm
2Oxonium ion, oxonium ion changes into silicon dioxide 2 with opening lower substrate intermediate ion injection zone after getting into substrate after follow-up The high temperature anneal, wherein the ion implanted region territory has certain degree of depth in P type substrate.As shown in Figure 2, remove the photoresist layer 3 that covers on the substrate after, substrate 1 is carried out The high temperature anneal, repair since before inject oxonium ion and substrate caused damage.Substrate is warming up to 900 ℃ earlier, and kept this temperature 1.5 hours; Continue afterwards to be warming up to 1300 ℃, kept this temperature 2.5 hours, be cooled to room temperature after the formation silicon dioxide isolated area.Ion implanted region territory in substrate forms the silicon dioxide isolated area.As shown in Figure 3; Substrate is re-injected ion; Thereby form P trap and N-drift region, the silicon dioxide isolated area that before forms is positioned at the P well area, and the silicon dioxide isolated area has certain distance from the surface of P trap; Also be the surface that the silicon dioxide isolated area does not contact the P trap, to form current channel below the grid in the P trap.。
Known processing procedure according to the LDMOS device is processed into required high-voltage LDMOS device with substrate afterwards, and device architecture is as shown in Figure 4.
The structure of high-voltage LDMOS device comprises: in P type substrate, N-drift region 5 is set, the P well region 4 of contact N-drift region 5 is set on 5 limits, N-drift region, in the P well region 4 near N-drift region 5, silicon dioxide isolated area 2 is set.The N+ doping source region contact source metal aluminium that is provided with in the P well region 4.Grid oxic horizon is formed on N+ doping source region that is provided with in the P well region 4 and the end face that drains the P well region 4 between the drift region 5.Therefore, the passage that forms in the body through grid 7 and grid oxic horizon below, the electric current between grid 7 Controlling Source polar regions and the drain electrode drift region plays a lateral MOS device.Drain-drift region 5 is created on field oxide 6 belows, is covered by bpsg layer, also can select for use passivation layer to cover.Pass passivation layer and bpsg layer, etching drain electrode joint opening makes the top-side drain metallic aluminium through the contact of the N+ doped region in the joint N-drift region 5 drain electrode N-drift region 5, reduces contact resistance.As shown in Figure 4, gate oxide below the grid 7 of step shape and field oxide 6 can form through diverse ways.These methods comprise growth or deposition oxide, from channel region or utilize the LOCOS type etching of oxidate technology.The grid 7 of step shape has long grid length, and the grid 7 of step shape is electric current flowing between the drain electrode below passage and gate oxide and the field oxide 6, and necessary connection is provided, and reduces gate leakage capacitance.Top-side drain metallic aluminium or drain electrode interconnection line can electrically contact the N-drift region preferably through the joint N+ doped region in the N-drift region, reduce contact resistance.
The high-voltage LDMOS device that the foregoing description makes is done corresponding test, compare with the LDMOS device of routine and have high punch through voltage.
The present invention is through the local mode of injecting ion of easy break-through between leaking in the LDMOS device source; Inject certain density oxonium ion; Form the silicon dioxide isolated area through The high temperature anneal again after the injection, punch through voltage is leaked in the source that utilizes the characteristics of silicon dioxide to improve the LDMOS device.
More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (8)
1. optimize the method that the break-through performance is leaked in the high-voltage LDMOS device source for one kind, it is characterized in that:
On substrate, cover a photoresist layer, on photoresist layer, open an opening, in opening, expose substrate, inject oxonium ion from opening part;
Remove the photoresist layer that covers on the substrate, substrate is carried out The high temperature anneal, the ion implanted region territory in the substrate under the opening forms the silicon dioxide isolated area;
In substrate, inject the ion of P type and N type respectively, form P trap and vicinity respectively and contact the N-drift region of P trap, the silicon dioxide isolated area is positioned at the P well area;
In P trap and N-drift region, carry out N type ion respectively and inject to form N type heavily doped region, N type heavily doped region that is provided with in the N-drift region and N-drift region constitute the drain region of LDMOS device, and the N type heavily doped region that forms in the P trap constitutes the source area of LDMOS device; The position at silicon dioxide isolated area place is in the P trap between the N type heavily doped region and N-drift region;
Generate gate oxide and polysilicon gate above the P well area in the P trap between N type heavily doped region and the N-drift region.
2. method according to claim 1 is characterized in that: the oxygen ion concentration of said injection is 1 * 10
18/ cm
2~ 3 * 10
18/ cm
2
3. method according to claim 1 is characterized in that: said The high temperature anneal is earlier substrate to be warming up to 900 ~ 1000 ℃, and keeps this temperature; Continue to be warming up to 1200 ~ 1300 ℃ afterwards, be cooled to room temperature after the silicon dioxide isolated area to be formed.
4. method according to claim 3 is characterized in that: after annealing temperature rises to 900-1000 ℃ in the said The high temperature anneal, kept this temperature 0.5 ~ 2 hour.
5. method according to claim 3 is characterized in that: after annealing temperature rises to 1200-1300 ℃ in the said The high temperature anneal, kept this temperature 0.5 ~ 4 hour.
6. method according to claim 3 is characterized in that: after annealing temperature rises to 1000 ℃ in the said The high temperature anneal, kept this temperature 1 hour.
7. method according to claim 3 is characterized in that: after annealing temperature rises to 1200 ℃ in the said The high temperature anneal, kept this temperature 3 hours.
8. a high-voltage LDMOS device is characterized in that, comprising:
In P type substrate, the N-drift region is set; On limit, N-drift region, the P trap is set; In the P trap near the N-drift region, the silicon dioxide isolated area is set, N type heavily doped region that is provided with in the said N-drift region and N-drift region constitute the drain region, in the P trap, are formed with the source area of N type heavily doped region; And be provided with gate oxide and polysilicon gate above N type heavily doped region that in the P trap, is provided with and the P well area between the N-drift region, be used to improve the punch through voltage between the device source leakage in the silicon dioxide isolated area between source area and the N drift region.
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Application publication date: 20120418 |