CN101719515B - LDMOS device with transverse diffusing buried layer below grid - Google Patents
LDMOS device with transverse diffusing buried layer below grid Download PDFInfo
- Publication number
- CN101719515B CN101719515B CN2009102117555A CN200910211755A CN101719515B CN 101719515 B CN101719515 B CN 101719515B CN 2009102117555 A CN2009102117555 A CN 2009102117555A CN 200910211755 A CN200910211755 A CN 200910211755A CN 101719515 B CN101719515 B CN 101719515B
- Authority
- CN
- China
- Prior art keywords
- conductivity type
- regions
- ldmos device
- grid
- buried regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 230000035755 proliferation Effects 0.000 claims description 32
- 239000002019 doping agent Substances 0.000 claims description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 11
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000003672 processing method Methods 0.000 claims description 3
- 238000009826 distribution Methods 0.000 claims description 2
- 238000002955 isolation Methods 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 abstract description 45
- 230000000694 effects Effects 0.000 abstract description 10
- 239000003990 capacitor Substances 0.000 abstract description 3
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- 239000000203 mixture Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 230000001629 suppression Effects 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses an LDMOS device with a transverse diffusing buried layer below a grid, comprising a semiconductor body and the grid positioned on the semiconductor body. A first conduction type doping channel region is arranged on the semiconductor body and below the grid; and a first conduction type transverse diffusing buried layer is arranged below the first conduction type doping channel region. The invention can properly reduce the use level of doping ions injected to the first conduction type doping channel region under the precondition of effectively inhibiting the short channel effect of the LDMOS device, thereby reducing the nonlinear capacitors of the LDMOS device so that the radio frequency power and the performance of the LDMOS device are further improved.
Description
Technical field
The present invention relates to have under a kind of grid the LDMOS device of horizontal proliferation buried regions
Background technology
In radio-frequency power LDMOS device, for power output, power gain and the linearity that improves device, requirement is under the requirement of satisfying leakage-source puncture voltage BVdss, suppress device threshold voltage Vth that the short-channel effect by device causes and leakage-source output current Ids drift as much as possible, reduce each nonlinear capacitance such as grid-source capacitor C gs, the grid-drain capacitance Cgd and the leakage-source capacitor C ds of device simultaneously as far as possible with drain source voltage Vds.Usually inject the dosage of dopant ion by increasing LDMOS device grid lower channel district, and the horizontal proliferation condition of regulating this ion implanted layer is come the short-channel effect of suppression device.But the channel region that has improved injects the increase that dopant ion dosage often causes each nonlinear capacitance of device.Therefore the means of the short-channel effect of suppression device commonly used are afoul with the requirement of the nonlinear capacitance that reduces device.
Summary of the invention
The object of the invention provides the LDMOS device that has the horizontal proliferation buried regions under a kind of grid, under the prerequisite that effectively suppresses short-channel effect, can suitably reduce the dosage that channel region injects dopant ion, thereby reduced each nonlinear capacitance of device, made the performance of radio-frequency power LDMOS device obtain further improvement.
Technical scheme of the present invention is: the LDMOS device that has the horizontal proliferation buried regions under a kind of grid, comprise the grid on semiconductor body and the semiconductor body, described semiconductor body is provided with the first conductivity type doped channel regions in the below of grid, the below of the described first conductivity type doped channel regions is provided with the first conductivity type horizontal proliferation buried regions.Wherein first conductivity type is P type or N type.
Further, described semiconductor body also comprises the first conductivity type heavy doping substrate, the first conductivity type epitaxial loayer on the first conductivity type heavy doping substrate, the described first conductivity type doped channel regions is positioned on the first conductivity type epitaxial loayer, one side of the described first conductivity type doped channel regions is in abutting connection with the first conductivity type heavy doping source region is arranged, be formed with the second conductivity type heavy doping source region opposite on the described first conductivity type doped channel regions and the first conductivity type heavy doping source region with first conductivity type, the opposite side of the described first conductivity type doped channel regions is provided with the second conductivity type heavy doping drain region by the second conductivity type separated drift regions, and source region and surface, drain region are respectively equipped with source region ohmic contact regions and drain region ohmic contact regions.As can be seen, when first conductivity type was the P type, second conductivity type was the N type; Otherwise when first conductivity type was the N type, second conductivity type was the P type.
Further, the described first conductivity type heavy doping source region is connected with first conductivity type heavy doping substrate conduction.This conduction connects and can be 1) through hole of being filled by metal or conducting objects connects 2) by the groove that metal or conducting objects are filled, perhaps be 3) this source region of connection that forms on the first conductivity type epitaxial loayer and first conductivity type of substrate mix and be connected.Wherein first conductivity type mix to connect and one of to be connected with preceding two and can to exist simultaneously, and electric conductivity is better.
The processing method of horizontal proliferation buried regions of the present invention is: in existing LDMOS device manufacturing process flow process, in form the channel ion injecting mask and carry out the first conductive type of channel dopant ion inject this processing step before or after, increased formation buried regions ion injecting mask, and carry out ion and inject the processing step that forms first conduction type ion injection buried regions, through the first conductive type of channel horizontal proliferation Technology for Heating Processing step, form the first conductivity type doped channel regions and the first conductivity type horizontal proliferation buried regions simultaneously then.
In a lateral direction, can inject the buried regions ion injecting mask edge of buried regions and the relative position relation at grid edge by changing first conduction type ion, regulate the relative position that first conduction type ion injects the buried regions and the first conductive type of channel dopant ion implanted layer.And then can regulate the relative position that channel region mixes and the horizontal proliferation buried regions mixes, so that optimize the performance of LDMOS device according to different needs.
Further, described buried regions ion injecting mask is photoresist or silicon nitride dielectric layer.
Advantage of the present invention is:
1, the present invention under grid the first conductivity type doped channel regions below the first conductivity type horizontal proliferation buried regions is set, the further short-channel effect of suppression device, make and under the prerequisite that short-channel effect is effectively suppressed, can suitably reduce the dosage that dopant ion is injected in the first conductive type of channel district, thereby reduced each nonlinear capacitance of device, made the performance of radio-frequency power LDMOS device obtain further improvement.
Device simulation calculates and shows, under the condition that other device architecture parameter is identical with technological process at all, optimized design with the LDMOS device of the first conductivity type horizontal proliferation buried regions and the conventional LDMOS device (as shown in Figure 1) of optimized design, has identical conducting resistance, under identical leakage-source puncture voltage BVdss and the identical situation of threshold voltage vt h with the drift of drain source voltage Vds, the dosage that dopant ion is injected in the former the first conductive type of channel district only be the latter's about 60%, and this has caused under typical device operating state the former each nonlinear capacitance lower by about 10% than the latter.This shows that the first conductivity type horizontal proliferation buried regions really can improve the performance of radio-frequency power LDMOS device.
2, the present invention's first conductivity type horizontal proliferation buried regions also can suppress the parasitical bipolar transistor effect in the LDMOS device, has further improved the anti-surge ability of device.
Description of drawings
Fig. 1 is the structural representation of prior art LDMOS device;
Fig. 2 is the structural representation of LDMOS device specific embodiment of the present invention;
Fig. 3 is the structural representation of the another specific embodiment of LDMOS device of the present invention;
Fig. 4 is the formation schematic diagram of horizontal proliferation buried regions of the present invention;
Fig. 5 forms schematic diagram for second of horizontal proliferation buried regions of the present invention;
Fig. 6 forms schematic diagram for the 3rd of horizontal proliferation buried regions of the present invention;
Fig. 7 forms schematic diagram for the 4th of horizontal proliferation buried regions of the present invention.
Wherein: 1 semiconductor body; 2 grid; 3 first conductivity type doped channel regions; 4 first conductivity type horizontal proliferation buried regions; 5 first conductivity type heavy doping substrates; 6 first conductivity type epitaxial loayers; 7 first conductivity type heavy doping source regions; 8 second conductivity type heavy doping source regions; 9 second conductivity type drift regions; 10 second conductivity type heavy doping drain regions; 11 buried regions ion injecting masks; 12 first conduction type ions inject buried regions; 13 photoresists; The nitride dielectric layer of 14 silicon; 15 source region ohmic contact regions; 16 drain region ohmic contact regions; 17 through holes; 18 grooves; 19 first conductivity types mix and connect; 20 field plates; 21 first conductive type of channel dopant ion implanted layers.
Embodiment
Below in conjunction with drawings and Examples the present invention is further described:
Embodiment: as shown in Figures 2 and 3, one provenance drain breakdown voltage between the 60V-120V, have the LDMOS device of horizontal proliferation buried regions under the grid, comprise the grid 2 on semiconductor body 1 and the semiconductor body 1, described semiconductor body 1 is provided with the first conductivity type doped channel regions 3 in the below of grid 2, the below of the described first conductivity type doped channel regions 3 is provided with the first conductivity type horizontal proliferation buried regions 4.Described semiconductor body 1 also comprises the first conductivity type heavy doping substrate 5, the first conductivity type epitaxial loayer 6 on the first conductivity type heavy doping substrate 5, the described first conductivity type doped channel regions 3 is positioned on the first conductivity type epitaxial loayer 6, one side of the described first conductivity type doped channel regions 3 is in abutting connection with the first conductivity type heavy doping source region 7 is arranged, be formed with the second conductivity type heavy doping source region 8 opposite with first conductivity type in the described first conductivity type doped channel regions 3 and the first conductivity type heavy doping source region 7, the opposite side of the described first conductivity type doped channel regions 3 is provided with the second conductivity type heavy doping drain region 10 by 9 isolation of the second conductivity type drift region.Source region and surface, drain region are respectively equipped with source region ohmic contact regions 15 and drain region ohmic contact regions 16.
First conductivity type is the P type in the present embodiment, and second conductivity type is the N type.Wherein, the second conductivity type drift region, 9 length are between 2 microns～6 microns, and the face doping content of the second conductivity type drift region 9 is at 1～6E12/cm
2Between; The dopant ion implantation dosage of P type doped channel regions 3 is at 3～15E13/cm
2Between; The dopant ion implantation dosage of the first conductivity type horizontal proliferation buried regions 4 is at 2～20E13/cm
2Between, dopant ion is B11+, the peak point of vertical CONCENTRATION DISTRIBUTION of the first conductivity type horizontal proliferation buried regions 4 apart from the distance on semiconductor body surface between 0.2～2.0 micron.
Semiconductor body 1 top can also be provided with field plate 20, and field plate 20 can be single, also can be multiple.
The described first conductivity type heavy doping source region 7 is connected with the first conductivity type heavy doping substrate, 5 conductions.This conduction connects and can be 1) through hole 17 of being filled by metal or conducting objects connects (as shown in Figure 3), 2) groove 18 of being filled by metal or conducting objects connects (as shown in Figure 2), perhaps is 3) this source region of connection that forms on the first conductivity type epitaxial loayer and first conductivity type of substrate mix and be connected 19 (extremely shown in Figure 7 as Fig. 4).Wherein first conductivity type mix to connect 19 and one of is connected with preceding two and can exists simultaneously, and electric conductivity is better.
Add man-hour, in LDMOS device manufacturing process flow process, in form the channel ion injecting mask and carry out the first conductive type of channel dopant ion inject this processing step before or after, increase forms buried regions ion injecting mask 11 and carries out ion and inject the processing step (extremely shown in Figure 7 as Fig. 4) that forms first conduction type ion and inject buried regions 12, through the first conductive type of channel horizontal proliferation Technology for Heating Processing, form the first conductivity type doped channel regions 3 and the first conductivity type horizontal proliferation buried regions 4 simultaneously again.
Described buried regions ion injecting mask 11 is photoresist 13 or silicon nitride dielectric layer 14.
In a lateral direction, can inject buried regions ion injecting mask 11 edges of buried regions 12 and the relative position relation at grid 2 edges by changing first conduction type ion, regulate the relative position that first conduction type ion injects the buried regions 12 and the first conductive type of channel dopant ion implanted layer 21.
As shown in Figure 4, buried regions ion injecting mask 11 is a photoresist 13, aims at grid 2 edges by top and its edge that photoetching and corrosion make photoresist 13 cover the grid and the second conductivity type drift region 9; And then carry out first conduction type ion and inject, first conduction type ion that obtains injects buried regions 12 and aligns substantially with the first conductive type of channel dopant ion implanted layer 21.
As shown in Figure 5, because it is difficult with processing to make the edge of photoresist 13 aim at the edge of grid 2 by photoetching and corrosion, so can be in processing grid 2, elder generation's grown/deposited above grid 2 materials has the nitride dielectric layer 14 of suitable thickness, carry out photoetching and etching jointly to form the grid 2 that the top has nitride dielectric layer 14 with grid 2 materials then, thereby guaranteed that grid 2 are concordant with the edge of nitride dielectric layer 14, then in the man-hour that adds of carrying out the first conductivity type horizontal proliferation buried regions 4,13 carry out mask with photoresist again, the edge of photoresist 13 is arranged on the top of nitride dielectric layer 14, at this moment, photoresist 13 and the nitride dielectric layer 14 common buried regions ion injecting masks 11 that form.
As shown in Figure 6, when first conduction type ion of needs processing inject buried regions 12 towards the second conductivity type type drift region 9 transversely be shorter than the first conductive type of channel dopant ion implanted layer 21 time, in the photoresist ion injecting mask 13 that forms by photoetching and corrosion covers grid 2 fully.
As shown in Figure 7, when first conduction type ion of needs processing inject buried regions 12 towards the second conductivity type drift region 9 transversely be longer than the first conductive type of channel dopant ion implanted layer 21 time, the part of grid 2 is exposed to outside the edge of photoresist mask 13.When carrying out the injection of buried regions ion among this embodiment, the ion of injection must have enough energy so that ion can penetrate grid.
The present invention under grid the first conductivity type doped channel regions below be provided with the first conductivity type horizontal proliferation buried regions, the further short-channel effect of suppression device, make and under the prerequisite that short-channel effect is effectively suppressed, can suitably reduce the dosage that dopant ion is injected in the first conductive type of channel district, thereby reduced each nonlinear capacitance of device, made the performance of radio-frequency power LDMOS device obtain further improvement.
Claims (3)
1. have the LDMOS device of horizontal proliferation buried regions under the grid, comprise the grid (2) on semiconductor body (1) and the semiconductor body (1), described semiconductor body (1) is provided with the first conductivity type doped channel regions (3) in the below of grid (2); Described semiconductor body (1) also comprises the first conductivity type heavy doping substrate (5), the first conductivity type epitaxial loayer (6) on the first conductivity type heavy doping substrate (5), it is characterized in that: the described first conductivity type doped channel regions (3) is positioned on the first conductivity type epitaxial loayer (6), one side of the described first conductivity type doped channel regions (3) is in abutting connection with the first conductivity type heavy doping source region (7) is arranged, be formed with the second conductivity type heavy doping source region (8) opposite with first conductivity type in the described first conductivity type doped channel regions (3) and the first conductivity type heavy doping source region (7), the opposite side of the described first conductivity type doped channel regions (3) is provided with the second conductivity type heavy doping drain region (10) by the isolation of the second conductivity type drift region (9); The below of the described first conductivity type doped channel regions (3) is provided with the first conductivity type horizontal proliferation buried regions (4), the peak point of vertical CONCENTRATION DISTRIBUTION of the described first conductivity type horizontal proliferation buried regions (4) apart from the distance on semiconductor body surface between 0.2～2.0 micron.
2. the processing method of the described LDMOS device of claim 1, it is characterized in that: in LDMOS device manufacturing process flow process, in form the channel ion injecting mask and carry out the first conductive type of channel dopant ion inject this processing step before or after, increase to form buried regions ion injecting mask (11) and carry out the ion injection and form first conduction type ion injection buried regions (12) step, through the first conductive type of channel horizontal proliferation Technology for Heating Processing step, form the first conductivity type doped channel regions (3) and the first conductivity type horizontal proliferation buried regions (4) simultaneously again.
3. the processing method of LDMOS device according to claim 2 is characterized in that: described buried regions ion injecting mask (11) is the nitride dielectric layer (14) of photoresist (13) or silicon.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009102117555A CN101719515B (en) | 2009-11-03 | 2009-11-03 | LDMOS device with transverse diffusing buried layer below grid |
| PCT/CN2010/078344 WO2011054282A1 (en) | 2009-11-03 | 2010-11-02 | Ldmos device with lateral diffusion buried layer under gate and method for fabricating the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009102117555A CN101719515B (en) | 2009-11-03 | 2009-11-03 | LDMOS device with transverse diffusing buried layer below grid |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101719515A CN101719515A (en) | 2010-06-02 |
| CN101719515B true CN101719515B (en) | 2011-11-23 |
Family
ID=42434057
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009102117555A Active CN101719515B (en) | 2009-11-03 | 2009-11-03 | LDMOS device with transverse diffusing buried layer below grid |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN101719515B (en) |
| WO (1) | WO2011054282A1 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101719515B (en) * | 2009-11-03 | 2011-11-23 | 苏州远创达科技有限公司 | LDMOS device with transverse diffusing buried layer below grid |
| CN102376762B (en) * | 2010-08-26 | 2013-09-11 | 上海华虹Nec电子有限公司 | Super junction LDMOS(Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof |
| CN101969074B (en) | 2010-10-28 | 2012-07-04 | 电子科技大学 | High voltage lateral double diffused MOSFET element |
| CN103035727B (en) * | 2012-11-09 | 2015-08-19 | 上海华虹宏力半导体制造有限公司 | RFLDMOS device and manufacture method |
| CN103855210A (en) * | 2012-12-03 | 2014-06-11 | 上海华虹宏力半导体制造有限公司 | Radio frequency transverse double-diffusion field effect transistor and manufacturing method thereof |
| CN105633146B (en) * | 2014-10-27 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | RFLDMOS device and its manufacturing method |
| CN112002759A (en) * | 2020-08-20 | 2020-11-27 | 杰华特微电子（杭州）有限公司 | Lateral diffusion transistor and manufacturing method thereof |
| CN114497173B (en) * | 2020-11-12 | 2023-10-31 | 苏州华太电子技术股份有限公司 | Double-buried-channel RFLDMOS device applied to radio frequency power amplification |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5386136A (en) * | 1991-05-06 | 1995-01-31 | Siliconix Incorporated | Lightly-doped drain MOSFET with improved breakdown characteristics |
| US6168983B1 (en) * | 1996-11-05 | 2001-01-02 | Power Integrations, Inc. | Method of making a high-voltage transistor with multiple lateral conduction layers |
| DE10311699A1 (en) * | 2003-03-17 | 2004-11-18 | Infineon Technologies Ag | Laterally-diffused metal oxide semiconductor, high frequency transistor includes pocket zone of first conductivity type, introduced into semiconductor material |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6989567B2 (en) * | 2003-10-03 | 2006-01-24 | Infineon Technologies North America Corp. | LDMOS transistor |
| KR100628250B1 (en) * | 2005-09-28 | 2006-09-27 | 동부일렉트로닉스 주식회사 | Semiconductor device for using power and method for fabricating the same |
| CN101719515B (en) * | 2009-11-03 | 2011-11-23 | 苏州远创达科技有限公司 | LDMOS device with transverse diffusing buried layer below grid |
-
2009
- 2009-11-03 CN CN2009102117555A patent/CN101719515B/en active Active
-
2010
- 2010-11-02 WO PCT/CN2010/078344 patent/WO2011054282A1/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5386136A (en) * | 1991-05-06 | 1995-01-31 | Siliconix Incorporated | Lightly-doped drain MOSFET with improved breakdown characteristics |
| US6168983B1 (en) * | 1996-11-05 | 2001-01-02 | Power Integrations, Inc. | Method of making a high-voltage transistor with multiple lateral conduction layers |
| DE10311699A1 (en) * | 2003-03-17 | 2004-11-18 | Infineon Technologies Ag | Laterally-diffused metal oxide semiconductor, high frequency transistor includes pocket zone of first conductivity type, introduced into semiconductor material |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2011054282A1 (en) | 2011-05-12 |
| CN101719515A (en) | 2010-06-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101719515B (en) | LDMOS device with transverse diffusing buried layer below grid | |
| CN100585875C (en) | Ldmos transistor | |
| CN105789311B (en) | Horizontal proliferation field effect transistor and its manufacturing method | |
| CN109461774B (en) | HEMT device containing high dielectric coefficient dielectric block | |
| CN104009076A (en) | AlGaN/GaN heterojunction field effect transistor | |
| CN104992978A (en) | Radio frequency LDMOS transistor and manufacture method thereof | |
| CN102201445A (en) | Partial silicon on insulator (PSOI) lateral super-junction power semiconductor device | |
| CN114447102A (en) | Gallium nitride heterojunction field effect transistor with compound semiconductor layer on substrate | |
| CN104659091A (en) | Ldmos device and manufacturing method thereof | |
| CN104752500B (en) | Radio frequency LDMOS device and process | |
| CN104485360A (en) | Radio frequency ldmos device and manufacturing method thereof | |
| CN102104026B (en) | Method for manufacturing power metal oxide semiconductor (MOS) transistor device integrated with Schottky diodes | |
| US10312368B2 (en) | High voltage semiconductor devices and methods for their fabrication | |
| CN201570499U (en) | LDMOS device with transverse-diffusion buried layer under grid | |
| CN105514166A (en) | NLDMOS device and manufacture method thereof | |
| CN106298943B (en) | A kind of lateral double diffusion metal oxide semiconductor field-effect tube with bulk electric field modulation | |
| CN104538441B (en) | Radio frequency LDMOS device and its manufacture method | |
| CN103022125B (en) | NLDMOS device in BCD technique and manufacture method | |
| CN104183632B (en) | The self aligned drain terminal field plate structures of RF LDMOS and preparation method | |
| CN104241358A (en) | Radio frequency ldmos device and manufacturing method thereof | |
| CN105679831A (en) | Lateral diffusion field effect transistor and manufacturing method thereof | |
| CN107910358B (en) | LDMOS (laterally diffused metal oxide semiconductor) and manufacturing method thereof | |
| CN104638003B (en) | Radio frequency LDMOS device and process | |
| CN103050510B (en) | ESD (electronic static discharge) device in RFLDMOS (ratio frequency laterally diffused metal oxide semiconductor) process and manufacture method of ESD device | |
| TW200304188A (en) | Semiconductor component and manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |