CN105047705B - A kind of high pressure IGBT and its manufacture method of electron injection enhancement type - Google Patents
A kind of high pressure IGBT and its manufacture method of electron injection enhancement type Download PDFInfo
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- 238000002347 injection Methods 0.000 title claims abstract description 24
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- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000009825 accumulation Methods 0.000 claims abstract description 37
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 23
- 239000010703 silicon Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 229920005591 polysilicon Polymers 0.000 claims abstract description 10
- -1 phosphonium ion Chemical class 0.000 claims description 15
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 239000000969 carrier Substances 0.000 claims description 6
- 229910052681 coesite Inorganic materials 0.000 claims description 6
- 229910052906 cristobalite Inorganic materials 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052682 stishovite Inorganic materials 0.000 claims description 6
- 229910052905 tridymite Inorganic materials 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 abstract description 27
- 230000007423 decrease Effects 0.000 description 10
- 238000003860 storage Methods 0.000 description 10
- 238000004088 simulation Methods 0.000 description 7
- 230000008859 change Effects 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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Abstract
The invention discloses a kind of high pressure IGBT of electron injection enhancement type, in n‑The planar section of in the groove of middle part and both sides is equipped with gate oxide above silicon substrate, and polysilicon layer is equipped with above gate oxide, is known as groove flat grid G；The n of groove flat grid G both sides‑A p base is respectively provided with silicon substrate, and is isolated by gate oxide with groove flat grid G, n in each p bases+Launch site upper surface forms an emitter E respectively with place p bases short circuit；n‑With being equipped with discrete n carrier accumulation layers at both sides p bases bottom connection above drift region；n‑N field stop layers, p+ collecting zones, collector C are equipped with below drift region successively.The invention also discloses the high pressure IGBT manufacture method of above-mentioned electron injection enhancement type.The high pressure IGBT structure of the present invention, significantly improves saturation voltage during break-over of device, blocking voltage is high, on-state loss is low, latch-up current density is higher.
Description
Technical field
The invention belongs to power semiconductor device technical field, is related to a kind of high pressure IGBT of electron injection enhancement type, this
Invention further relates to the high pressure IGBT manufacture method of this kind of electron injection enhancement type.
Background technology
High pressure IGBT needs one of key technical problem solved in development, exactly reduces saturation voltage during on-state.
In existing planar gate IGBT and trench gate IGBT structure, carrier storage (CS) layer is usually introduced, to produce electron injection
Enhancement effect, so as to increase the conductance modulation during conducting, achievees the purpose that to reduce saturation voltage.
But for planar gate IGBT structure, though saturation voltage can be effectively reduced using CS layers, and with higher
Short-circuit capacity, but be still easy to that breech lock occurs at high temperature, cause the reliability decrease of device.To trench gate IGBT structure
Speech, although can effectively suppress latch-up, needs wide grid spacing to obtain higher short-circuit capacity, causes cellular density
Reduce, current capacity declines；Simultaneously because groove is deeper, cause process costs higher.
The content of the invention
It is an object of the invention to provide a kind of high pressure IGBT of electron injection enhancement type, employ groove-planar gate and
Carrier accumulation layer, can effectively reduce its saturation voltage, can meet the application requirement of high voltage switch well.
Another object of the present invention also resides in the high pressure IGBT manufacture method for providing this kind of electron injection enhancement type, makes device
Structure design and the free degree increase that makes, and have relatively simple manufacture craft.
The technical solution adopted by the present invention is a kind of high pressure IGBT of electron injection enhancement type, including as n-Drift region
N-Silicon substrate, in n-The top middle part of silicon substrate is provided with groove, has the thickness identical with the planar section of both sides in the trench
Gate oxide, a T-shaped polysilicon layer is provided with above gate oxide, be known as groove-planar gate G；In groove-flat
The n of face grid G both sides-A p base is each provided with silicon substrate, and is isolated by gate oxide with groove-planar gate G,
A n is provided with each p bases+Launch site, the n per side+The p bases short circuit at launch site upper surface and place is formed respectively
One emitter E；In n-With at both sides p bases bottom connection, being respectively arranged with discrete n carriers storage above drift region
Layer；In n-N field stop layers are provided with below drift region, p+ collecting zones are provided with below n field stop layers, under p+ collecting zones
Side is provided with collector C.
Another technical solution that the present invention uses is a kind of high pressure IGBT manufacturer of above-mentioned electron injection enhancement type
Method, this method carry out according to the following steps：
Step 1：Treated<100>N-type silicon substrate back, is first injected using phosphonium ion, is annealed and is promoted, is formed
N field stop layers；
Step 2：Injected on n field stop layers surface, then using boron ion, anneal and promote, form p+Collecting zone；
Step 3：By thermal oxide in n-Surface of silicon grows one layer of SiO2Masking layer；
Step 4：Along n-Silicon substrate upper end middle part longitudinally sets the window of groove, is carved using reactive ion etching mode
Lose shallow trench；
Step 5：Erode SiO2Masking layer, thermally grown gate oxide, and depositing polysilicon again, using surface planarisation
Method, forms the polysilicon layer of surfacing；
Step 6：Etches polycrystalline Si-gate and gate oxide, form grid G；
Step 7：Injected using boron ion, anneal and promote, p bases are formed on surface；
Step 8：Injected using high energy phosphonium ion, anneal and promote, immediately below p bases and n-Silicon substrate joint is formed
Discrete n carrier accumulation layers；
Step 9：Injected using phosphonium ion, anneal and promote, n is formed in p base region surfaces+Launch site；
Step 10：Electrode preparation, scribing, encapsulation are carried out,.
The invention has the advantages that the high pressure IGBT hereinafter referred to as CS-TP-IGBT of electron injection enhancement type of the present invention,
Groove-planar gate and carrier accumulation layer are employed, its saturation voltage can be effectively reduced, can meet high-power well
The application requirement of switch.
Brief description of the drawings
Fig. 1 is the existing planar gate IGBT structure diagrammatic cross-section with carrier accumulation layer；
Fig. 2 is existing groove-planar gate IGBT structure diagrammatic cross-section；
Fig. 3 is the structural profile illustration that the present invention injects enhanced high pressure IGBT (CS-TP-IGBT)；
Fig. 4 is the schematic equivalent circuit of CS-TP-IGBT structures of the present invention；
Fig. 5 is CS-TP-IGBT of the present invention positive resistances under identical structural parameters with existing TP-IGBT and CS-IGBT
Disconnected simulated behavior curve compares；
Fig. 6 is that CS-TP-IGBT of the present invention turns on spy with existing TP-IGBT and CS-IGBT under identical structural parameters
Property simulation curve compares；
Fig. 7 is for CS-TP-IGBT of the present invention with existing TP-IGBT and CS-IGBT in identical structural parameters and dispatch from foreign news agency travel permit
Turn-on characteristics simulation curve under part compares；
Fig. 8 is for CS-TP-IGBT of the present invention with existing TP-IGBT and CS-IGBT in identical structural parameters and dispatch from foreign news agency travel permit
Turn-off characteristic simulation curve under part compares；
Fig. 9 is I-V characteristics of the CS-TP-IGBT of the present invention with existing TP-IGBT and CS-IGBT under identical structural parameters
Simulation curve variation with temperature compares；
Figure 10 is CS-TP-IGBT blocking voltages of the present invention with trench mesas width WmChange curve；
Figure 11 is CS-TP-IGBT blocking voltages of the present invention with gash depth dtChange curve；
Figure 12 is CS-TP-IGBT blocking voltages of the present invention with accumulation layer concentration NCSChange curve；
Figure 13 is CS-TP-IGBT blocking voltages of the present invention with storage layer thickness WCSChange curve；
Figure 14 is CS-TP-IGBT on state characteristics of the present invention with trench mesas width WmChange curve；
Figure 15 is CS-TP-IGBT on state characteristics of the present invention with gash depth dtChange curve；
Figure 16 is CS-TP-IGBT on state characteristics of the present invention with accumulation layer concentration NCSChange curve；
Figure 17 is CS-TP-IGBT on state characteristics of the present invention with storage layer thickness WCSChange curve.
Embodiment
The present invention is described in detail with reference to the accompanying drawings and detailed description.
With reference to Fig. 1, the conducting channels of existing CS-IGBT structures is on surface, its length is by p bases and n+Spread launch site
Horizontal junction depth difference determine.In addition, there is an a little higher than n of concentration below p bases-The n carrier accumulation layers of drift region.
With reference to Fig. 2, the conducting channels of existing TP-IGBT structures is also on surface, the simply n between two p bases-Drift
Move above area and be provided with a shallow trench, and gash depth is less than the depth of p bases, groove width is less than between the p bases of both sides
Spacing.
With reference to Fig. 3, the high pressure IGBT structure of electron injection enhancement type of the invention is, including as n-The n of drift region-Silicon
Substrate, in n-The top middle part of silicon substrate is provided with (shallow) groove, has thickness phase with the planar section of both sides in the trench
Same gate oxide, is provided with a T-shaped polysilicon layer above gate oxide, is known as groove-planar gate G；Groove-
The n of planar gate G both sides-Be each provided with a p base on silicon substrate, and by gate oxide and groove-planar gate G every
From being provided with a n in each p bases+Launch site, the n per side+The p bases at launch site upper surface and place short circuit difference shape
Into an emitter E；In n-With at both sides p bases bottom connection, being respectively arranged with discrete n carriers storage above drift region
Layer (abbreviation CS)；In n-N field stop layers are provided with below drift region, p+ collecting zones are provided with below n field stop layers, in p+ collection
Collector C is provided with below electric area.
There are three pn-junctions in Fig. 1-Fig. 3 from bottom to top, be referred to as J1, J2, J3Knot.
Fig. 3 and Fig. 1, Fig. 2 are contrasted as it can be seen that including n carriers accumulation layer and groove-plane in the structure of the present invention
Grid, on the basis of existing TP-IGBT structures, keep original groove-planar gate, p bases, n+Launch site, n-Drift region and
N field stop layers, p+ collector region structures below is constant, particularly, in two p bases and n-It is respectively provided between drift region
One n carrier accumulation layer being similar in CS-IGBT structures, other regions do not have significant change.
The state modulator scope of CS-TP-IGBT of the present invention is：
The shape of groove is rectangular channel, smooth at bottom corners, and gash depth is less than the junction depth (depth) of p bases, groove
Width is less than the spacing of both sides p bases, and the surface of p bases is 1~2 μm away from trenched side-wall mesa width.
The concentration of n carrier accumulation layers is 1 × 1015~5 × 1015cm-3When, the thickness of n carrier accumulation layers is 2~3 μ
m。
The operation principle of CS-TP-IGBT of the present invention is,
As shown in figure 3, the high pressure IGBT structure of the present invention, when adding forward voltage (U at CS-TP-IGBT both endsCE>0)
When, J2Tie reverse-biased, undertake forward blocking voltage.Since the concentration of carrier accumulation layer is higher than n-Drift region, causes its blocking voltage
Decline.Simultaneously because there are shallow trench, can be by J2The electric field that knot knee is concentrated is transferred to the bottom of groove, to make up
Influence of the carrier accumulation layer to device blocking voltage；
When CS-TP-IGBT grid Gs add higher than threshold voltage positive grid voltage (UGE>UT) when, table of the raceway groove in p bases
Face is formed, while trenched side-wall can form electron accumulation area, n+Launch site can be by raceway groove and accumulation area to n-Drift region injection electricity
Son, causes J1Knot more positively biased, then collecting zone can be to n-Hole is injected in drift region.Injection a part of hole can with by n+Hair
It is compound to penetrate the electronics that area comes, another part hole can only pass through n+P bases immediately below launch site and flow into emitter.Due to
There are n carrier accumulation layers so that place forms a hole barrier between p bases and n carrier accumulation layers, which can hinder
Only hole passes through p bases, and then this partial holes will be in the n below shallow trench and accumulation layer-Accumulated in drift region.For
Guarantee n-The electroneutral of drift region, n+Launch site will be to n-More electronics are injected in drift region.With existing TP-IGBT and CS-
IGBT is compared, and CS-TP-IGBT of the invention can imitate electron injection enhancement due to there is the double action of shallow trench and accumulation layer
More acutely it should thus strengthen n-The conductance modulation of drift region, causes device integrally to have lower saturation voltage；
When adding minus gate voltage (U in CS-TP-IGBT grid GsGE<0) when, the shut-off of CS-TP-IGBT then with TP-IGBT and
CS-IGBT is identical.First, the raceway groove of p base region surfaces disappears, and has cut off the source of electronics, then, n-Drift region it is non-flat
Weighing apparatus carrier will be gradually reduced by the extraction of the voluntarily compound additional positive voltage of sum aggregate-emitter-base bandgap grading, until all non-equilibrium
Carrier is wholly absent, and CS-TP-IGBT is just thoroughly turned off.
Fig. 4 is the equivalent circuit of the CS-TP-IGBT of the present invention, it is seen then that CS-TP-IGBT devices of the invention are equivalent to one
The parallel circuit of a pnp transistor controlled by MOSFET and pin diodes.
Simplation verification
In order to evaluate the characteristic of CS-TP-IGBT of the present invention, by taking 6.5kV voltage class as an example, structure is established according to Fig. 3
Model, utilizes forward blocking characteristic of the ISE simulation softwares to CS-TP-IGBT at ambient and elevated temperatures、On state characteristic, switch are special
Property and I-V characteristic emulated respectively, and with identical structural parameters (i.e. when storage layer thickness WCSFor 0 when, CS-TP-
IGBT structure is identical with TP-IGBT structures；As gash depth dtFor 0 when, CS-TP-IGBT structures then with CS-IGBT structures
It is identical) existing TP-IGBT and CS-IGBT compare.
1) blocking characteristics
Fig. 5 give the present invention CS-TP-IGBT with existing TP-IGBT and CS-IGBT under identical structural parameters
Forward blocking simulated behavior curve compares.As seen from Figure 5, CS-TP-IGBT forward blocking characteristics of the invention under room temperature 300K
Curve and existing TP-IGBT and CS-IGBT are very close, and the forward blocking voltage of CS-TP-IGBT is lower than TP-IGBT about
20V, than CS-IGBT high about 50V.But under high temperature 420K, the high temperature blocking characteristics curve and TP- of CS-TP-IGBT of the invention
IGBT is almost overlapped, both high-temperature current leakages are slightly less than existing CS-IGBT.
2) on state characteristic
Fig. 6 give the present invention CS-TP-IGBT with existing TP-IGBT and CS-IGBT under identical structural parameters
On state characteristic simulation curve compares.As seen from Figure 6, in 300K the present invention CS-TP-IGBT on-state characteristic substantially than
TP-IGBT goes with CS-IGBT.In 100A/cm2Current density under, CS-TP-IGBT saturation voltages than TP-IGBT it is low about
0.15V, the low about 0.45V than CS-IGBT.And the zero temperature coefficient point of the CS-TP-IGBT of the present invention is lower, corresponding electricity
Current density is only 26A/cm2, illustrate that CS-TP-IGBT high temperature on state characteristics are more preferable.
3) switching characteristic
The CS-TP-IGBT of the invention of Fig. 7, Fig. 8 respectively present invention are with existing TP-IGBT and CS-IGBT identical
The simulated behavior curve that turns on and off under the conditions of structural parameters and external circuit compares.Turn-on characteristics as shown in Figure 7 are as it can be seen that originally
Invention CS-TP-IGBT open with existing TP-IGBT open very close to, but all than existing CS-IGBT open substantially will
It hurry up.Also, it is influenced by temperature equal very little.Turn-off characteristic as shown in Figure 8 is as it can be seen that the shut-off curve of CS-TP-IGBT of the present invention
Almost overlapped with the shut-off curve of existing TP-IGBT, it is slightly slower than CS-IGBT.Also, the tail currents under 420K high temperature are equal
Reduce.
4) I-V characteristic
Fig. 9 is that the I-V of the CS-TP-IGBT and existing TP-IGBT and CS-IGBT of the present invention under identical structural parameters is special
Property simulation curve variation with temperature compares figure.As seen from Figure 9, in 300K, the saturation current density of CS-TP-IGBT compares TP-
IGBT high about 30A/cm2, than CS-IGBT high about 110A/cm2；In 420K, the latch-up current density of CS-TP-IGBT is up to
1150A/cm2, the low about 30A/cm than TP-IGBT2, the high about 240A/cm than CS-IGBT2.Illustrate the anti-door bolt of CS-TP-IGBT
Lock ability is higher.
Every characteristic of device is, it is necessary to key structural parameters, such as gash depth, mesa width and accumulation layer in order to balance
Concentration strictly controlled.Influence of lower these key parameters of surface analysis to device property of the present invention.
Figure 10, Figure 11 are the blocking voltages of the CS-TP-IGBT of the present invention with the change curve of groove parameter.Can by Figure 10
See, with trench mesas width wmIncrease, blocking voltage first increases then rapid decrease, and works as wmAt=1 μm, blocking voltage is most
It is high.As seen from Figure 11, with gash depth dtIncrease, blocking voltage can first increase then rapid decrease, and work as dtAt=3.5 μm,
Blocking voltage highest.Comparatively speaking, influence of the gash depth to blocking voltage is than mesa width wmInfluence bigger, ditch groove width
The influence of degree then very little.It is therefore desirable to strictly control gash depth.
Figure 12, Figure 13 are the blocking characteristics curves of the CS-TP-IGBT of the present invention with the change of storage layer parameter.By Figure 12
As it can be seen that work as WCSAt=2 μm, with accumulation layer concentration NCSIncrease, blocking voltage rapid decrease, and work as NCS=1 × 1016cm-3When,
Blocking voltage declines quickly.As seen from Figure 13, N is worked asCS=1 × 1015cm-3When, with storage layer thickness WCSIncrease, blocking voltage
Decline, and work as WCSAt=4 μm, blocking voltage declines more；Comparatively speaking, accumulation layer concentration NCSInfluence to blocking voltage
Than accumulation layer width WCSInfluence bigger.So accumulation layer concentration NCSNeed strictly to control.
Figure 14, Figure 15 are the CS-TP-IGBT on state characteristics curves of the present invention with the change of groove parameter.As seen from Figure 14,
With trench mesas width WmIncrease, saturation voltage rapid decrease.As seen from Figure 15, with gash depth dtIncrease, saturation voltage
Also can decline.Comparatively speaking, trench mesas width wmHave a great influence to saturation voltage.
Figure 16, Figure 17 are the CS-TP-IGBT on state characteristics curves of the present invention with the change of storage layer parameter.Figure 16 as it can be seen that
Work as WCSAt=2 μm, with accumulation layer concentration NCSIncrease, saturation voltage rapid decrease, and work as NCS=1 × 1016cm-3When, saturation
Voltage declines quickly.As seen from Figure 17, N is worked asCS=1 × 1015cm-3When, with storage layer thickness WCSIncrease, saturation voltage decline
It is less.Comparatively speaking, accumulation layer concentration NCSInfluence to saturation voltage is than accumulation layer width WCSInfluence bigger.So deposit
Reservoir concentration NCSNeed strictly to control.
The CS-TP-IGBT manufacture methods of the present invention, specifically implement according to following steps：
Step 1：Treated<100>N-type silicon substrate back, first using phosphonium ion (P+) injection, anneal and promote,
Form n field stop layers；
Step 2：On n field stop layers surface, then using boron ion (B+) injection, anneal and promote, form p+Collecting zone；
Step 3：By thermal oxide in n-Surface of silicon grows one layer of SiO2Masking layer；
Step 4：Along n-Silicon substrate upper end middle part longitudinally sets the window of groove, utilizes reactive ion etching mode
(RIE) shallow trench is etched；
Step 5：Erode SiO2Masking layer, thermally grown gate oxide, and depositing polysilicon again, using surface planarisation
Method, forms the polysilicon layer of surfacing；
Step 6：Etches polycrystalline Si-gate and gate oxide, form grid G；
Step 7：Using boron ion (B+) injection, anneal and promote, p bases are formed on surface；
Step 8：Using high energy phosphonium ion (P+) injection, anneal and promote, immediately below p bases and n-Silicon substrate joint
Form discrete n carrier accumulation layers；Or referred to as n carriers store (CS) layer
Step 9：Using phosphonium ion (P+) injection, anneal and promote, n is formed in p base region surfaces+Launch site；
Step 10：After the preparation of progress electrode, scribing, encapsulation.
In conclusion the present invention CS-TP-IGBT structures compared with existing TP-IGBT or CS-IGBT structures, in device
Part can produce stronger electron injection enhancement effect during turning on, and cause n-The conductance modulation of drift region is strengthened, can be effectively
Reduce the saturation voltage of device, and good trade-off is obtained between blocking voltage, high temperature latch-up current and saturation current density.
Further, since gash depth is shallower, accumulation layer thickness range is wider, and the free degree of device design and fabrication is larger.In reality
When technique makes, CS-TP-IGBT only needs to increase the etching technics of shallow trench on the Process ba- sis of traditional planar gate IGBT
With the ion implantation technology of accumulation layer, cost is relatively low, is promoted easy to device.
Claims (2)
- A kind of 1. high pressure IGBT of electron injection enhancement type, it is characterised in that：Including as n-The n of drift region-Silicon substrate, in n- The top middle part of silicon substrate is provided with groove, the gate oxide that to have thickness with the planar section of both sides in the trench identical, A T-shaped polysilicon layer is provided with above gate oxide, is known as groove-planar gate G；In groove-planar gate G both sides n-A p base is each provided with silicon substrate, and is isolated by gate oxide with groove-planar gate G, in each p bases It is provided with a n+Launch site, the n per side+The p bases short circuit at launch site upper surface and place forms an emitter E respectively； n-With at both sides p bases bottom connection, being respectively arranged with discrete n carrier accumulation layers above drift region；In n-Below drift region N field stop layers are provided with, p+ collecting zones are provided with below n field stop layers, collector C is provided with below p+ collecting zones；The shape of the groove is rectangular channel, smooth at bottom corners, and gash depth is less than the depth of p bases, and groove width is small Spacing between the p bases of both sides, and the mesa width that p bases upper surface inside edge is formed with side trenched side-wall is 1~2 μm；The concentration of the n carriers accumulation layer is 1 × 1015~5 × 1015cm-3When, the thickness of n carrier accumulation layers is 2~3 μ m。
- 2. the high pressure IGBT manufacture method of the electron injection enhancement type described in a kind of claim 1, it is characterised in that this method is pressed Following steps carry out：Step 1：Treated<100>n-The silicon substrate back side, is first injected using phosphonium ion, is annealed and is promoted, and forms n resistances Only layer；Step 2：Injected on n field stop layers surface, then using boron ion, anneal and promote, form p+Collecting zone；Step 3：By thermal oxide in n-Surface of silicon grows one layer of SiO2Masking layer；Step 4：Along n-Silicon substrate upper end middle part longitudinally sets the window of groove, is etched using reactive ion etching mode Groove,The shape of the groove is rectangular channel, smooth at bottom corners, and gash depth is less than the depth of p bases, and groove width is small Spacing between the p bases of both sides, and the surface of p bases is 1~2 μm away from trenched side-wall mesa width；Step 5：Erode SiO2Masking layer, thermally grown gate oxide, and depositing polysilicon again, using method for planarizing surface, Form the polysilicon layer of surfacing；Step 6：Etches polycrystalline Si-gate and gate oxide, form grid G；Step 7：Injected using boron ion, anneal and promote, p bases are formed on surface；Step 8：Injected using high energy phosphonium ion, anneal and promote, immediately below p bases and n-Silicon substrate joint forms discrete N carrier accumulation layers, the concentration of the n carriers accumulation layer is 1 × 1015~5 × 1015cm-3When, n carrier accumulation layers Thickness is 2~3 μm；Step 9：Injected using phosphonium ion, anneal and promote, n is formed in p base region surfaces+Launch site；Step 10：Electrode preparation, scribing, encapsulation are carried out,.
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| CN105489644B (en) * | 2015-12-30 | 2019-01-04 | 杭州士兰集成电路有限公司 | IGBT device and preparation method thereof |
| CN107342317B (en) * | 2016-04-29 | 2020-08-14 | 株洲中车时代电气股份有限公司 | Novel U-shaped groove IGBT and manufacturing method thereof |
| CN109564943B (en) * | 2017-02-13 | 2022-06-24 | 富士电机株式会社 | Semiconductor device with a plurality of semiconductor chips |
| CN109087945B (en) * | 2018-08-22 | 2021-11-26 | 苏州达晶微电子有限公司 | IGBT manufacturing method |
| CN109713030B (en) * | 2018-12-25 | 2021-12-31 | 郑州师范学院 | RC-IGBT device |
| CN110212027B (en) * | 2019-06-10 | 2022-04-22 | 西安理工大学 | Electron injection enhanced dual-mode MOS control thyristor and manufacturing method thereof |
| CN110491936B (en) * | 2019-08-21 | 2023-05-12 | 江苏中科君芯科技有限公司 | Carrier storage type IGBT device with double polysilicon gates |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101540338A (en) * | 2009-04-29 | 2009-09-23 | 西安理工大学 | Groove flat-grid MOSFET component and fabricating method thereof |
| CN102184950A (en) * | 2011-05-09 | 2011-09-14 | 电子科技大学 | Insulated gate bipolar transistor with cavity blocking layer(s) |
| CN102420133A (en) * | 2011-09-30 | 2012-04-18 | 上海华虹Nec电子有限公司 | Method for manufacturing insulated gate bipolar transistor (IGBT) device |
| CN102800591A (en) * | 2012-08-31 | 2012-11-28 | 电子科技大学 | Preparation method for FS-IGBT device |
| CN103748685A (en) * | 2011-07-14 | 2014-04-23 | Abb技术有限公司 | Insulated gate bipolar transistor |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013114477A1 (en) * | 2012-01-31 | 2013-08-08 | パナソニック株式会社 | Semiconductor device and production method for same |
-
2015
- 2015-06-30 CN CN201510375474.9A patent/CN105047705B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101540338A (en) * | 2009-04-29 | 2009-09-23 | 西安理工大学 | Groove flat-grid MOSFET component and fabricating method thereof |
| CN102184950A (en) * | 2011-05-09 | 2011-09-14 | 电子科技大学 | Insulated gate bipolar transistor with cavity blocking layer(s) |
| CN103748685A (en) * | 2011-07-14 | 2014-04-23 | Abb技术有限公司 | Insulated gate bipolar transistor |
| CN102420133A (en) * | 2011-09-30 | 2012-04-18 | 上海华虹Nec电子有限公司 | Method for manufacturing insulated gate bipolar transistor (IGBT) device |
| CN102800591A (en) * | 2012-08-31 | 2012-11-28 | 电子科技大学 | Preparation method for FS-IGBT device |
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