CN110504312B - Transverse IGBT with short circuit self-protection capability - Google Patents
Transverse IGBT with short circuit self-protection capability Download PDFInfo
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
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- 229910002601 GaN Inorganic materials 0.000 description 2
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- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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Abstract
The invention belongs to the technical field of power semiconductor devices, and relates to a transverse IGBT with short-circuit self-protection capability. According to the transverse IGBT structure with the short-circuit self-protection capability, the PMOS structure and the NMOS structure are integrated on the basis of the traditional IGBT structure, and meanwhile, the diode and the resistor are matched for use, so that a short-circuit self-protection circuit can be formed to protect an IGBT device, when the IGBT is short-circuited, the protection circuit enables a low-resistance path to be formed between a gate electrode and an emitter electrode of the IGBT, the voltage drop on the gate electrode is reduced, the short-circuit current is reduced, the device is prevented from being failed due to short circuit, the short-circuit protection mode is simple and efficient, the integration degree is high, the size is small, and the cost is low.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and relates to a transverse IGBT with short-circuit self-protection capability.
Technical Field
The Insulated Gate Bipolar Transistor (IGBT) is used as a new generation of power electronic device, and combines the advantages of a field effect transistor (MOSFET) and a bipolar crystal transistor (BJT), so that the IGBT has the advantages of easy driving of the MOSFET, low input impedance and high switching speed, and also has the advantages of high on-state current density, low on-state voltage, low loss and good stability of the BJT. Therefore, the high-power electronic circuit is developed into one of core electronic components in modern power electronic circuits and is widely applied to various fields of traffic, communication, household appliances and aerospace. The performance of the power electronic system is greatly improved by the application of the IGBT.
The lateral IGBT is widely concerned due to the characteristic of integration, and for a conventional lateral IGBT device (as shown in fig. 1), a protection circuit formed by dedicated components is generally used to protect the IGBT from short circuit. Detecting voltage V between collector and emitter of IGBT by using deviceceV at short circuit of IGBTceThe voltage rises sharply, and when the voltage exceeds a set value, the component device can turn off the IGBT to play a role in protection. The IGBT short-circuit protection circuit is generally protected by using dedicated components, however, the core technology is mastered by foreign companies,therefore, the protection circuit is high in cost and large in size, cannot meet the application requirements of low-cost and small-size products, and is long in detection process period, slow in response and multiple in problems.
Disclosure of Invention
The invention provides a transverse IGBT structure with short-circuit self-protection capability in order to overcome the defects of the conventional transverse IGBT short-circuit protection method.
The technical scheme of the invention is as follows:
a lateral IGBT structure with short-circuit self-protection capability, the schematic diagram of the cell structure of which is shown in fig. 2 (the cross-sectional views along the line AB, the line CD and the line EF are shown in fig. 3, fig. 4 and fig. 5), comprising: the collector structure comprises a back collector metal 1, a P + type collector region 2, an N type field stop layer 3 and an N-type drift region 4 which are sequentially stacked from bottom to top; the method is characterized in that: a trench structure and an N-type field stop layer are arranged above the N-drift region 4 and along the Z direction, wherein the trench structure comprises a gate dielectric layer 51, a gate electrode 61, a separation gate electrode 62, a separation gate dielectric layer 52 and an isolation dielectric layer 53; an N-type charge storage layer 15 is arranged above the N-drift region 4 and on one side of the groove; a P-type base region 7 is arranged above the N-type charge storage layer 15 and along one side of the groove; a P + contact region 10 and an N + emitter region 9 which are mutually parallel and independent are arranged above the P-type base region 7 along the Z direction and one side of the groove; a P-type doping layer 18, an N-type buried layer 17 and a P-type buried layer 16 are arranged above the N-drift region 4 along the Z direction and along the other side of the trench; an N-type isolation layer 19 is arranged inside the P-type doped layer; a P-type trap 20 is arranged in the N-type isolation layer 19; a P + contact region 23, an N + source region 22 and an N + drain region 21 are arranged in the P-type trap 20 along the Z direction; a P + collector region 11 is arranged in the N-type field stop layer 8; a collector metal 14 is arranged above the P + collector region 11; a dielectric layer 12 and a dielectric layer 27 are arranged above the gate electrode 61, the gate dielectric layer 51 and the isolation dielectric layer 53; a dielectric layer 26 is arranged above the N + source region 22 and above the N + drain region 21; a gate dielectric layer 24 is arranged above the N + source region 22, the N + drain region 21 and the P-type trap 20; a gate electrode 25 is arranged above the gate dielectric layer 24; a contact metal 28 is arranged above the P + contact region 23 and above the N + source region 22; a contact metal 29 is arranged above the N + drain region 21; a contact metal 30 is arranged above the P-type doped layer 18; emitter metal 13 is arranged above the P + contact region 10, above the N + emitter region 9, above the separation gate electrode 62 and above the dielectric layer 12; the gate electrode 61 is shorted to the contact metal 29; a diode 32 and a resistor 33 are connected in series between the contact metal 30 and the emitter metal 13, the anode of the diode 32 is in short circuit with the contact metal 30, the cathode of the diode 32 is in short circuit with the resistor 33, one end of the resistor 33 is in short circuit with the cathode of the diode 32, and the other end of the resistor 33 is in short circuit with the emitter metal 13; the gate electrode 25 is shorted to the anode of the diode 32; the contact metal 28 is shorted to the cathode of the diode 32.
Further, a lateral IGBT structure with short-circuit self-protection capability has a schematic diagram of a cell structure as shown in fig. 6 (its cross-sectional views along the line AB, the line CD and the line EF are shown in fig. 7, fig. 8 and fig. 9), and is characterized in that the N + isolation layer is replaced by an insulating dielectric layer 19.
Further, a schematic diagram of a cell structure of the lateral IGBT structure with short-circuit self-protection capability is shown in fig. 10 (its cross-sectional views along the line AB, the line CD and the line EF are shown in fig. 11, fig. 12 and fig. 13), and is characterized in that a diode 32 is integrated on the surface of the device, the diode 32 is composed of a P-type semiconductor 201, an N-type semiconductor 202, an anode metal 35 and a cathode metal 36, and a dielectric layer 34 is used for isolating the diode from the device.
Further, a lateral IGBT structure with short-circuit self-protection capability, whose cell structure is schematically shown in fig. 14 (its cross-sectional views along the line AB, CD and EF are shown in fig. 15, 16 and 17), is characterized in that the split gate electrode 62 is made to be L-shaped and to half-surround the gate electrode 61.
Further, the semiconductor material of the lateral IGBT device in the invention adopts Si, SiC, GaAs or GaN, the groove filling material adopts polycrystalline Si, SiC, GaAs or GaN, and each part can adopt the same material or different material combinations.
Furthermore, the device structure is not only suitable for an IGBT device, but also suitable for an MOSFET device, and the P-type collector region 11 on the back of the device is replaced by an N + layer.
Working principle of the invention
When the emitter 13 is connected with a low potential, the collector 14 is connected with a high potential, and the gate electrode 61 is connected with a high potential which is larger than the threshold voltage, the device is in a forward conducting state, current flows away from the MOS channel of the IGBT, when the collector voltage continues to increase, the PMOS formed by the P-type buried layer 16, the N-type buried layer 17, the P-type doped layer 18 and the separation gate electrode 62 is opened, an extra path is provided for the current flow, a voltage drop is generated on the resistor 32 when the current flows through the resistor 32, when the device works in a stable state and the resistance value of the resistor 32 is set to ensure that the voltage drop on the resistor 32 is not small enough to invert the surface of the P trap 20 below the polycrystalline gate electrode 26, the NMOS formed by the N + source region 22, the P trap 20, the N + drain region 21 and the gate electrode 26 is in a non-conducting state, however, when the device is short-circuited, the current flowing through the, the voltage drop on the resistor 32 is increased, when the voltage drop on the resistor 32 is large enough to make the surface of the P trap 20 below the polycrystalline gate electrode 26 inverted, the integrated NOMS is turned on, so that a low-resistance path is formed between the gate electrode 61 and the emitter, the voltage drop on the gate electrode 61 is reduced along with the low-resistance path, the short-circuit current of the device is reduced, and the device is protected from being damaged due to short circuit.
The beneficial effects of the invention are as follows:
aiming at the defects of the existing short-circuit protection method of the transverse IGBT, the transverse IGBT structure with the short-circuit self-protection capability provided by the invention can form a short-circuit self-protection circuit to protect an IGBT device by integrating a PMOS structure and an NMOS structure on the basis of the traditional IGBT structure and matching with the use of a diode and a resistor, when the IGBT is in short circuit, the protection circuit enables a low-resistance path to be formed between the IGBT gate electrode and an emitter electrode, so that the voltage drop on the gate electrode is reduced, the short-circuit current is reduced, the failure of the device due to the short circuit is avoided, and the short-circuit protection method is simple and efficient, the integration level is high, the size is small, and the cost is low.
Drawings
Fig. 1 is a schematic diagram of a half-cell structure of a conventional lateral IGBT, where 1 is a substrate electrode, 2 is a P-type substrate, 3 is a buried dielectric layer, 4 is an N-drift region, 5 is a gate dielectric layer, 6 is a gate electrode, 7 is a P-type base region, 8 is an N-type field stop layer, 9 is an N + emitter region, 10 is a P + contact region, 11 is a P + collector region, 12 is a dielectric layer, and 13 is an emitter metal.
Fig. 2 is a schematic diagram of a lateral IGBT structure cell with short-circuit self-protection capability according to embodiment 1 of the present invention.
Fig. 3 is a cross-sectional view of a lateral IGBT structure with short-circuit self-protection capability according to embodiment 1 of the present invention along line AB.
Fig. 4 is a cross-sectional view of a lateral IGBT structure with short-circuit self-protection capability according to embodiment 1 of the present invention along the CD line.
Fig. 5 is a cross-sectional view of a lateral IGBT structure with short-circuit self-protection capability according to embodiment 1 of the present invention along the EF line.
Fig. 6 is a schematic diagram of a lateral IGBT structure cell with short-circuit self-protection capability according to embodiment 2 of the present invention.
Fig. 7 is a cross-sectional view of a lateral IGBT structure with short-circuit self-protection capability according to embodiment 2 of the present invention along line AB.
Fig. 8 is a cross-sectional view of a lateral IGBT structure with short-circuit self-protection capability according to embodiment 2 of the present invention along the CD line.
Fig. 9 is a cross-sectional view of a lateral IGBT structure with short-circuit self-protection capability according to embodiment 2 of the present invention along the EF line.
Fig. 10 is a schematic diagram of a lateral IGBT structure cell with short-circuit self-protection capability according to embodiment 3 of the present invention.
Fig. 11 is a cross-sectional view of a lateral IGBT structure with short-circuit self-protection capability according to embodiment 3 of the present invention along line AB.
Fig. 12 is a cross-sectional view of a lateral IGBT structure with short-circuit self-protection capability according to embodiment 3 of the present invention along the CD line.
Fig. 13 is a cross-sectional view of a lateral IGBT structure with short-circuit self-protection capability according to embodiment 3 of the present invention along the EF line.
Fig. 14 is a schematic diagram of a lateral IGBT structure cell with short-circuit self-protection capability according to embodiment 4 of the present invention.
Fig. 15 is a cross-sectional view of a lateral IGBT structure with short-circuit self-protection capability according to embodiment 4 of the present invention along line AB.
Fig. 16 is a cross-sectional view of a lateral IGBT structure with short-circuit self-protection capability according to embodiment 4 of the present invention along the CD line.
Fig. 17 is a cross-sectional view of a lateral IGBT structure with short-circuit self-protection capability according to embodiment 4 of the present invention along the EF line.
Fig. 18 is a schematic diagram of a lateral IGBT structure cell with short-circuit self-protection capability according to embodiment 5 of the present invention.
Fig. 19 is a cross-sectional view of a lateral IGBT structure with short-circuit self-protection capability according to embodiment 5 of the present invention along line AB.
Fig. 20 is a cross-sectional view of a lateral IGBT structure with short-circuit self-protection capability according to embodiment 5 of the present invention along the CD line.
Fig. 21 is a cross-sectional view of a lateral IGBT structure with short-circuit self-protection capability according to embodiment 5 of the present invention along the EF line.
In fig. 2 to 21, where 1 is a substrate electrode, 2 is a P-type substrate, 3 is a buried dielectric layer, 4 is an N-drift region, 51 is a gate dielectric layer, 52 is a split gate dielectric layer, 53 is an isolation dielectric layer, 54 is a dielectric layer, 61 is a gate electrode, 62 is a split gate electrode, 7 is a P-type base region, 8 is an N-type field stop layer, 9 is an N + emitter region, 10 is a P + contact region, 11 is a P + collector region, 12 is a dielectric layer, 13 is an emitter metal, 14 is a collector metal, 15 is an N-type charge storage region, 16 is a P-type buried layer, 17 is an N-type buried layer, 18 is a P-type doped layer, 19 is an N + isolation layer 191, an isolation dielectric layer, 20 is a P-type trap, 21 is an N + drain region, 22 is an N + source region, 23 is a P + contact region, 24 is a gate dielectric layer, 25 is a gate electrode, 26 is a dielectric layer, 27 is a dielectric layer, 30 is contact metal, 31 is gate electrode metal, 32 is diode, 33 is resistor, 34 is dielectric layer, 35 is anode metal, 36 is cathode metal, 37 is isolation dielectric layer, 38 is doped polysilicon, 39 is contact metal, 40 is contact metal, 201 is P-type semiconductor, 202 is N-type semiconductor.
Detailed Description
The principles and features of this invention will be further explained with reference to the drawings, which are provided for illustration purposes only and are not intended to limit the scope of the invention.
Example 1
A lateral IGBT structure with short-circuit self-protection capability, the schematic diagram of the cell structure of which is shown in fig. 2 (the cross-sectional views along the line AB, the line CD and the line EF are shown in fig. 3, fig. 4 and fig. 5), comprising: the collector structure comprises a back collector metal 1, a P + type collector region 2, an N type field stop layer 3 and an N-type drift region 4 which are sequentially stacked from bottom to top; the method is characterized in that: a trench structure and an N-type field stop layer are arranged above the N-drift region 4 and along the Z direction, wherein the trench structure comprises a gate dielectric layer 51, a gate electrode 61, a separation gate electrode 62, a separation gate dielectric layer 52 and an isolation dielectric layer 53; an N-type charge storage layer 15 is arranged above the N-drift region 4 and on one side of the groove; a P-type base region 7 is arranged above the N-type charge storage layer 15 and along one side of the groove; a P + contact region 10 and an N + emitter region 9 which are mutually parallel and independent are arranged above the P-type base region 7 along the Z direction and one side of the groove; a P-type doping layer 18, an N-type buried layer 17 and a P-type buried layer 16 are arranged above the N-drift region 4 along the Z direction and along the other side of the trench; an N-type isolation layer 19 is arranged inside the P-type doped layer; a P-type trap 20 is arranged in the N-type isolation layer 19; a P + contact region 23, an N + source region 22 and an N + drain region 21 are arranged in the P-type trap 20 along the Z direction; a P + collector region 11 is arranged in the N-type field stop layer 8; a collector metal 14 is arranged above the P + collector region 11; a dielectric layer 12 and a dielectric layer 27 are arranged above the gate electrode 61, the gate dielectric layer 51 and the isolation dielectric layer 53; a dielectric layer 26 is arranged above the N + source region 22 and above the N + drain region 21; a gate dielectric layer 24 is arranged above the N + source region 22, the N + drain region 21 and the P-type trap 20; a gate electrode 25 is arranged above the gate dielectric layer 24; a contact metal 28 is arranged above the P + contact region 23 and above the N + source region 22; a contact metal 29 is arranged above the N + drain region 21; a contact metal 30 is arranged above the P-type doped layer 18; emitter metal 13 is arranged above the P + contact region 10, above the N + emitter region 9, above the separation gate electrode 62 and above the dielectric layer 12; the gate electrode 61 is shorted to the contact metal 29; a diode 32 and a resistor 33 are connected in series between the contact metal 30 and the emitter metal 13, the anode of the diode 32 is in short circuit with the contact metal 30, the cathode of the diode 32 is in short circuit with the resistor 33, one end of the resistor 33 is in short circuit with the cathode of the diode 32, and the other end of the resistor 33 is in short circuit with the emitter metal 13; the gate electrode 25 is shorted to the anode of the diode 32; the contact metal 28 is shorted to the cathode of the diode 32; the gate electrode 61 is connected with the P + contact region 10, the N + emitter region 9, the P-type base region 7, the N-type charge storage layer 15 and the N-drift region 4 through a gate dielectric layer 51, the gate electrode 61 is connected with the separation gate electrode 62 through an isolation dielectric layer 53, and the gate electrode 61 is short-circuited with the gate electrode metal 31; the separation gate electrode is connected with the P-type doping layer 18, the N-type buried layer 17 and the P-type buried layer 16 through a separation gate dielectric layer 52; the diode 32 may be a PN junction diode, a schottky diode, a SiC diode; the contact metal 30 may be an ohmic contact metal or a schottky contact metal.
Example 2
A lateral IGBT structure with short-circuit self-protection capability, the schematic diagram of the cell structure of which is shown in fig. 6 (the cross-sectional views along the line AB, the line CD and the line EF are shown in fig. 7, fig. 8 and fig. 9), comprising: the collector structure comprises a back collector metal 1, a P + type collector region 2, an N type field stop layer 3 and an N-type drift region 4 which are sequentially stacked from bottom to top; the method is characterized in that: a trench structure and an N-type field stop layer are arranged above the N-drift region 4 and along the Z direction, wherein the trench structure comprises a gate dielectric layer 51, a gate electrode 61, a separation gate electrode 62, a separation gate dielectric layer 52 and an isolation dielectric layer 53; an N-type charge storage layer 15 is arranged above the N-drift region 4 and on one side of the groove; a P-type base region 7 is arranged above the N-type charge storage layer 15 and along one side of the groove; a P + contact region 10 and an N + emitter region 9 which are mutually parallel and independent are arranged above the P-type base region 7 along the Z direction and one side of the groove; a P-type doping layer 18, an N-type buried layer 17 and a P-type buried layer 16 are arranged above the N-drift region 4 along the Z direction and along the other side of the trench; an isolation dielectric layer 191 is arranged inside the P-type doped layer; a P-type trap 20 is arranged in the isolation medium layer 191; a P + contact region 23, an N + source region 22 and an N + drain region 21 are arranged in the P-type trap 20 along the Z direction; a P + collector region 11 is arranged in the N-type field stop layer 8; a collector metal 14 is arranged above the P + collector region 11; a dielectric layer 12 and a dielectric layer 27 are arranged above the gate electrode 61, the gate dielectric layer 51 and the isolation dielectric layer 53; a dielectric layer 26 is arranged above the N + source region 22 and above the N + drain region 21; a gate dielectric layer 24 is arranged above the N + source region 22, the N + drain region 21 and the P-type trap 20; a gate electrode 25 is arranged above the gate dielectric layer 24; a contact metal 28 is arranged above the P + contact region 23 and above the N + source region 22; a contact metal 29 is arranged above the N + drain region 21; a contact metal 30 is arranged above the P-type doped layer 18; emitter metal 13 is arranged above the P + contact region 10, above the N + emitter region 9, above the separation gate electrode 62 and above the dielectric layer 12; the gate electrode 61 is shorted to the contact metal 29; a diode 32 and a resistor 33 are connected in series between the contact metal 30 and the emitter metal 13, the anode of the diode 32 is in short circuit with the contact metal 30, the cathode of the diode 32 is in short circuit with the resistor 33, one end of the resistor 33 is in short circuit with the cathode of the diode 32, and the other end of the resistor 33 is in short circuit with the emitter metal 13; the gate electrode 25 is shorted to the anode of the diode 32; the contact metal 28 is shorted to the cathode of the diode 32; the gate electrode 61 is connected with the P + contact region 10, the N + emitter region 9, the P-type base region 7, the N-type charge storage layer 15 and the N-drift region 4 through a gate dielectric layer 51, the gate electrode 61 is connected with the separation gate electrode 62 through an isolation dielectric layer 53, and the gate electrode 61 is short-circuited with the gate electrode metal 31; the separation gate electrode is connected with the P-type doping layer 18, the N-type buried layer 17 and the P-type buried layer 16 through a separation gate dielectric layer 52; the diode 32 may be a PN junction diode, a schottky diode, a SiC diode; the contact metal 30 may be an ohmic contact metal or a schottky contact metal.
Example 3
A lateral IGBT structure with short-circuit self-protection capability, whose cell structure schematic diagram is shown in fig. 10 (its cross-sectional views along the line AB, the line CD and the line EF are shown in fig. 11, fig. 12 and fig. 13), characterized in that: the diode 31 is integrated on the surface of the device on the basis of embodiment 1, the diode 31 is composed of a P-type semiconductor 201, an N-type semiconductor 202, an anode metal 35 and a cathode metal 36, and the dielectric layer 34 is used for isolating the diode from the device.
Integrating the diode 31 into the device surface improves the integration of the device and simplifies the complexity of the external circuitry.
Example 4
A lateral IGBT structure with short-circuit self-protection capability, whose cell structure schematic diagram is shown in fig. 14 (its cross-sectional views along the line AB, the line CD and the line EF are shown in fig. 15, fig. 16 and fig. 17), characterized in that: the split gate electrode 62 is formed in an L-shape to surround the gate electrode 61 in half on the basis of embodiment 2.
Making the split gate electrode 62L-shaped reduces miller capacitance and increases device switching speed.
Example 5
A lateral IGBT structure with short-circuit self-protection capability, whose cell structure schematic diagram is shown in fig. 18 (its cross-sectional views along the line AB, the line CD and the line EF are shown in fig. 19, fig. 20 and fig. 21), characterized in that: on the basis of embodiment 3, the resistor 32 is integrated on the surface of the device, the resistor 32 is composed of doped polysilicon 38, contact metal 39 and contact metal 40, and the dielectric layer 37 is used for isolating the resistor from the device.
Integrating resistor 32 into the surface of the device improves device integration and simplifies the complexity of the external circuitry.
Claims (6)
1. A lateral IGBT with short-circuit self-protection capability has a cellular structure comprising: the back collector metal (1), the P + type collector region (2), the buried dielectric layer (3) and the N-type drift region (4) are sequentially stacked from bottom to top; defining the three-dimensional direction of the device by a three-dimensional rectangular coordinate system: defining the transverse direction of the device as the x-axis direction, the vertical direction of the device as the y-axis direction, and the longitudinal direction of the device, namely the third dimension direction, as the z-axis direction; the method is characterized in that: along the z-axis direction, two ends of the upper layer of the N-drift region (4) are respectively provided with a trench structure and an N-type field stop layer (8), wherein the trench structure comprises a trench gate dielectric layer (51), a trench gate electrode (61), a separation gate electrode (62), a separation gate dielectric layer (52) and an isolation dielectric layer (53); an N-type charge storage layer (15) is arranged above the N-drift region (4) and on one side of the groove; a P-type base region (7) is arranged above the N-type charge storage layer (15) and along one side of the groove; a first P + contact area (10) and an N + emitter area (9) are arranged above the P-type base area (7) in parallel along the z direction and one side of the groove; a P-type doping layer (18), an N-type buried layer (17) and a P-type buried layer (16) are arranged above the N-drift region (4) along the z direction and along the other side of the trench; an N-type isolation layer (19) is arranged inside the P-type doped layer; a P-type trap (20) is arranged in the N-type isolation layer (19); a second P + contact region (23), an N + source region (22) and an N + drain region (21) are arranged in the P-type trap (20) along the Z direction; a P + collector region (11) is arranged in the N-type field stop layer (8); a collector metal (14) is arranged above the P + collector region (11); a first dielectric layer (12) and a second dielectric layer (27) are arranged above the trench gate electrode (61), the trench gate dielectric layer (51) and the isolation dielectric layer (53); a third dielectric layer (26) is arranged above the N + source region (22) and above the N + drain region (21); a gate dielectric layer (24) is arranged above the N + source region (22), the N + drain region (21) and the P-type trap (20); a gate electrode (25) is arranged above the gate dielectric layer (24); a first contact metal (28) is arranged above the second P + contact region (23) and above the N + source region (22); a second contact metal (29) is arranged above the N + drain region (21); a third contact metal (30) is arranged above the P-type doped layer (18); emitter metal (13) is arranged above the first P + contact region (10), above the N + emitter region (9), above the separation gate electrode (62) and above the first dielectric layer (12); the trench gate electrode (61) is shorted to a second contact metal (29); a diode (32) and a resistor (33) are connected in series between the third contact metal (30) and the emitter metal (13), the anode of the diode (32) is in short circuit with the third contact metal (30), the cathode of the diode (32) is in short circuit with the resistor (33), one end of the resistor (33) is in short circuit with the cathode of the diode (32), and the other end of the resistor (33) is in short circuit with the emitter metal (13); the gate electrode (25) is short-circuited with the anode of the diode (32); the first contact metal (28) is shorted to a cathode of a diode (32); the trench gate electrode (61) is connected with the first P + contact region (10), the N + emitter region (9), the P-type base region (7), the N-type charge storage layer (15) and the N-drift region (4) through a trench gate dielectric layer (51), the trench gate electrode (61) is connected with the separation gate electrode (62) through an isolation dielectric layer (53), and the trench gate electrode (61) is in short circuit with the gate electrode metal (31); the separation gate electrode is connected with the P-type doping layer (18), the N-type buried layer (17) and the P-type buried layer (16) through a separation gate dielectric layer (52); the diode (32) is one of a PN junction diode, a Schottky diode and a SiC diode; the third contact metal (30) is an ohmic contact metal or a Schottky contact metal.
2. The lateral IGBT with short-circuit self-protection capability according to claim 1, characterized in that a diode (31) is integrated on the surface of the device, the diode (31) is composed of a P-type semiconductor (201), an N-type semiconductor (202), an anode metal (35) and a cathode metal (36), and the fourth dielectric layer (34) is used for isolating the diode from the device.
3. The lateral IGBT with short-circuit self-protection capability according to claim 2, characterized in that the resistor (32) is integrated on the surface of the device, the resistor (32) is composed of doped polysilicon (38), a fourth contact metal (39) and a fifth contact metal (40), and a fifth dielectric layer (37) is used for isolating the resistor from the device.
4. Lateral IGBT with short-circuit self-protection capability according to claim 1, characterized by the device structure is not only suitable for IGBT devices, but also for MOSFET devices, with the P-type collector region (11) on the back of the device being replaced by an N + layer.
5. A lateral IGBT with short-circuit self-protection capability has a cellular structure comprising: the back collector metal (1), the P + type collector region (2), the buried dielectric layer (3) and the N-type drift region (4) are sequentially stacked from bottom to top; defining the three-dimensional direction of the device by a three-dimensional rectangular coordinate system: defining the transverse direction of the device as the x-axis direction, the vertical direction of the device as the y-axis direction, and the longitudinal direction of the device, namely the third dimension direction, as the z-axis direction; the method is characterized in that: along the z-axis direction, two ends of the upper layer of the N-drift region (4) are respectively provided with a trench structure and an N-type field stop layer (8), wherein the trench structure comprises a trench gate dielectric layer (51), a trench gate electrode (61), a separation gate electrode (62), a separation gate dielectric layer (52) and an isolation dielectric layer (53); an N-type charge storage layer (15) is arranged above the N-drift region (4) and on one side of the groove; a P-type base region (7) is arranged above the N-type charge storage layer (15) and along one side of the groove; a first P + contact region (10) and an N + emitter region (9) which are mutually parallel and independent are arranged above the P-type base region (7) along the Z direction and one side of the groove; a P-type doping layer (18), an N-type buried layer (17) and a P-type buried layer (16) are arranged above the N-drift region (4) along the Z direction and along the other side of the groove; an isolation dielectric layer (191) is arranged inside the P-type doped layer; a P-type trap (20) is arranged in the isolation medium layer (191); a second P + contact region (23), an N + source region (22) and an N + drain region (21) are arranged in the P-type trap (20) along the Z direction; a P + collector region (11) is arranged in the N-type field stop layer (8); a collector metal (14) is arranged above the P + collector region (11); a first dielectric layer (12) and a second dielectric layer (27) are arranged above the trench gate electrode (61), the trench gate dielectric layer (51) and the isolation dielectric layer (53); a third dielectric layer (26) is arranged above the N + source region (22) and above the N + drain region (21); a gate dielectric layer (24) is arranged above the N + source region (22), the N + drain region (21) and the P-type trap (20); a gate electrode (25) is arranged above the gate dielectric layer (24); a first contact metal (28) is arranged above the second P + contact region (23) and above the N + source region (22); a second contact metal (29) is arranged above the N + drain region (21); a third contact metal (30) is arranged above the P-type doped layer (18); emitter metal (13) is arranged above the first P + contact region (10), above the N + emitter region (9), above the separation gate electrode (62) and above the first dielectric layer (12); the trench gate electrode (61) is shorted to a second contact metal (29); a diode (32) and a resistor (33) are connected in series between the third contact metal (30) and the emitter metal (13), the anode of the diode (32) is in short circuit with the third contact metal (30), the cathode of the diode (32) is in short circuit with the resistor (33), one end of the resistor (33) is in short circuit with the cathode of the diode (32), and the other end of the resistor (33) is in short circuit with the emitter metal (13); the gate electrode (25) is short-circuited with the anode of the diode (32); the first contact metal (28) is shorted to a cathode of a diode (32); the trench gate electrode (61) is connected with the first P + contact region (10), the N + emitter region (9), the P-type base region (7), the N-type charge storage layer (15) and the N-drift region (4) through a trench gate dielectric layer (51), the trench gate electrode (61) is connected with the separation gate electrode (62) through an isolation dielectric layer (53), and the trench gate electrode (61) is in short circuit with the gate electrode metal (31); the separation gate electrode is connected with the P-type doping layer (18), the N-type buried layer (17) and the P-type buried layer (16) through a separation gate dielectric layer (52); the diode (32) is one of a PN junction diode, a Schottky diode and a SiC diode; the third contact metal (30) is an ohmic contact metal or a Schottky contact metal.
6. A lateral IGBT with short-circuit self-protection capability according to claim 5, characterized in that the split-gate electrode (62) is made L-shaped to half-surround the trench-gate electrode (61).
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