CN112259597A - TVS device - Google Patents
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- CN112259597A CN112259597A CN202010974113.7A CN202010974113A CN112259597A CN 112259597 A CN112259597 A CN 112259597A CN 202010974113 A CN202010974113 A CN 202010974113A CN 112259597 A CN112259597 A CN 112259597A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 229920005591 polysilicon Polymers 0.000 claims abstract description 23
- 230000015556 catabolic process Effects 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 238000000407 epitaxy Methods 0.000 claims description 23
- 239000003990 capacitor Substances 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 6
- 238000012858 packaging process Methods 0.000 claims description 2
- 230000001052 transient effect Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 12
- 230000001960 triggered effect Effects 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
- H01L29/745—Gate-turn-off devices with turn-off by field effect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
- H01L29/745—Gate-turn-off devices with turn-off by field effect
- H01L29/7455—Gate-turn-off devices with turn-off by field effect produced by an insulated gate structure
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/044—Physical layout, materials not provided for elsewhere
Abstract
The invention discloses a TVS device which is connected with a resistance-capacitance delay circuit and comprises a P substrate material, an N-type epitaxial layer, a P-type trap (Pwell) growing on the surface of the N-type epitaxial layer, an N-type heavily doped region (N + region) on the surface of the Pwell, a polycrystalline silicon (POLY) gate and a polycrystalline resistor, wherein a semiconductor main body of a multi-cell structure is formed; the N + region on the surface is used as a drain electrode, the N-type epitaxial layer is used as a source electrode, Pwell is used as a substrate, polysilicon is used as a grid electrode to form an N-type MOS structure, and the breakdown voltage of the similar insulated gate bipolar transistor structure is controlled to be between 6V and 40V, so that the N-type MOS structure is used for electrostatic and low-voltage surge protection.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a TVS device with a similar insulated gate bipolar transistor structure and controlled by capacitance-blocking delay.
Background
The TVS device is generally used at a port of a PCB board to discharge a transient high voltage entering from the port to GND or an adjacent differential mode signal port, thereby preventing a protected chip from being damaged. When the transient voltage is higher than the breakdown voltage, the clamping voltage of the TVS is easy to control and meets the protection requirement; when the working voltage is 12V to 24V, the clamping voltage is influenced by TVS avalanche breakdown PN junction, the protection function can not be satisfied, and the protected chip is damaged.
In recent years, a silicon controlled rectifier (also called thyristor, SCR) structure is widely applied to a Transient Voltage Super (TVS) device, a circuit capable of meeting a 3.3-30V working Voltage is designed by designing a trigger structure and a PN junction capable of bearing withstand Voltage, and a Snapback characteristic of the circuit enables a clamp Voltage to be excellent, so that the ultrahigh static protection requirement of a signal port is met. However, due to the structural limitation, the starting voltage is high, and the leakage current path is started only after the external voltage is higher than the breakdown voltage, so that the requirement of low-voltage surge is difficult to meet. As shown in the circuit diagram of the TVS device with the MOS-triggered SCR structure in fig. 1, a commonly implemented method is a TVS device with a MOS-triggered surface junction lateral structure SCR, the SCR partial sectional view is as shown in the structure and the circuit diagram of the TVS device with the MOS-triggered surface junction lateral structure SCR in fig. 2, the TVS device is connected in parallel between a port and GND, an Anode is connected with a high potential, a Cathode is connected with a low potential, when the TVS is not turned on without a transient voltage, a capacitor C is charged by a resistor R, an input end of an inverter formed by a PMOS and an NMOS is at the high potential and an output end is at the low potential, a gate electrode of the MOS-triggered surface junction lateral structure SCR is at the low potential and cannot form a conductive channel, an N +/Pwell junction in the SCR structure bears, and the device is in a non-conductive and voltage-. When high transient voltage such as electrostatic event occurs at the anode, firstly, a PMOS path of the inverter provides high potential for an MOS polycrystalline grid, grid charge enables a channel to be inverted, current occurs between a source and a drain of the MOS, electronic current is injected into an N-type epitaxy through the channel, namely, base driving current of a PNP type transistor is provided, the PNPN thyristor is started, and transient voltage is clamped. The delay circuit is composed of the resistance capacitor and the inverter, and provides stable voltage for the grid after the circuit is started to work for a period of time, so that the burning caused by overlarge channel current is prevented.
However, the horizontal structure is difficult to control the uniform distribution of current, the limit capacity of the unit area is poor, the utilization rate of the horizontal area is low, and the through-current capacity of the product is limited. In order to solve the above problems, the present invention provides a TVS device with a novel igbt-like structure.
The equivalent circuit diagram of part of the insulated gate bipolar transistor device is shown in figure 3, the cross section diagram of the FS-IGBT device is shown in figure 4, and the N-concentration of a drift region in the structure is very low, the thickness is generally more than 100um, a gate oxide layer is thicker, the IGBT device has high withstand voltage and strong current capacity, is generally applied to the aspect of power control and is not suitable for transient surge protection such as ESD.
Disclosure of Invention
Aiming at the application of transient surge protection, the invention provides a TVS device with a similar insulated gate bipolar transistor structure and controlled by capacitance-blocking delay.
The purpose of the invention is realized by the following scheme: a TVS device is connected with a resistance-capacitance delay circuit and comprises a P substrate material, an N-type epitaxial layer, a P-type trap (Pwell) growing on the surface of the N-type epitaxial layer, an N-type heavily doped region (N + region) on the surface of the Pwell, a polycrystalline silicon (POLY) gate and a polycrystalline resistor, wherein a semiconductor main body of a multi-cell structure is formed, and a PNPN longitudinal junction Silicon Controlled Rectifier (SCR) structure is formed by the P substrate material, the N-type epitaxial layer, the P-type trap and the N + region on the surface; the N + region on the surface is used as a drain electrode, the N-type epitaxial layer is used as a source electrode, Pwell is used as a substrate, polysilicon is used as a grid electrode to form an N-type MOS structure, and the breakdown voltage of the similar insulated gate bipolar transistor structure is controlled to be between 6V and 40V, so that the N-type MOS structure is used for electrostatic and low-voltage surge protection.
The invention relates to an improved similar insulated gate bipolar transistor device, wherein an SCR structure is opened and conducted to discharge charges when in transient high-voltage rising edge by adding an MOS structure.
On the basis of the scheme, the resistance-capacitance delay circuit is composed of a resistance capacitor and an MOS inverter, and a longitudinal junction silicon controlled structure with breakdown voltage of 6-40V is formed by designing the sizes and the intervals of a P substrate material, an N type epitaxial layer, a Pwell and an N + region. The invention can control the MOS switch by designing the resistance-capacitance and the phase inverter with proper parameters, and obtain the TVS with the similar insulated gate bipolar transistor structure with ideal performance. The delay circuit composed of the resistance-capacitance and the inverter supplies a stable potential to the gate.
Furthermore, by designing the doping concentration and thickness of the N + region, the Pwell and the N-type epitaxial layer and the thickness of the polysilicon gate oxide, an N-type MOS structure with the turn-on voltage of 0.5V-2V and the on-resistance of not more than 0.2 ohm is formed. I.e. to obtain a proper turn-on voltage and as low on-resistance as possible.
The invention can properly design the thickness of the gate oxide layer, the doping concentration and the thickness of the N + region on the surface, the Pwell and the N-type epitaxial layer, and obtain proper threshold voltage, such as 0.5V-2V. The TVS device is started to work when transient voltage appears at an anode, firstly, a PMOS path of a phase inverter provides high potential for an MOS polycrystalline grid, grid charge enables a channel to be inverted, current appears between a source and a drain of the MOS, electronic current is injected into an N-type epitaxial layer through the channel, namely, base driving current of a PNP transistor is provided, and the PNPN thyristor is started to clamp the transient voltage. The delay circuit is composed of the resistance capacitor and the inverter, and provides stable voltage for the grid after the circuit is started to work for a period of time, so that the burning caused by overlarge channel current is prevented. The grid structure of VDMOS can be designed to replace the plane polycrystal grid, the MOS channel current path is changed into the longitudinal direction, the current density of VDMOS can be larger than LDMOS, and the triggering and the turn-off are easier to control.
In the invention, P + implantation on the back of a wafer of the IGBT is replaced by a P substrate material to form an anode of a quasi-insulated gate bipolar transistor structure;
an N-type epitaxial layer replaces an N-type buffer layer and an N-type drift region of the IGBT to form a source region of an MOS in the quasi-insulated gate bipolar transistor structure;
the quasi-insulated gate bipolar transistor structure is designed into a multi-cell structure, which is beneficial to increasing the limit current capacity.
On the basis of the scheme, the P substrate material adopts a P + substrate, one side of an N + region on the surface of the Pwell is provided with a P type heavily doped region (P + region) as a thyristor Gate turn-off Control (GTO Gate Control), the other side of the N + region or the other side of the N + region is provided with a polysilicon POLY which is respectively connected with the N +, the Pwell and the N epitaxy to form an MOS structure which takes the N + region as a drain electrode, the N type epitaxy layer as a source electrode, the Pwell as a substrate and the polysilicon as a grid electrode, wherein the P + substrate is connected with an anode, the P + region and the N + region are connected with a cathode, and the polysilicon POLY as an MOS polycrystal Gate is controlled by an MOS inverter.
The invention changes the substrate type relative to the IGBT, uses thinner epitaxy, reduces the thickness of a gate oxide layer, and combines a capacitance resistor and an inverter to form a control logic to obtain the TVS device with the similar insulated gate bipolar transistor structure controlled by the capacitance-blocking delay.
The principle of the invention is as follows: a delay circuit is formed by a resistance-capacitance device and an inverter, and proper threshold voltage is obtained by designing the thickness of a gate oxide layer, the doping concentration and the thickness of an N-type heavily doped surface, a P-type trap and an N-type epitaxial layer, for example, the typical threshold is 0.5V-2V). When the circuit where the TVS is located normally works, the resistance-capacitance and the phase inverter form a delay circuit, before the circuit starts to work, a stable potential is provided, the MOS is turned off, and the TVS keeps a low leakage current state. When the transient voltage rising edge of the TVS device exceeding the working voltage comes, firstly, a PMOS path of an inverter provides high potential for an MOS polycrystalline grid, grid charge enables a channel to be inverted, current appears between a source electrode and a drain electrode of the MOS, electron current is injected to an N-type epitaxy through the channel, namely, base electrode driving current of a PNP-type transistor is provided, the PNPN thyristor is started, and transient voltage is clamped. After the circuit is started to work for a period of time, the resistance-capacitance module provides a high level for the input end of the phase inverter, and cuts off the PMOS, so that the output end of the PMOS recovers a low level to cut off the grid, and provides stable voltage for the grid, thereby preventing the channel current from being burnt out due to overlarge current.
Furthermore, the polysilicon POLY is arranged on the surface of the semiconductor body and on the opposite surface of the P + region, and is transversely connected with the N + region, the Pwell and the N epitaxy respectively on one side of the N + region to form a planar polycrystalline gate and form the LDMOS.
The polysilicon POLY is used as an IGBT Gate pole (IGBT Gate Control) and is controlled by an inverter formed by a PMOS and an NMOS, the P + substrate is connected with the anode of the delay circuit, and the N + area and the P + area are connected with the cathode of the delay circuit.
In addition, the gate structure of VDMOS can also be designed to replace the planar poly gate, and the MOS channel current path becomes vertical, that is: the polycrystalline silicon POLY is provided with a groove in the N + region, so that the polycrystalline silicon POLY is respectively connected with the N + region, the Pwell and the N epitaxy along the longitudinal direction to form a gate structure of the VDMOS. The current density of the VDMOS can be larger than that of the LDMOS, and the triggering and the turn-off are easier to control.
The upper surface of the polysilicon POLY is used as an IGBT Gate (IGBT Gate Control) and is controlled by an inverter formed by a PMOS and an NMOS, the P + substrate is connected with the anode of the delay circuit, and the N + area and the P + area are connected with the cathode of the delay circuit.
In the invention, in the delay circuit formed by the resistance-capacitance and the MOS inverter, the capacitor is an MOS capacitor or a PIP capacitor.
And when part of the electric connection can not be connected through the metal surface metal wire, the connection is carried out through a lead wire in the packaging process.
The invention has the advantages that: the quasi-insulated gate bipolar transistor structure is designed into a multi-cell structure, which is beneficial to increasing the limit current capacity; the doping concentrations of the N-type epitaxy and the P-type trap are properly designed to obtain proper turn-on voltage and as low as possible on-resistance. The invention has large current density per unit area in the on state. The SCR structure in the structure is longitudinal, the thickness, the resistivity, the depth of a trap, the depth of an injection junction and the like of an epitaxial layer are uniform, the charge distribution, the electric field lines and the like are reasonably distributed in a breakdown state, the junction area can be efficiently utilized, and the current density can be far higher than that of a transverse SCR structure.
Drawings
FIG. 1 is a schematic circuit diagram of a TVS device with a MOS-triggered SCR structure;
FIG. 2 is a schematic diagram of a TVS device structure and circuit of a MOS-triggered SCR with a surface junction lateral structure;
FIG. 3 is an equivalent circuit diagram of a portion of an insulated gate bipolar transistor device;
FIG. 4 is a schematic diagram of an FS-IGBT structure;
FIG. 5 is a schematic diagram of a quasi-IGBT structure according to the present invention;
FIG. 6 is a schematic diagram of a TVS device structure and circuit of a pseudo-IGBT structure controlled by RC delay;
FIG. 7 is a schematic diagram of an IGBT-like structure using a VDMOS surface structure;
FIG. 8 is a schematic diagram of a TVS device structure and circuit with a VDMOS surface structure for a pseudo-IGBT with RC delay control;
the reference numbers in the figures illustrate:
1-P + substrate;
2-N type epitaxy;
Pwell-P-well;
n + -N type heavy doping;
p + -heavily doped P-type;
3-lateral polysilicon POLY;
4-longitudinal POLY;
r is resistance;
c-capacitance.
Detailed Description
Example 1
An improved quasi-insulated gate bipolar transistor device is shown in a cross section view in fig. 5, a P + substrate 1, a thinned N-type epitaxy 2, a P-type well Pwell on the N-type epitaxy 2 and an N-type heavily doped N + on the surface of the P-type well Pwell form a PNPN longitudinal junction silicon controlled rectifier structure SCR, one side of the N + is provided with a P-type heavily doped P +, the other side of the N + heavily doped N + is transversely connected with an N + region, the Pwell and the N-type epitaxy 2 respectively, and a transverse polycrystalline silicon POLY3 is controlled to be 6V-40V, wherein the N-type heavily doped N + on the surface serves as a drain electrode, the N-type epitaxy 2 layer serves as a source electrode, the P-type well Pwell serves as a substrate, and the polycrystalline silicon serves as a gate electrode to form an NMOS.
The improved similar insulated gate bipolar transistor device of the embodiment is connected with a delay circuit which is composed of a resistor R, a capacitor C, a PMOS inverter and an NMOS inverter, and is the same as the delay circuit which is composed of the resistor-capacitor inverter and the MOS inverter in the figure 1.
As shown in FIG. 7, the P + substrate is connected to the anode, the P + region is connected to the cathode as the Gate of the thyristor (GTO Gate Control), the POLY-POLY is controlled by the MOS inverter as the MOS POLY-Gate, and the N + region is connected to the cathode.
The lateral polysilicon POLY described in this embodiment is connected to the N +, Pwell and N-type epitaxy on the surface of the semiconductor body and on one side of the N-type heavily doped N +, respectively, to form a planar POLY gate and an LDMOS.
In the embodiment, compared with the IGBT, the substrate type is changed, a thinner N-type epitaxy is used, the thickness of a gate oxide layer is reduced, and a control logic is formed by combining a capacitance resistor and a MOS inverter to obtain the TVS device with the similar insulated gate bipolar transistor structure controlled by the capacitance delay.
Example 2
An improved bipolar transistor device similar to the bipolar transistor device in embodiment 1 is similar to that in embodiment 1, and a cross-sectional view is shown in fig. 6, a P + substrate 1, a thinned N-type epitaxy 2, a P-type well Pwell on the N-type epitaxy 2, and an N-type heavily doped N + on the surface of the P-type well Pwell form a PNPN longitudinal junction silicon controlled rectifier structure SCR, one side of the N + has a P-type heavily doped P +, one longitudinal polysilicon POLY4 in the N-type heavily doped P +, the longitudinal polysilicon POLY4 is longitudinally connected with the N +, the P-type well Pwell and the N-type epitaxy 2, the breakdown voltage is controlled between 6V and 40V, wherein the N-type heavily doped N + on the surface serves as a drain, the N-type epitaxy 2 layer serves as a source, the P-type well Pwell serves as a substrate, and the polysilicon POLY serves as a gate to form.
The improved similar insulated gate bipolar transistor device of the embodiment is connected with a delay circuit formed by a resistance-capacitance and a MOS inverter, and the delay circuit is the same as the delay circuit of the embodiment 1.
As shown in fig. 8, P + substrate 1 is connected to the anode, P + region is connected to the cathode as the Gate of the thyristor (GTO Gate Control), vertical POLY4 is controlled by the MOS inverter as the MOS POLY Gate, and N + is connected to the cathode.
In this embodiment, the polysilicon POLY has a trench in the N + region, so that the polysilicon POLY is respectively connected to the N + region, Pwell and N epitaxy along the longitudinal direction to form a gate structure of the VDMOS.
Claims (10)
1. A TVS device is connected with a resistance-capacitance delay circuit, and is characterized in that: the PNPN longitudinal junction silicon controlled rectifier structure comprises a P substrate material, an N-type epitaxial layer, a P-type trap (Pwell) growing on the surface of the N-type epitaxial layer, an N-type heavily doped region (N + region) on the surface of the Pwell, a polycrystalline silicon (POLY) gate and a polycrystalline resistor, wherein the semiconductor body of the multi-cell structure is formed by the P substrate material, the N-type epitaxial layer, the P-type trap and the N + region on the surface; the N + region on the surface is used as a drain electrode, the N-type epitaxial layer is used as a source electrode, Pwell is used as a substrate, polysilicon is used as a grid electrode to form an N-type MOS structure, and the breakdown voltage of the similar insulated gate bipolar transistor structure is controlled to be between 6V and 40V, so that the N-type MOS structure is used for electrostatic and low-voltage surge protection.
2. The TVS device of claim 1, wherein: the resistance-capacitance delay circuit is composed of a resistance capacitor and an MOS inverter, and a longitudinal junction silicon controlled structure with breakdown voltage of 6-40V is formed by designing the size and the interval of a P substrate material, an N type epitaxial layer, a Pwell and an N + region.
3. The TVS device of claim 1 or 2, wherein: by designing the doping concentration and thickness of the N + region, the Pwell and the N-type epitaxial layer and the thickness of the polysilicon gate oxide, an N-type MOS structure with the turn-on voltage of 0.5V-2V and the on-resistance of not more than 0.2 ohm is formed.
4. The TVS device of claim 3, wherein: the P substrate material adopts a P + substrate and a thinned N-type epitaxial layer, one side of the N + region on the surface of the Pwell is provided with a P-type heavily doped region (P + region) as a thyristor Gate turn-off Control (GTO Gate Control), the other side of the N + region or the other side of the N + region is provided with a polysilicon POLY which is respectively connected with the N +, the Pwell and the N epitaxy, so that an MOS structure with the N + region as a drain electrode, the N-type epitaxial layer as a source electrode, the Pwell as a substrate and the polysilicon as a grid electrode is formed, wherein the P + substrate is connected with an anode, the P + region and the N + region are connected with a cathode, and the polysilicon POLY as an MOS polycrystalline grid is controlled by an MOS inverter.
5. The TVS device of claim 4, wherein: the polycrystalline silicon POLY is arranged on the surface of the semiconductor body and on the surface opposite to the P + region, and is transversely connected with the N + region, the Pwell and the N epitaxy respectively on one side of the N + region to form a planar polycrystalline gate.
6. The TVS device of claim 5, wherein: the polysilicon POLY is used as an IGBT Gate pole (IGBT Gate Control) and is controlled by an inverter formed by a PMOS and an NMOS, the P + substrate is connected with the anode of the delay circuit, and the N + area and the P + area are connected with the cathode of the delay circuit.
7. The TVS device of claim 4, wherein: the polycrystalline silicon POLY is provided with a groove in the N + region, so that the polycrystalline silicon POLY is respectively connected with the N + region, the Pwell and the N epitaxy along the longitudinal direction to form a gate structure of the VDMOS.
8. The TVS device of claim 7, wherein: the upper surface of the polysilicon POLY is used as an IGBT Gate (IGBT Gate Control) and is controlled by an inverter formed by a PMOS and an NMOS, the P + substrate is connected with the anode of the delay circuit, and the N + area and the P + area are connected with the cathode of the delay circuit.
9. The TVS device of claim 1 or 2, wherein: in the resistance-capacitance delay circuit, the capacitor is an MOS capacitor or a PIP capacitor.
10. The TVS device of claim 1 or 2, wherein: the TVS devices are connected through metal surface metal wires, or connected through leads in the packaging process when part of the electrical connections cannot be connected through the metal surface metal wires.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010974113.7A CN112259597A (en) | 2020-09-16 | 2020-09-16 | TVS device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010974113.7A CN112259597A (en) | 2020-09-16 | 2020-09-16 | TVS device |
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| Publication Number | Publication Date |
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| CN112259597A true CN112259597A (en) | 2021-01-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202010974113.7A Pending CN112259597A (en) | 2020-09-16 | 2020-09-16 | TVS device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116564959A (en) * | 2023-05-30 | 2023-08-08 | 上海晶岳电子有限公司 | SGT MOS process TVS device and manufacturing method thereof |
| CN116598306A (en) * | 2023-05-30 | 2023-08-15 | 上海晶岳电子有限公司 | TVS device and manufacturing method thereof |
-
2020
- 2020-09-16 CN CN202010974113.7A patent/CN112259597A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116564959A (en) * | 2023-05-30 | 2023-08-08 | 上海晶岳电子有限公司 | SGT MOS process TVS device and manufacturing method thereof |
| CN116598306A (en) * | 2023-05-30 | 2023-08-15 | 上海晶岳电子有限公司 | TVS device and manufacturing method thereof |
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