CN107768240B - Source region structure of trench transistor and preparation method thereof - Google Patents
Source region structure of trench transistor and preparation method thereof Download PDFInfo
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- CN107768240B CN107768240B CN201710901735.5A CN201710901735A CN107768240B CN 107768240 B CN107768240 B CN 107768240B CN 201710901735 A CN201710901735 A CN 201710901735A CN 107768240 B CN107768240 B CN 107768240B
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- 238000002360 preparation method Methods 0.000 title abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 229910000838 Al alloy Inorganic materials 0.000 claims description 3
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 239000007769 metal material Substances 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000009825 accumulation Methods 0.000 abstract description 2
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000004075 alteration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention relates to the technical field of semiconductors, in particular to a source region structure of a trench transistor and a preparation method thereof, wherein the source region structure comprises the following steps: the substrate comprises a body layer and an epitaxial layer formed on the upper surface of the body layer, wherein the epitaxial layer is provided with a first doping type; the drift layer is formed on the upper surface of the substrate and has a second doping type; a plurality of first grooves which are transversely spaced are formed on the upper surface of the drift layer, and source electrodes are formed on the upper parts of the drift layer on two sides of the first grooves; the oxide layer covers the side wall and the bottom of the first groove; a conductive layer; a dielectric layer; the metal layer covers the upper surface of the dielectric layer; a plurality of contact holes for connecting the drift layer and the metal layer are formed in the dielectric layer; an accumulation region can be formed on the side wall of the groove, low on-resistance can be realized, the normally-off state of the device can be kept without an additional structural layer, meanwhile, the drift layer serves as a buffer to reduce the peak electric field at the bottom of the grid electrode when the drain electrode is under high voltage, and the withstand voltage of the device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a source region structure of a trench transistor and a preparation method thereof.
Background
With the continuous research and development of a VVMOS (vertical V-groove MOSFET, abbreviated as VVMOS), a power MOSFET is rapidly developed, which has become a mainstream power semiconductor switching device in medium and small power application fields. Power MOSFETs have been developed in the direction of structural optimization and structural innovation, pushing device performance towards higher voltage application ranges, lower on-resistance, higher frequency and higher reliability.
Power MOSFETs are three-terminal semiconductor switches that are commonly used for power supply and load control of circuits. Under the condition of constant packaging power, the smaller the on resistance of the device is, the lower the self power consumption is, and the larger the current can pass through. In a given package, to achieve a large switching current, the only feasible way to improve the thermal characteristics of the package is to reduce the device on-resistance. However, in the low-voltage and low-power MOSFET field, reducing the on-resistance of the device may affect the normally-off state of the MOSFET device, and further reducing the on-resistance of the device is limited.
Disclosure of Invention
In view of the above problem, the present invention provides a source region structure of a trench transistor, including:
the substrate comprises a body layer and an epitaxial layer formed on the upper surface of the body layer, wherein the epitaxial layer is provided with a first doping type;
the drift layer is formed on the upper surface of the substrate and has a second doping type;
a plurality of first grooves which are transversely spaced are formed on the upper surface of the drift layer, and source electrodes are formed on the upper parts of the drift layer on two sides of the first grooves;
the oxide layer covers the side wall and the bottom of the first groove;
a conductive layer filling the first trench and having the first doping type;
the dielectric layer covers the upper surface of the source electrode and the upper surface of the conducting layer;
the metal layer covers the upper surface of the dielectric layer;
and a plurality of contact holes for connecting the epitaxial layer and the metal layer are formed in the dielectric layer.
In the above source region structure, the first doping type is N-type, and the second doping type is P-type.
In the source region structure, the thickness of the drift layer is 900-1100A.
In the above source region structure, the first trench extends vertically.
In the above source region structure, a side cross section of the first trench is trapezoidal.
In the above source region structure, the metal layer is an aluminum alloy or a copper alloy.
A device structure of a trench transistor, comprising the source region structure as described above, further comprising:
a termination region structure disposed around the source region structure.
In the device structure, the termination region structure includes a trench-type isolation ring, and the isolation ring is used to isolate the termination region structure from the source region structure.
A preparation method of a source region structure of a trench transistor is applied to the source region structure of the trench transistor, and comprises the following steps:
step S1, providing a substrate, wherein the substrate includes a body layer and an epitaxial layer formed on the upper surface of the body layer, and the epitaxial layer has a first doping type;
step S2, forming a drift layer on the upper surface of the substrate, wherein the drift layer has a second doping type;
step S3, etching the upper surface of the drift layer to form a plurality of first grooves which are transversely spaced;
step S4, preparing an oxide layer to cover the side wall and the bottom of the first trench;
step S5, filling the first trench covered with the oxide layer with a conductive material to form a conductive layer, where the conductive layer has the first doping type;
step S6, forming a source layer on the drift layer by ion implantation;
step S7, depositing a dielectric layer on the upper surfaces of the source layer and the conductive layer;
step S8, etching and penetrating the dielectric layer and the source layer into the drift layer to form a plurality of second trenches and a source on both sides of each second trench;
step S9, filling each second groove with a metal material to form a plurality of contact holes;
step S10, a metal layer is formed on the dielectric layer and the upper surface of the contact hole.
Has the advantages that: according to the source region structure of the trench transistor and the preparation method thereof, the prepared source region structure forms an accumulation region on the side wall of the trench, low on-resistance can be realized, the normally-off state of the device can be kept without an additional structural layer, and meanwhile, the drift layer serves as a buffer to reduce the peak electric field at the bottom of the grid electrode when the drain electrode is in high voltage, so that the withstand voltage of the device is improved.
Drawings
FIG. 1 is a schematic structural diagram illustrating a source region structure of a trench transistor according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a method for fabricating a source region structure of a trench transistor according to an embodiment of the present invention;
fig. 3 to 7 are schematic views of structures formed in each step of the method for manufacturing the source region structure of the trench transistor according to an embodiment of the present invention.
Detailed Description
The invention is further illustrated with reference to the following figures and examples.
Example one
In a preferred embodiment, as shown in fig. 1, a source region structure of a trench transistor is provided, which may include:
a substrate 10 including a body layer 11 and an epitaxial layer 12 formed on an upper surface of the body layer 11, wherein the epitaxial layer 12 has a first doping type;
a drift layer 20 formed on the upper surface of the substrate 10, wherein the drift layer 20 has a second doping type;
a plurality of first trenches TR1 are formed on the upper surface of the drift layer 20 at intervals in the lateral direction, and source electrodes 51 are formed on the upper portion of the drift layer 20 at both sides of the first trenches TR 1;
an oxide layer 30 covering the sidewalls and bottom of the first trench TR 1;
a conductive layer 40 filling the first trench TR1 and having a first doping type;
a dielectric layer 60 covering the upper surface of the source electrode 51 and the upper surface of the conductive layer 40;
a metal layer 70 covering the upper surface of the dielectric layer 60;
a plurality of contact holes CT connecting the epitaxial layer 20 and the metal layer 70 are formed in the dielectric layer.
In the above technical solution, the material forming the substrate 10 may be silicon; the doping type of the body layer 11 as the drain electrode can be the same as that of the epitaxial layer 12, but the body layer 11 can be heavily doped, and the epitaxial layer 12 and the drift layer 20 can be lightly doped, so that the electric field intensity of the epitaxial layer 12 tends to be uniformly distributed, and the electric field peak value is avoided; the source 51 may have a first doping type with a heavily doped concentration; the conductive medium in the contact hole CT may be a metal, such as tungsten metal, and the conductive medium may not completely fill the trench forming the contact hole CT in an actual process, so the trench forming the contact hole CT generally needs to extend into the drift layer 20 to ensure the connection between the source 51 and the metal layer 70, but an electrical isolation structure exists between the conductive medium in the contact hole CT and the drift layer 20; the conductive layer 40 may have a heavily doped concentration to be in a depleted state in a region around the first trench TR 1; the first trench TR1 generally needs to extend down into the epitaxial layer 12.
In a preferred embodiment, the first doping type is N-type and the second doping type is P-type.
In a preferred embodiment, the thickness of the drift layer 20 may be 900-1100A (angstroms), such as 920A, 950A, 1000A, 1050A or 1080A.
In a preferred embodiment, the first trench TR1 extends vertically, but this is preferred and should not be construed as limiting the invention.
In a preferred embodiment, the first trench TR1 has a trapezoidal side cross-section.
In a preferred embodiment, the metal layer 70 is an aluminum alloy or a copper alloy.
Example two
In a preferred embodiment, a device structure of a trench transistor is further provided, in which the above source region structure may be included, and the method may further include:
and a termination region structure disposed around the source region structure.
In the foregoing embodiment, preferably, the termination region structure includes a trench-type isolation ring, and the isolation ring is used to isolate the termination region structure from the source region structure.
EXAMPLE III
In a preferred embodiment, as shown in fig. 2 to 7, a method for manufacturing a source region structure of a trench transistor is further provided, wherein the method may include:
step S1, providing a substrate 10, in which the substrate 10 includes a body layer 11 and an epitaxial layer 12 formed on an upper surface of the body layer 11, and the epitaxial layer 12 has a first doping type;
step S2, forming a drift layer 20 on the upper surface of the substrate 10, wherein the drift layer 20 has a second doping type;
step S3, etching the upper surface of the drift layer 20 to form a plurality of laterally spaced first trenches TR 1;
step S4, preparing an oxide layer 30 covering the sidewalls and the bottom of the first trench TR 1;
step S5, filling the first trench TR1 covered with the oxide layer 30 with a conductive material to form a conductive layer 40, wherein the conductive layer 40 has a first doping type;
step S6, forming a source layer 50 on the drift layer 20 by ion implantation;
step S7, depositing a dielectric layer 60 on the upper surfaces of the source layer 50 and the conductive layer 40;
step S8, forming a plurality of second trenches TR2 and source electrodes 51 at two sides of each second trench TR2 by etching and penetrating the dielectric layer 60 and the source electrode layer 50 into the drift layer 20;
step S9, filling each second trench TR2 with a metal material to form a plurality of contact holes CT;
in step S10, a metal layer 70 is formed on the upper surface of the dielectric layer 60 and the contact hole CT.
In the above technical solution, the body layer 11 may be formed by an N-type doping process with a heavily doped concentration; the epitaxial layer 12 may be formed using an N-type doping process with a light doping concentration; the drift layer 20 may be formed using a P-type doping process with a light doping concentration; the conductive layer 40 may be formed using polysilicon, and the conductive layer 40 may have a first doping type with a heavily doped concentration; the first doping type may be N-type and the second doping type may correspondingly be P-type.
While the specification concludes with claims defining exemplary embodiments of particular structures for practicing the invention, it is believed that other modifications will be made in the spirit of the invention. While the above invention sets forth presently preferred embodiments, these are not intended as limitations.
Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above description. Therefore, the appended claims should be construed to cover all such variations and modifications as fall within the true spirit and scope of the invention. Any and all equivalent ranges and contents within the scope of the claims should be considered to be within the intent and scope of the present invention.
Claims (9)
1. A source region structure of a trench transistor, comprising:
the substrate comprises a body layer and an epitaxial layer formed on the upper surface of the body layer, wherein the epitaxial layer is provided with a first doping type;
the drift layer is formed on the upper surface of the substrate and has a second doping type;
a plurality of first grooves which are transversely spaced are formed on the upper surface of the drift layer, and source electrodes are formed on the upper parts of the drift layer on two sides of the first grooves;
the oxide layer covers the side wall and the bottom of the first groove;
a conductive layer filling the first trench and having the first doping type, the first trench extending down into the epitaxial layer;
the dielectric layer covers the upper surface of the source electrode and the upper surface of the conducting layer;
the metal layer covers the upper surface of the dielectric layer;
a plurality of contact holes for connecting the epitaxial layer and the metal layer are formed in the dielectric layer;
the groove of the contact hole extends to the drift layer, and an electric isolation structure exists between the conductive medium in the contact hole and the drift layer.
2. The source region structure of claim 1, wherein the first doping type is N-type and the second doping type is P-type.
3. The source region structure of claim 1, wherein the drift layer has a thickness of 900 to 1100 Å.
4. The source region structure of claim 1, wherein the first trench extends vertically.
5. The source structure of claim 1 wherein said first trench is trapezoidal in side cross-section.
6. The source region structure of claim 1, wherein the metal layer is an aluminum alloy or a copper alloy.
7. A device structure of a trench transistor, comprising the source region structure of any one of claims 1 to 6, further comprising:
a termination region structure disposed around the source region structure.
8. The device structure of claim 7, wherein the termination region structure comprises a trenched isolation ring for isolating the termination region structure from the source region structure.
9. A method for manufacturing a source region structure of a trench transistor, which is applied to the source region structure of the trench transistor in claim 1, comprising:
step S1, providing a substrate, wherein the substrate includes a body layer and an epitaxial layer formed on the upper surface of the body layer, and the epitaxial layer has a first doping type;
step S2, forming a drift layer on the upper surface of the substrate, wherein the drift layer has a second doping type;
step S3, etching the upper surface of the drift layer to form a plurality of first grooves which are transversely spaced;
step S4, preparing an oxide layer to cover the side wall and the bottom of the first trench;
step S5, filling the first trench covered with the oxide layer with a conductive material to form a conductive layer, where the conductive layer has the first doping type;
step S6, forming a source layer on the drift layer by ion implantation;
step S7, depositing a dielectric layer on the upper surfaces of the source layer and the conductive layer;
step S8, etching and penetrating the dielectric layer and the source layer into the drift layer to form a plurality of second trenches and a source on both sides of each second trench;
step S9, filling each second groove with a metal material to form a plurality of contact holes;
step S10, a metal layer is formed on the dielectric layer and the upper surface of the contact hole.
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| US20170125531A9 (en) * | 2009-08-31 | 2017-05-04 | Yeeheng Lee | Thicker bottom oxide for reduced miller capacitance in trench metal oxide semiconductor field effect transistor (mosfet) |
| CN102103997B (en) * | 2009-12-18 | 2012-10-03 | 上海华虹Nec电子有限公司 | Structure of groove type power MOS (Metal Oxide Semiconductor) device and preparation method thereof |
| CN106684126A (en) * | 2016-12-12 | 2017-05-17 | 中航（重庆）微电子有限公司 | Trench type transistor device structure and making method |
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