CN109360807A - The integrated preparation method for exhausting reinforced pipe - Google Patents
The integrated preparation method for exhausting reinforced pipe Download PDFInfo
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- CN109360807A CN109360807A CN201811076167.0A CN201811076167A CN109360807A CN 109360807 A CN109360807 A CN 109360807A CN 201811076167 A CN201811076167 A CN 201811076167A CN 109360807 A CN109360807 A CN 109360807A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 238000002347 injection Methods 0.000 claims abstract description 36
- 239000007924 injection Substances 0.000 claims abstract description 36
- 238000001259 photo etching Methods 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 230000007797 corrosion Effects 0.000 claims abstract description 14
- 238000005260 corrosion Methods 0.000 claims abstract description 14
- 238000002161 passivation Methods 0.000 claims abstract description 11
- 230000003647 oxidation Effects 0.000 claims abstract description 8
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 8
- 238000004544 sputter deposition Methods 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 230000008021 deposition Effects 0.000 claims abstract description 7
- 230000008020 evaporation Effects 0.000 claims abstract description 6
- 238000001704 evaporation Methods 0.000 claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 6
- 239000013078 crystal Substances 0.000 claims abstract description 4
- 238000009792 diffusion process Methods 0.000 claims abstract description 3
- 238000002513 implantation Methods 0.000 claims description 28
- 230000002708 enhancing effect Effects 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 9
- 239000004411 aluminium Substances 0.000 claims description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- QQMBHAVGDGCSGY-UHFFFAOYSA-N [Ti].[Ni].[Ag] Chemical compound [Ti].[Ni].[Ag] QQMBHAVGDGCSGY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 230000004927 fusion Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 230000005669 field effect Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 230000001413 cellular effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 208000033999 Device damage Diseases 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8236—Combination of enhancement and depletion transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0883—Combination of depletion and enhancement field effect transistors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of integrated preparation method for exhausting reinforced pipe, include the following steps, select N-type crystal orientation substrate, isolated area is set on substrate, first enhancement region and the first depletion region, to the first enhancement region, first depletion region carries out pressure-resistant ring region photoetching, pressure-resistant ring region is injected, it promotes and aoxidizes, the p-type formed in isolated area adulterates diffusion, to the first enhancement region, when first depletion region carries out gate oxidation, deposit polycrystalline silicon: polycrystalline injection is carried out to the grid of the two again, then photoetching is carried out, corrosion, NSD injection is carried out again, multiple PN junctions are formed on polycrystalline simultaneously to form the source region of depletion region enhancement region, finally carry out sputtering photoetching, passivation deposition and back side evaporation.The integrated production method for exhausting reinforced pipe makes in the manufacturing process of reinforced pipe while integrated fusion exhausts pipe, by being integrated with anti-ESD function element, can effectively enhance the anti-ESD ability of device.
Description
Technical field
The present invention relates to the production preparation sides that electronic component design field more particularly to a kind of integrated enhancing exhaust pipe
Method.
Background technique
Field effect transistor (Field Effect Transistor abridges (FET)) abbreviation field-effect tube.There are mainly two types of
Type (junction FET-JFET) and Metal-Oxide Semiconductor field-effect tube (metal-oxide
Semiconductor FET, abbreviation MOS-FET).Conduction, also referred to as unipolar transistor are participated in by majority carrier.It belongs to
Voltage controlled semiconductor device.With input resistance high (107~1015 Ω), noise is small, low in energy consumption, dynamic range is big, easily
In integrating, there is no the advantages that secondary-breakdown phenomenon, safety operation area field width, bipolar junction transistor and power transistor are become
Powerful competitor.It is made into design that is existing enhanced and having depletion mode transistor in a substrate, then can be referred to as enhancing and exhaust
Pipe.Existing high voltage planar enhancing exhausts the anti-ESD of pipe product (Electro-Static discharge, Electro-static Driven Comb) ability
It is weak, it is producing and is easily causing device damage using link, main cause is that thin gate oxide is easily punctured by ESD, to influence
Product reliability and service life.
Summary of the invention
In view of the deficiency of above-mentioned current technology, it is desirable to provide a kind of preparation method of the novel component for exhausting enhancing,
Solve the problems, such as existing product can not integrate simultaneously exhaust pipe, reinforced pipe function and be easy breakdown.
To achieve the above object, the utility model provides a kind of integrated preparation method for exhausting reinforced pipe, including as follows
Step,
N-type crystal orientation substrate is selected, isolated area, the first enhancement region and the first depletion region are set on substrate, is enhanced first
Area, the first depletion region carry out pressure-resistant ring region photoetching, and pressure-resistant ring region is injected, promoted and aoxidized, and form the p-type in isolated area
Doping diffusion,
When carrying out gate oxidation to the first enhancement region, the first depletion region, deposit polycrystalline silicon: the grid of the two is carried out again
Then polycrystalline injection carries out photoetching, corrosion, then carries out NSD injection, while forming multiple PN junctions on polycrystalline and exhausting to be formed
The source region of area enhancement region finally carries out sputtering photoetching, passivation deposition and back side evaporation.
Further, the substrate is the epitaxial wafer substrate of Sb doped.
Specifically, the polycrystalline implantation dosage of the polycrystalline injection is 4E13~6E13, Implantation Energy 20Kev-40Kev.
Preferably, the implantation dosage of the NSD injection is 5E15~6E15, Implantation Energy 120Kev-160Kev.
Optionally, the trap temperature that pushes away of the NSD injection is 850 degrees Celsius to 1050 degrees Celsius, and pushing away the trap time is 20 minutes
To 30 minutes.
It further, further include step before the gate oxidation,
JFET injection and JFET annealing；JFET injection is carried out in active area, implantation dosage: 1.8E12~2.2E12, injection
Energy: 100Kev-140Kev injects element phosphor, then carries out JFET annealing, annealing temperature: 1050 DEG C~1250 DEG C, when annealing
Between: 120-150 minutes；
P-well exposure, injection push away trap；P-well photoetching is carried out, the P trap that will exhaust the primitive unit cell area of pipe and reinforced pipe is opened, then
Carry out p-well injection.Wherein, implantation dosage: 4E13~5E13, Implantation Energy: 100Kev-140Kev injects element: boron.Then
Remove photoresist, carries out p-well and push away trap, push away trap temperature: being set as 1050 DEG C~1250 DEG C, the time is set as 120-180 minutes；
VTH photoetching, injection；VTH is injected on the p-well surface of the first depletion region, implantation dosage is 4E12~6E12, injection
Energy is 100Kev-120Kev, injects element arsenic.
Specifically, the sputtering is lithographically sputtered aluminum, deposits the aluminium of 4um on substrate, then photoetching corrosion aluminium, is formed and is increased
Grid region and the source region of pipe are exhausted by force.
Preferably, the passivation deposition includes deposit passivation layer silicon nitride (Si3N4)Then photoetching
Corrosion forms open region.
Further, the back side evaporation includes step, and the disk back side is thinned and evaporates to 230-300 microns, then overleaf
Titanium-nickel-silver.
It is different from the prior art, the above-mentioned integrated production method for exhausting reinforced pipe makes same in the manufacturing process of reinforced pipe
When integrated fusion exhaust pipe, by being integrated with anti-ESD function element, can effectively enhance the anti-ESD ability of device, while the technique mistake
Journey and conventional MOS process compatible.
Detailed description of the invention
Fig. 1 is to exhaust reinforced pipe schematic equivalent circuit described in specific embodiment；
Fig. 2 is preparing substrate schematic diagram described in specific embodiment；
Fig. 3 is active area photoetching schematic diagram described in specific embodiment；
Fig. 4 is that p-well described in specific embodiment promotes schematic diagram；
Fig. 5 is that polycrystalline described in specific embodiment injects schematic diagram；
Fig. 6 is NSD photoetching schematic diagram described in specific embodiment；
Fig. 7 is splash-proofing sputtering metal schematic diagram described in specific embodiment；
Fig. 8 is that schematic diagram is evaporated at the back side described in specific embodiment.
Specific embodiment
Technology contents, construction feature, the objects and the effects for detailed description technical solution, below in conjunction with specific reality
It applies example and attached drawing is cooperated to be explained in detail.
Following technical proposals of the invention are integrated with anti-ESD function element, can have on the basis of tradition enhancing exhausts pipe
The effect enhancing anti-ESD ability of device, while the technical process and tradition VMOS (metal-oxide semiconductor (MOS)) process compatible.
The depletion type VMOS pipe of the device and enhanced VDMOS pipe common drain, while between the end Gate and the end Source
Multiple PN junctions are integrated, ESD impact electric current of releasing is played the role of, equivalent circuit is as shown in Figure 1.
Referring to Fig. 2, in the embodiment shown in Figure 2, our technical solution includes the following steps:
Step 1: preparing extension.
As shown in the figure, the substrate of epitaxial wafer uses N-type (100) crystal orientation, and antimony (Sb) doping, resistivity is less than 0.02 Ω
cm.The epitaxial thickness of substrate is selected as 55-60um, and the selection of electrical resistivity of epitaxy range exists: 12.5-14.5 Ω cm is set by above-mentioned
The device pressure resistance of meter can achieve 600V-700V. and see Fig. 1.
Step 2: once oxidation.
Ring (pressure-resistant ring region) photoetching, the terminal protection ring region of pressure-resistant ring region finger device part are carried out to epitaxial wafer, including protected
Retaining ring, the protection parts such as czermak space and field plate.It will be seen that the substrate of epitaxial wafer has been divided into enhancement region, isolation from figure
Area, depletion region；Enhancement region, depletion region are staggered in the plane and are isolated by being arranged between isolated area, and into one
Step ground, enhancement region are divided into the resistance to pressure area of reinforced pipe and cellular region, the area reinforced pipe Gate Pad again, and the area Gate PAD is also known as gate regions.
Depletion region, which is also further divided into exhaust pipe cellular region and exhaust tube grid, pads the area Gate Pad.This mode being staggered can be with
It is designed and is obtained by different photolithography plates, be finally only required to accomplish, carried out in the position for being preset as the resistance to pressure area of reinforced pipe
Ring injection, Ring is promoted and oxidation, specifically includes step, grows in extension on piece(1 angstrom is equal to 0.1 and receives
Rice) oxide layer, for Ring injection masking layer.Ring photoetching is carried out, the needs for exhausting pipe and reinforced pipe are high voltage bearing
Terminal is opened.Then ring injection is carried out, wherein the energy injected: 110Kev~130Kev, implantation dosage: 1.6E13~
2E13 injects element boron.Following Ring is promoted, and environment temperature is promoted to be selected as 1050 DEG C~1250 DEG C, about 500 points of the time
Clock, and oxide layer is grown simultaneouslyBy above-mentioned once oxidation, the purpose of step is the pressure-resistant ring region and consumption to reinforced pipe
Although isolated area between plays shielding action, protects to area of isolation, and the foreign ion of subsequent process steps is stopped to be infused
Enter to the region.
Step 3: active area photoetching, corrosion.
In specific implement, as shown in Figure 3, it would be desirable to active area photoetching is carried out, it is then that the active area of tube core is rotten
Eating awayOxide layer.Main purpose is then after opening active area, as the subsequent injection region JFET
Domain.
Step 4: JFET injection and JFET annealing.
JFET injection is carried out in active area, implantation dosage: 1.8E12~2.2E12, Implantation Energy: 100Kev-140Kev,
Inject element: phosphorus (P).Then JFET anneals, temperature: 1150 DEG C, the time: 120-150 minutes.The step can reduce device
Conducting resistance.
Step 5, p-well exposure, injection push away trap.
Here 4 be please see Figure, we carry out p-well photoetching first in the embodiment shown in fig. 4, will exhaust pipe and reinforced pipe
The p-well in primitive unit cell area is opened, and p-well injection is then carried out.Wherein, implantation dosage: 4E13~5E13, Implantation Energy: 100Kev-
140Kev injects element: boron.Then remove photoresist, carry out p-well and push away trap, push away trap temperature: 1150 DEG C, the time can be set to
120-180 minutes.This step is primarily used to form P well area, convenient for the progress of subsequent step.
Step 6: VTH (Threshold Voltage, threshold voltage) photoetching, injection.
The step is infused in the p-well surface for exhausting pipe, is to be formed to exhaust pipe by the purpose of this step.Wherein implantation dosage:
4E12~6E12, Implantation Energy: 100Kev-120Kev injects element: arsenic (As).
Step 7: grid oxygen, deposit polycrystalline silicon.
Gate oxide thickness degreeDeposit polycrystalline silicon thickness
Step 8: polycrystalline injects, and photoetching, corrosion.
Polycrystalline implantation dosage: 4E13~6E13, Implantation Energy: 20Kev-40Kev injects element: boron.Then photoetching, it is rotten
Erosion.Here 5 be please see Figure, when executing the step, what we selected is to carry out polycrystalline injection, rather than polycrystalline is grown, polycrystalline
Injection enables to go polycrystalline depth enough in injection, can form p-type polysilicon deep enough in grid, facilitate subsequent PN
The formation of knot provides basis for the production of PN junction.
Step 9: NSD (N+Source/Drain, high concentration source/drain) photoetching, NSD injection, NSD are promoted.
It by NSD lithography step, is capable of forming enhancing and exhausts the source region of pipe, while forming multiple PN junctions on polycrystalline.NSD
Implantation dosage: 5E15~6E15, Implantation Energy: 120Kev-160Kev injects element: phosphorus.NSD pushes away trap temperature: 950 DEG C, when
Between: 25 minutes.In embodiment as shown in FIG. 6, it is seen that, it is designed by the step, not only forms the source that enhancing exhausts pipe
Area forms N-type poly-region also on polycrystalline and aforementioned p-type polycrystalline forms multiple concatenated PN junction structures, in ESD impact,
Leakage current protects device.
Step 10: generating medium, sputtering, passivation layer deposition, back side evaporation.
Generating medium includes the photoetching of step hole, pitting corrosion.Deposition medium BPSG (boron-phosphorosilicate glass) Then it opens
Hole forms hole contact.
Sputtering selection can be with aluminium (Al), also progress Al photoetching, corrosion.4um or so is deposited in the particular embodiment
Aluminium, then photoetching corrosion aluminium forms grid region and source region that enhancing exhausts pipe, and final result is as shown in Figure 7.
Passivation layer deposition, passivation layer photoetching, corrosion specifically include, deposit passivation layer silicon nitride (Si3N4)Then photoetching and corrosion expose the aluminium layer of grid and source electrode, form open region.
Back side evaporation step includes, in the backsize Ti-Ni-Ag (titanium-nickel-silver) of material: the disk back side is thinned and arrives
230-300 microns, then Ti-Ni-Ag is overleaf evaporated, final effect is as shown in Figure 8.
It should be noted that being not intended to limit although the various embodiments described above have been described herein
Scope of patent protection of the invention.Therefore, it based on innovative idea of the invention, change that embodiment described herein is carried out and is repaired
Change, or using equivalent structure or equivalent flow shift made by description of the invention and accompanying drawing content, it directly or indirectly will be with
Upper technical solution is used in other related technical areas, is included within scope of patent protection of the invention.
Claims (9)
1. a kind of integrated preparation method for exhausting reinforced pipe, which is characterized in that include the following steps,
N-type crystal orientation substrate is selected, isolated area, the first enhancement region and the first depletion region are set on substrate, to the first enhancement region, the
One depletion region carries out pressure-resistant ring region photoetching, and pressure-resistant ring region is injected, promoted and aoxidized, and forms the p-type doping in isolated area
Diffusion,
When carrying out gate oxidation to the first enhancement region, the first depletion region, polycrystalline deposit polycrystalline silicon: is carried out to the grid of the two again
Then injection carries out photoetching, corrosion, then carries out NSD injection, while forming multiple PN junctions on polycrystalline to form depletion region increasing
The source region in strong area finally carries out sputtering photoetching, passivation deposition and back side evaporation.
2. the integrated preparation method for exhausting reinforced pipe according to claim 1, which is characterized in that the substrate is Sb doped
Epitaxial wafer substrate.
3. the integrated preparation method for exhausting reinforced pipe according to claim 1, which is characterized in that the polycrystalline injects more
Brilliant implantation dosage is 4E13~6E13, Implantation Energy 20Kev-40Kev.
4. the integrated preparation method for exhausting reinforced pipe according to claim 1, which is characterized in that the note of the NSD injection
Entering dosage is 5E15~6E15, Implantation Energy 120Kev-160Kev.
5. the integrated preparation method for exhausting reinforced pipe according to claim 1, which is characterized in that the NSD injection pushes away
Trap temperature is 850 degrees Celsius to 1050 degrees Celsius, and pushing away the trap time is 20 minutes to 30 minutes.
6. the integrated preparation method for exhausting reinforced pipe according to claim 1, which is characterized in that before the gate oxidation also
Including step,
JFET injection and JFET annealing；JFET injection is carried out in active area, implantation dosage: 1.8E12~2.2E12, Implantation Energy:
100Kev-140Kev injects element phosphor, then carries out JFET annealing, annealing temperature: 1050 DEG C~1250 DEG C, annealing time:
120-150 minutes；
P-well exposure, injection push away trap；P-well photoetching is carried out, the p-well that will exhaust the primitive unit cell area of pipe and reinforced pipe is opened, and P is then carried out
Trap injection.Wherein, implantation dosage: 4E13~5E13, Implantation Energy: 100Kev-140Kev injects element: boron.Then remove light
Photoresist carries out p-well and pushes away trap, pushes away trap temperature: being set as 1050 DEG C~1250 DEG C, the time is set as 120-180 minutes；
VTH photoetching, injection；VTH is injected on the p-well surface of the first depletion region, implantation dosage is 4E12~6E12, and Implantation Energy is
100Kev-120Kev injects element arsenic.
7. the integrated preparation method for exhausting reinforced pipe according to claim 1, which is characterized in that the sputtering, which is lithographically, splashes
Aluminium is penetrated, deposits the aluminium of 4um on substrate, then photoetching corrosion aluminium, forms grid region and source region that enhancing exhausts pipe.
8. the integrated preparation method for exhausting reinforced pipe according to claim 1, which is characterized in that the passivation, which deposits, includes
Deposit passivation layer silicon nitrideThen photoetching corrosion forms open region.
9. the integrated preparation method for exhausting reinforced pipe according to claim 1, which is characterized in that the back side, which is evaporated, includes
Step is thinned the disk back side to 230-300 microns, then overleaf evaporates titanium-nickel-silver.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113838756A (en) * | 2021-09-24 | 2021-12-24 | 南瑞联研半导体有限责任公司 | Device manufacturing method for improving micro-deformation of Trench-IGBT wafer |
| CN114823881A (en) * | 2021-03-25 | 2022-07-29 | 台湾积体电路制造股份有限公司 | Electronic device and method of manufacturing the same |
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| CN114823881A (en) * | 2021-03-25 | 2022-07-29 | 台湾积体电路制造股份有限公司 | Electronic device and method of manufacturing the same |
| CN113838756A (en) * | 2021-09-24 | 2021-12-24 | 南瑞联研半导体有限责任公司 | Device manufacturing method for improving micro-deformation of Trench-IGBT wafer |
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Application publication date: 20190219 |