CN105633129A - Thyristor chip with seven-layer p-n junction isolation structure and preparation method of thyristor chip - Google Patents
Thyristor chip with seven-layer p-n junction isolation structure and preparation method of thyristor chip Download PDFInfo
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- CN105633129A CN105633129A CN201610142598.7A CN201610142598A CN105633129A CN 105633129 A CN105633129 A CN 105633129A CN 201610142598 A CN201610142598 A CN 201610142598A CN 105633129 A CN105633129 A CN 105633129A
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- 238000002955 isolation Methods 0.000 title claims abstract description 52
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 239000012535 impurity Substances 0.000 claims abstract description 66
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 43
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 43
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910052796 boron Inorganic materials 0.000 claims abstract description 39
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 39
- 239000010703 silicon Substances 0.000 claims abstract description 39
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 38
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 19
- 238000009792 diffusion process Methods 0.000 claims abstract description 16
- 230000003647 oxidation Effects 0.000 claims abstract description 10
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 10
- 238000002161 passivation Methods 0.000 claims abstract description 9
- 239000004411 aluminium Substances 0.000 claims description 36
- 238000001259 photo etching Methods 0.000 claims description 20
- 238000005260 corrosion Methods 0.000 claims description 16
- 230000007797 corrosion Effects 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 10
- 238000004140 cleaning Methods 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 7
- 238000012360 testing method Methods 0.000 claims description 7
- 230000009977 dual effect Effects 0.000 claims description 6
- 238000001459 lithography Methods 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 5
- 238000005488 sandblasting Methods 0.000 claims description 5
- 239000000956 alloy Substances 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000005265 energy consumption Methods 0.000 abstract description 4
- FGUJWQZQKHUJMW-UHFFFAOYSA-N [AlH3].[B] Chemical compound [AlH3].[B] FGUJWQZQKHUJMW-UHFFFAOYSA-N 0.000 abstract 2
- VRAIHTAYLFXSJJ-UHFFFAOYSA-N alumane Chemical compound [AlH3].[AlH3] VRAIHTAYLFXSJJ-UHFFFAOYSA-N 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 8
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 239000006185 dispersion Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229960000583 acetic acid Drugs 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- 239000012362 glacial acetic acid Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 101001050294 Homo sapiens Sperm-egg fusion protein Juno Proteins 0.000 description 1
- 241001062009 Indigofera Species 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 102100023119 Sperm-egg fusion protein Juno Human genes 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009849 deactivation Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 238000004506 ultrasonic cleaning Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/747—Bidirectional devices, e.g. triacs
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Weting (AREA)
Abstract
The invention discloses a thyristor chip with a seven-layer p-n junction isolation structure and a preparation method of the thyristor chip. The thyristor chip comprises an anode region P1, an N-type long base region, a short base region P2, an N<+>-type cathode region, a front oxidation film, a front gate metal electrode, a front cathode metal electrode, a back anode metal electrode, an annular passivation groove and an isolation ring of the seven-layer p-n junction isolation structure, wherein the isolation ring of the seven-layer p-n junction isolation structure comprises a boron impurity region, a boron-aluminum mixed impurity region, an aluminum impurity region, an aluminum-aluminum overlapping impurity region, an aluminum impurity region, the boron-aluminum mixed impurity region and the boron impurity region from top to bottom; and the isolation ring of the seven-layer p-n junction isolation structure is arranged between the front oxidation film and the back anode metal electrode along the vertical direction and surrounds the peripheries of the anode region P1, the N-type long base region and the short base region P2. The thyristor chip is short in diffusion time, low in production energy consumption, high in efficiency, high in silicon wafer integrity rate, little in transverse diffusion of the isolation region surface and small in isolation region width, and saves the area of the silicon wafer.
Description
Technical field
The present invention relates to a kind of with seven layers of controlled silicon chip to logical isolation structure, particularly relate to a kind of seven layers manufactured for controlled silicon chip to logical isolation structure, the preparation method realizing this silicon controlled rectifier device chip is provided simultaneously.
Background technology
Logical isolation structure is widely used in controlled silicon chip, at present existing logical isolation structure is mainly contained boron diffusion break-through isolation structure and laser beam perforation vacuum expand constructed of aluminium, such as: background technology 1: boron diffusion break-through isolation technology, isolated area implementation method: the dual surface lithography isolation two-sided boron of window gives deposition high temperature knot, advantage: production stage is few, shortcoming: diffusion time length, production energy consumption is big, efficiency is low, the transverse dispersion on isolated area surface is big, cause isolated area width big, waste silicon area; Background technology 2: laser beam perforation is vacuum expansion aluminum technology then, isolated area implementation method: laser boring vacuum stopped pipe expands aluminium high temperature knot, advantage: diffusion time is short, synchronously form isolated area, P1, P2 district, shortcoming: laser beam perforation efficiency is low, owing to being covered with thickly dotted reach through hole on silicon chip, increasing the difficulty of successive process, silicon chip percentage of damage in follow-up processing procedure is big.
Summary of the invention
It is an object of the invention to provide a kind of with seven layers of controlled silicon chip to logical isolation structure and its preparation method.
The technical solution used in the present invention is:
With seven layers of controlled silicon chip to logical isolation structure and an its preparation method, comprise positive column P1, N-type growing base area, Duan Ji district P2, N-+The oxide film in type cathodic area and front, the gate metal electrode in front, the cathodic metal electrode in front, the anode metal electrodes at the back side, annular passivation groove and seven layers of isolation ring to logical isolation structure, the isolation ring of logical isolation structure is by boron impurity district from top to bottom by described seven floor, Peng Lv poly-doped impurity district, aluminium impurity district, aluminium-Lv Jiaodie impurity district, aluminium impurity district, Peng Lv poly-doped impurity district, boron impurity district is formed, described seven layers of isolation ring to logical isolation structure are vertically located between the oxide film in front and the anode metal electrodes at the back side and are surrounded on positive column P1, N-type growing base area, Duan Ji district P2 surrounding.
Described boron impurity district thickness is 20-30um, and described Peng Lv poly-doped impurity district thickness is 25-30um, and described aluminium impurity district thickness is 45-55um, and described aluminium-Lv Jiaodie impurity district thickness is 30-40um.
A kind of comprise the following steps with seven layers of preparation method to the controlled silicon chip of logical isolation structure: silicon single crystal flake, chemical corrosion or polishing, silicon chip cleans, oxidation, dual surface lithography is to logical isolation window, two-sided boron gives deposition, two-sided ion implantation aluminium, subtract thin oxide film, high temperature knot, photoetching front Duan Ji district window and back anode district window, synchronously carry out Duan Ji district, front and the boron diffusion of back anode district, cathodic area, photoetching front window, the phosphorous diffusion of cathodic area, front, photoetching passivation trench openings, table top corrosion and cleaning, glassivation, photoetching front fairlead, aluminium film is steamed in front, photoetching front side aluminum electrode, alloy, back side sandblasting and cleaning, Ti-Ni-Ag is steamed at the back side, chip testing and sorting �� scribing, two-sided boron gives deposition synchronously to carry out, two-sided ion implantation aluminium aligns, the back side carries out respectively, boron impurity and aluminium impurity are carried out by high temperature knot simultaneously.
The advantage of the present invention: diffusion time is short, production energy consumption is low, efficiency height, the complete rate height of silicon chip, the transverse dispersion on isolated area surface is few, and isolated area width is little, saves silicon area.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Fig. 1 is the vertical structure sectional view of the controlled silicon chip of background technology 1;
Fig. 2 is the isolated area Impurity Distribution graphic representation of background technology 1;
Fig. 3 is the vertical structure sectional view of the controlled silicon chip of background technology 2;
Fig. 4 is the vertical structure sectional view of controlled silicon chip of the present invention;
Fig. 5 is the isolated area Impurity Distribution graphic representation of the present invention.
Wherein: 1, oxide film; 2, the gate metal electrode in front; 3, the gate metal electrode in front; 4, annular passivation groove; 5, Duan Ji district P2; 6, N-+Type cathodic area; 7, N-type growing base area; 8, positive column P1; 9, the anode metal electrodes at the back side; 10, boron impurity district; 10 ', boron impurity district; 11, boron, aluminium poly-doped impurity district; 12, aluminium impurity district; 13, aluminium-Lv Jiaodie impurity district; 14, boron, boron poly-doped impurity district.
Embodiment
As shown in Figure 4,5 with seven layers of controlled silicon chip to logical isolation structure and an its preparation method, comprise positive column P18, N-type growing base area 7, Duan Ji district P25, N-+The oxide film 1 in type cathodic area 6 and front, the gate metal electrode 2 in front, the cathodic metal electrode 3 in front, the anode metal electrodes 9 at the back side, annular passivation groove 4 and the glassivation film being filled in passivation groove and seven layers of isolation ring to logical isolation structure, the isolation ring of logical isolation structure is by boron impurity district 10 from top to bottom by seven floor, boron, aluminium poly-doped impurity district 11, aluminium impurity district 12, aluminium-Lv Jiaodie impurity district 13, aluminium impurity district 12, boron, aluminium poly-doped impurity district 11, boron impurity district forms 10, seven layers of isolation ring to logical isolation structure is vertically located between the oxide film 1 in front and the anode metal electrodes 9 at the back side and is surrounded on positive column P18, N-type growing base area 7, Duan Ji district P25 surrounding, boron impurity district 10 thickness is 20-30um, Peng Lv poly-doped impurity district 11 thickness is 25-30um, aluminium impurity district 12 thickness is 45-55um, aluminium-Lv Jiaodie impurity district 13 thickness is 30-40um.
A kind of comprise the following steps with seven layers of preparation method to the controlled silicon chip of logical isolation structure: silicon single crystal flake, chemical corrosion or polishing, silicon chip cleans, oxidation, dual surface lithography is to logical isolation window, two-sided boron gives deposition, two-sided ion implantation aluminium, subtract thin oxide film, high temperature knot, photoetching front Duan Ji district window and back anode district window, synchronously carry out Duan Ji district, front and the boron diffusion of back anode district, cathodic area, photoetching front window, the phosphorous diffusion of cathodic area, front, photoetching passivation trench openings, table top corrosion and cleaning, glassivation, photoetching front fairlead, aluminium film is steamed in front, photoetching front side aluminum electrode, alloy, back side sandblasting and cleaning, Ti-Ni-Ag is steamed at the back side, chip testing and sorting �� scribing, dual surface lithography to after logical isolation window, synchronously two-sided to logical isolation window in carry out boron and give deposition, then align respectively, the back side carries out ion implantation aluminium, subtracts thin oxide film to remove the aluminium impurity layer on oxide film surface, then boron impurity and aluminium impurity is carried out high temperature knot simultaneously.
Concrete processing step is as follows:
1, silicon single crystal flake, condition: ��=20-25-30-35-40-45-50 ��, silicon single crystal flake thickness t=(250��300) �� 5um.
2, Chemical Corrosion for Silicon Wafer or polishing, condition: silicon wafer thickness t=(210��260 after completing) �� 5um.
3, silicon chip cleans, condition: silicon chip is carried out RCA cleaning.
4, it is oxidized, condition: T=1120 �� 20 DEG C, t=8.0 �� 1h, oxidated layer thickness=1.3-1.5um.
5, dual surface lithography is to logical isolation window, condition: two-sided even photoresist material-front baking-double-sided exposure-development-heavily fortified point film-corrosion oxidation film-remove photoresist-dry.
6, two-sided boron gives deposition, condition: T=1070 �� 20 DEG C, t=2.2 �� 0.5h, R=4.5 �� 0.8 ��/, forms boron and give settled layer in isolation window.
7, two-sided ion implantation aluminium, condition: implantation dosage is 8E14/cm2To 2E15/cm2, injecting energy is 160Kev to 220Kev, and implant angle is 0 �� to 7 ��, forms aluminium input horizon in isolation window.
8, thin oxide film is subtracted, condition: with the corrosive fluid of HF:DI water=1:1 corrosion 4 to 7 minutes, the oxide thickness eroded was 0.4 to 0.7um.
9, high temperature knot, condition: T=1270 �� 10 DEG C, t=38 �� 12h, nitrogen flow=5L/min, oxygen flow=0.5L/min, defining seven floor being made up of " boron impurity district��Peng Lv poly-doped impurity district��aluminium impurity district��aluminium-Lv Jiaodie impurity district��aluminium impurity district��Peng Lv poly-doped impurity district��boron impurity district " after knot to logical isolated area, this isolated area vertically runs through silicon chip. Wherein: boron impurity district thickness is at 20-30um, and described Peng Lv poly-doped impurity district thickness is at 25-30um, and described aluminium impurity district thickness is at 45-55um, and described aluminium-Lv Jiaodie impurity district thickness is at 30-40um.
10, photoetching front Duan Ji district's window and back anode district window, condition: two-sided even photoresist material-front baking-double-sided exposure-development-heavily fortified point film-corrosion oxidation film-remove photoresist-dry.
11, front Duan Ji district window and the boron diffusion of back anode district is synchronously carried out, condition: give deposition T=930 �� 10 DEG C, t=1.0 �� 0.2h, R=70 �� 5 ��/; Knot T=1250 �� 10 DEG C, t=32 �� 6h, Xj=35 �� 10um, R=220 �� 20 ��/.
12, cathodic area, photoetching front window, condition: two-sided even photoresist material-front baking-double-sided exposure-development-heavily fortified point film-corrosion oxidation film-remove photoresist-dry.
13, cathodic area phosphorous diffusion, condition: give deposition T=1050 �� 20 DEG C, t=1.5 �� 0.2h, R=3.5 �� 0.5 ��/, then T=1200 �� 10 DEG C that distribute, t=4 �� 1h, Xj=8-20um.
14, photoetching deactivation slot window, condition: two-sided even photoresist material-front baking-double-sided exposure-development-heavily fortified point film-corrosion oxidation film-drying-heavily fortified point film.
15, table top corrosion, condition: corrosive fluid proportioning is HF: glacial acetic acid: HNO3=1:1:(4-6), HF is concentration is the solution of 42%, Glacial acetic acid (CH3COOH) it is pure, HNO3Be concentration being the solution of 67%, corrosion temperature is 5-10 DEG C, and ditch groove depth is 70-100um, and groove width is 100��200um��
16, glassivation, condition: with GP350 type glass powder, layer glass film.
17, photoetching front fairlead, condition: the even photoresist material-front baking-face exposure-development-heavily fortified point film-corrosion oxidation film in front-remove photoresist-dry.
18, aluminium film is steamed in front, condition: require aluminium film thickness=5.0-8.0um.
19, photoetching front side aluminum electrode, condition: the even photoresist material-front baking-face exposure-development-heavily fortified point film-corrosion aluminium in front-remove photoresist-dry.
20, alloy, condition: T=480 �� 10 DEG C, t=0.4 �� 0.1h.
21, back side sandblasting and cleaning, condition: use W20#0.5-1.0um is removed in Buddha's warrior attendant sand blasting, DI water ultrasonic cleaning.
22, Ti-Ni-Ag is steamed at the back side, condition: Ti thickness=1000-1400A��; Ni thickness=4000-6000A��; Ag thickness=0.5-0.8um.
23, chip testing and sorting, condition: test with the automatic testing stand of JUNO. test VDRM��VRRM��IEB��VFGM��IDRM��IRRM��IH��IL��IGT��VGTEtc. parameter, and IGT is carried out point shelves.
24, scribing, condition: saw silicon chip with veneer sawing machine and indigo plant film is drawn and cuts 1/3 thickness.
Diffusion time of the present invention is short, production energy consumption is low, efficiency height, the complete rate height of silicon chip, and the transverse dispersion on isolated area surface is few, and isolated area width is little, saves silicon area.
Claims (3)
1., with seven layers of controlled silicon chip to logical isolation structure, comprise positive column P1, N-type growing base area, Duan Ji district P2, N-+The oxide film in type cathodic area and front, the gate metal electrode in front, the cathodic metal electrode in front, the anode metal electrodes at the back side, annular passivation groove and seven layers of isolation ring to logical isolation structure, it is characterized in that: the isolation ring of logical isolation structure is by boron impurity district from top to bottom by described seven floor, Peng Lv poly-doped impurity district, aluminium impurity district, aluminium-Lv Jiaodie impurity district, aluminium impurity district, Peng Lv poly-doped impurity district, boron impurity district is formed, described seven layers of isolation ring to logical isolation structure are vertically located between the oxide film in front and the anode metal electrodes at the back side and are surrounded on positive column P1, N-type growing base area, Duan Ji district P2 surrounding.
2. according to claim 1 a kind of with seven layers of controlled silicon chip to logical isolation structure, it is characterized in that: described boron impurity district thickness is 20-30um, described Peng Lv poly-doped impurity district thickness is 25-30um, described aluminium impurity district thickness is 45-55um, and described aluminium-Lv Jiaodie impurity district thickness is 30-40um.
3. one kind with seven layers of preparation method to the controlled silicon chip of logical isolation structure is: comprise the following steps: silicon single crystal flake, chemical corrosion or polishing, silicon chip cleans, oxidation, dual surface lithography is to logical isolation window, two-sided boron gives deposition, two-sided ion implantation aluminium, subtract thin oxide film, high temperature knot, photoetching front Duan Ji district window and back anode district window, synchronously carry out Duan Ji district, front and the boron diffusion of back anode district, cathodic area, photoetching front window, the phosphorous diffusion of cathodic area, front, photoetching passivation trench openings, table top corrosion and cleaning, glassivation, photoetching front fairlead, aluminium film is steamed in front, photoetching front side aluminum electrode, alloy, back side sandblasting and cleaning, Ti-Ni-Ag is steamed at the back side, chip testing and sorting �� scribing, it is characterized in that: two-sided boron gives deposition synchronously to carry out, two-sided ion implantation aluminium aligns, the back side carries out respectively, boron impurity and aluminium impurity are carried out by high temperature knot simultaneously.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106571402A (en) * | 2016-11-18 | 2017-04-19 | 吉林瑞能半导体有限公司 | Fast recovery diode and manufacturing method thereof |
| CN108133953A (en) * | 2017-09-27 | 2018-06-08 | 中航（重庆）微电子有限公司 | A kind of silicon-controlled device and preparation method thereof |
| CN110010675A (en) * | 2019-04-09 | 2019-07-12 | 捷捷半导体有限公司 | A kind of punch mesolow plane TVS chip and preparation method thereof |
| CN112435993A (en) * | 2019-08-26 | 2021-03-02 | 广东美的白色家电技术创新中心有限公司 | Power module |
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| KR20010068221A (en) * | 2000-01-03 | 2001-07-23 | 곽정소 | Conor gate type thyristor device |
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