CN111129110A - Power chip terminal structure, and manufacturing method and device of power chip terminal structure - Google Patents

Power chip terminal structure, and manufacturing method and device of power chip terminal structure Download PDF

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Publication number
CN111129110A
CN111129110A CN201911250604.0A CN201911250604A CN111129110A CN 111129110 A CN111129110 A CN 111129110A CN 201911250604 A CN201911250604 A CN 201911250604A CN 111129110 A CN111129110 A CN 111129110A
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oxide layer
stop ring
type
power chip
field
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Inventor
董少华
金锐
刘江
高明超
刘钺杨
和峰
王耀华
李立
吴军民
潘艳
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Global Energy Interconnection Research Institute
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Global Energy Interconnection Research Institute
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Abstract

The invention provides a power chip terminal structure, a manufacturing method and a device of the power chip terminal structure, wherein a P-type field limiting ring (2), a stop ring (4) and an oxide layer are formed on the front surface of an N-type substrate (1); lead holes are arranged on the P-type field limiting ring (2) and the stop ring (4), and a built-in field plate (6) and a stop ring metal (9) are formed on the front surface of the oxide layer based on the lead holes; a passivation layer (7) is formed on the front surfaces of the oxide layer, the built-in field plate (6) and the cut-off ring metal (9), so that the terminal structure is not easy to lose efficacy; the length requirement of the built-in field plate (6) is not high, and the design difficulty and complexity are reduced; the invention improves the surface charge contamination resistance of the terminal structure, reduces the sensitivity of the power chip to charges, and further improves the reliability of the terminal structure; the invention has simple process, is compatible with the traditional manufacturing process of the power chip and has strong feasibility of implementation; the invention is suitable for various power chips such as IGBT, VDMOS, FRD and the like.

Description

Power chip terminal structure, and manufacturing method and device of power chip terminal structure
Technical Field
The invention relates to the technical field of power electronic devices, in particular to a power chip terminal structure, and a manufacturing method and device of the power chip terminal structure.
Background
In the power chip, a local electric field peak value is formed under the influence of factors such as PN junction bending and the like, and the breakdown voltage of the power chip is far smaller than the breakdown voltage of an ideal PN junction. In order to reduce the peak value of a local electric field, improve the surface breakdown voltage and the reliability and enable the actual breakdown voltage of a power chip to be closer to an ideal value, a junction termination technology is generated due to operation.
The terminal structures of the power chips can be roughly divided into two types, namely an extension type terminal structure and a truncation type terminal structure, and a few power chips adopt a structure combining the extension type terminal structure and the truncation type terminal structure. The extended terminal structure is provided with some extended structures at the edge of the main junction, and the extended structures actually play a role in widening a depletion region of the main junction outwards, so that the electric field intensity is reduced, and the breakdown voltage is finally improved. Extended termination structures are commonly used in planar processes such as field plate field rings, junction termination extensions, lateral variable doping, resistive field plates. The truncation type terminal structure is to truncate the PN junction by means of wet etching of a curved surface groove, edge etching after scribing and lead welding, edge angle grinding of a wafer, dry etching of a deep groove and the like, to influence the surface electric field distribution by utilizing the truncation appearance, to realize the improvement of surface breakdown by combining with good surface passivation, and to be generally suitable for a table top or a grooving process.
The field ring in the extended terminal structure has the defects of sensitivity to surface charge contamination, low terminal efficiency, complex design and the like, and is usually used in combination with a field plate. The extended terminal structure combining the field ring and the field plate can effectively overcome the defects that the field ring is sensitive to surface charge contamination and the terminal efficiency is low; and the process is simple, is compatible with the main process, and is widely applied to power chips. However, an electric field peak value is introduced into the end of the field plate by the extended terminal structure formed by combining the field ring and the field plate, so that the field oxide layer and the isolation oxide layer are easily broken down, the length of the field plate needs to be strictly controlled, the field plate is not enough in length, and the field oxide layer and the isolation oxide layer are broken down due to the overlong length of the field plate, so that the terminal structure is easy to fail.
Disclosure of Invention
In order to overcome the defect that a terminal structure in the prior art is easy to lose efficacy, the invention provides a power chip terminal structure, a manufacturing method and a device of the power chip terminal structure, wherein a P-type field limiting ring (2), a stop ring (4) and an oxide layer are formed on the front surface of an N-type substrate (1); lead holes are formed in the P-type field limiting ring (2) and the stop ring (4), and a built-in field plate (6) and a stop ring metal (9) are formed on the front surface of the oxide layer based on the lead holes; and a passivation layer (7) is formed on the front surfaces of the built-in field plate (6) and the cut-off ring metal (9), so that the terminal structure is not easy to fail.
In order to achieve the purpose of the invention, the invention adopts the following technical scheme:
in one aspect, the present invention provides a method for manufacturing a power chip terminal structure, including:
forming a P-type field limiting ring (2), a stop ring (4) and an oxide layer on the front surface of an N-type substrate (1);
arranging lead holes on the P-type field limiting ring (2) and the stop ring (4), and forming a built-in field plate (6) and a stop ring metal (9) on the front surface of the oxide layer based on the lead holes;
and forming a passivation layer (7) on the front surfaces of the oxide layer, the built-in field plate (6) and the stop ring metal (9).
The positive surface of N type substrate (1) forms P type field limiting ring (2), stop ring (4) and oxide layer, includes:
forming a P-type field limiting ring (2) on the front surface of an N-type substrate (1) by adopting an oxidation, gluing, exposure, development, ion implantation, glue removal and high-temperature annealing process;
then, a field oxide layer (3) is formed by adopting a high-temperature oxidation process, and the field oxide layer (3) completely covers the P-type field limiting ring (2);
then, a diffusion process combining a Pocl3 gaseous source, a PH3 gaseous source and a P2O5 solid source is adopted, and a stop ring (4) is formed on the front surface of the N-type substrate (1) by etching the field oxide layer (3);
and forming an isolation oxide layer (5) on the front surface of the stop ring (4) and the front surface of the field oxide layer (3) by adopting a deposition and reflow process.
The method is characterized in that lead holes are formed in a P-type field limiting ring (2) and a stop ring (4), and a built-in field plate (6) and a stop ring metal (9) are formed on the front surface of the oxide layer on the basis of the lead holes, and the method comprises the following steps:
a plurality of lead holes are respectively formed on the front surfaces of the P-type field limiting ring (2) and the stop ring (4) by adopting photoetching, etching and photoresist removing processes;
and depositing metal in the lead wire hole, and forming a built-in field plate (6) and a stop ring metal (9) by adopting photoetching, etching, photoresist removing and alloy processes.
One or more P-type field limiting rings (2) are arranged;
one lead hole of the stop ring (4);
the number of the lead holes on the P-type field limiting ring (2) is determined based on the surface charge quantity and the charge distribution condition of the power chip.
The implantation dosage of the ion implantation is 1e13cm-2～1e15 cm-2；
The doping concentration of the N-type substrate (1) is 1E11cm-3To 1E15cm-3；
The thickness of the field oxide layer (3) is 0.8 um-2 um.
The stop ring (4) is an N-type stop ring, a P-type stop ring or an N + P-type stop ring;
the isolation oxidation layer (5) adopts boron-phosphorus-silicon glass BPSG, phosphorus-silicon glass PSG or undoped silicon glass USG.
In another aspect, the invention provides a power chip termination structure, which includes a P-type field limiting ring (2), a stop ring (4) and an oxide layer disposed on a front surface of an N-type substrate (1), a built-in field plate (6) and a stop ring metal (9) disposed on the front surface of the oxide layer, and a passivation layer (7) disposed on the front surfaces of the oxide layer, the built-in field plate (6) and the stop ring metal (9).
The oxide layer comprises a field oxide layer (3) and an isolation oxide layer (5);
the field oxide layer (3) is positioned on the front surface of the N-type substrate;
the isolation oxide layer (5) is located on the front surfaces of the field oxide layer (3) and the stop ring (4).
One or more P-type field limiting rings (2) are arranged;
one lead hole of the stop ring (4);
the number of the lead holes on the P-type field limiting ring (2) is determined based on the surface charge quantity and the charge distribution condition of the power chip.
The doping concentration of the N-type substrate (1) is 1E11cm-3To 1E15cm-3；
The thickness of the field oxide layer (3) is 0.8 um-2 um.
The stop ring (4) is an N-type stop ring, a P-type stop ring or an N + P-type stop ring;
the isolation oxidation layer (5) adopts boron-phosphorus-silicon glass BPSG, phosphorus-silicon glass PSG or undoped silicon glass USG.
Compared with the closest prior art, the technical scheme provided by the invention has the following beneficial effects:
in the manufacturing method of the power chip terminal structure, the P-type field limiting ring (2), the stop ring (4) and the oxide layer are sequentially formed on the front surface of the N-type substrate (1); lead holes are formed in the P-type field limiting ring (2) and the stop ring (4), and a built-in field plate (6) and a stop ring metal (9) are formed on the front surface of the oxide layer based on the lead holes; a passivation layer (7) is formed on the front surfaces of the oxide layer, the built-in field plate (6) and the cut-off ring metal (9), so that the terminal structure is not easy to lose efficacy;
the built-in field plate (6) is adopted, the ring width of the P-type field limiting rings (2) and the distance between the P-type field limiting rings (2) are insensitive, the length requirement of the built-in field plate (6) is not high, and the design difficulty and complexity are reduced;
the terminal structure provided by the invention has strong surface charge contamination resistance, reduces the sensitivity of the power chip to charges, and further improves the reliability of the terminal structure;
the invention has simple process, is compatible with the traditional manufacturing process of the power chip and has strong feasibility of implementation;
the invention is suitable for various power chips such as IGBT, VDMOS, FRD and the like.
Drawings
FIG. 1 is a flow chart of a method for fabricating a power chip termination structure according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of forming a P-type field limiting ring according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating the formation of a field oxide layer according to an embodiment of the present invention;
FIG. 4 is a schematic view of an embodiment of the present invention in which a stop ring is formed;
FIG. 5 is a schematic diagram illustrating the formation of an isolation oxide layer according to an embodiment of the present invention;
fig. 6 is a schematic diagram of forming a built-in field plate and a stop ring metal in an embodiment of the invention;
FIG. 7 is a schematic diagram of the formation of a passivation layer in an embodiment of the invention;
FIG. 8 is a schematic diagram of a first power chip terminal structure according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a terminal structure of a second power chip in the embodiment of the present invention;
in the figure, 1, an N-type substrate, 2, a P-type field limiting ring, 3, a field oxide layer, 4, a stop ring, 5, an isolation oxide layer, 6, a built-in field plate, 7, a passivation layer, 8, a groove, 9, a stop ring metal, 10, a P-type doped layer of an active region, 11 and an active region metal.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
Example 1
Embodiment 1 of the present invention provides a method for manufacturing a power chip terminal structure, where a specific flowchart is shown in fig. 1, and the specific process is as follows:
s101: forming a P-type field limiting ring 2, a stop ring 4 and an oxide layer on the front surface of an N-type substrate 1;
s102: lead wire holes are formed in the P-type field limiting ring 2 and the stop ring 4, and a built-in field plate 6 and a stop ring metal 9 are formed on the front surface of the oxide layer based on the lead wire holes;
s103: a passivation layer 7 is formed on the front surfaces of the oxide layer, the built-in field plate 6 and the stop ring metal 9, as shown in fig. 7.
In S101, forming a P-type field limiting ring 2, a stop ring 4 and an oxide layer on the front surface of an N-type substrate 1, including:
forming a P-type field limiting ring 2 on the front surface of an N-type substrate 1 by adopting an oxidation, gluing, exposure, development, ion implantation, glue removal and high-temperature (1050 ℃ -1250 ℃ is selected) annealing process, as shown in fig. 2;
then, a high-temperature oxidation process is adopted to form a field oxide layer 3, as shown in fig. 3, and the field oxide layer 3 completely covers the P-type field limiting ring 2; in the process of forming the field oxide layer 3, a semi-insulating oxide film, silicon nitride, or the like may be used in combination;
then, a diffusion process combining a Pocl3 gaseous source, a PH3 gaseous source and a P2O5 solid source is adopted, and a stop ring 4 is formed on the front surface of the N-type substrate 1 by etching the field oxide layer 3, as shown in FIG. 4;
an isolation oxide layer 5 is formed on the front surface of the stopper ring 4 and the front surface of the field oxide layer 3 using a deposition and reflow process, as shown in fig. 5.
As shown in fig. 2, in the actual IBGT chip fabrication process, the P-type field limiting ring 2 of the termination structure and the P-type doped layer 10 of the active region are formed simultaneously.
In S102, the method includes providing a pin hole in the P-type field limiting ring 2 and the stop ring 4, and forming the built-in field plate 6 and the stop ring metal 9 on the front surface of the oxide layer based on the pin hole, and includes:
forming a plurality of lead holes on the front surfaces of the P-type field limiting ring 2 and the stop ring 4 respectively by adopting photoetching, etching and photoresist removing processes;
depositing metal in the lead wire hole, and forming the built-in field plate 6 and the stop ring metal 9 by adopting the processes of photoetching, etching, photoresist removal and alloying, as shown in fig. 6, in the specific process of manufacturing the power chip, the active region metal 11 is formed simultaneously with the built-in field plate 6 and the stop ring metal 9.
One or more P-type field limiting rings 2;
one lead hole of the stop ring 4 is provided;
the number of the pin holes on the P-type field limiting ring 2 is determined based on the surface charge quantity and the charge distribution condition of the power chip.
The implantation dose of the ion implantation is 1e13cm-2～1e15cm-2；
The substrate and the field limiting ring can form a PN junction, and in embodiment 1 of the present invention, the N-type substrate 1 is selected, the substrate is not limited to an N-type substrate, and may also be a P-type substrate, and when a P-type substrate is selected, the field limiting ring is an N-type doped field limiting ring. The doping concentration of the N-type substrate 1 of embodiment 1 of the present invention is 1E11cm-3To 1E15cm-3；
The thickness of the field oxide layer 3 is 0.8 um-2 um.
The stop ring 4 is an N-type stop ring, a P-type stop ring or an N + P-type stop ring;
the isolation oxide layer 5 is made of Boron Phosphorus Silicon Glass (BPSG) (boro phosphorus Silicon glass), Phosphorus Silicon Glass (PSG) (phosphorus Silicon glass) or Undoped Silicon Glass (USG) (undoped Silicon glass).
In the actual manufacturing process of the power chip, the passivation layer 7 only covers the terminal structure, and the active region does not have the passivation layer.
Example 2
Embodiment 2 of the present invention provides a power chip terminal structure, which is specifically manufactured by using the manufacturing method of the power chip terminal structure provided in embodiment 1 of the present invention, as shown in fig. 8. The semiconductor device comprises a P-type field limiting ring 2, a stop ring 4 and an oxide layer which are arranged on the front surface of an N-type substrate 1, a built-in field plate 6 and a stop ring metal 9 which are arranged on the front surface of the oxide layer, and a passivation layer 7 which is arranged on the front surfaces of the oxide layer, the built-in field plate 6 and the stop ring metal 9.
The oxide layer comprises a field oxide layer 3 and an isolation oxide layer 5;
the field oxide layer 3 is positioned on the front surface of the N-type substrate 1;
the isolation oxide layer 5 is located on the front surfaces of the field oxide layer 3 and the cutoff ring 4.
One or more P-type field limiting rings 2;
one lead hole of the stop ring 4 is provided;
the number of the pin holes on the P-type field limiting ring 2 is determined based on the surface charge quantity and the charge distribution condition of the power chip.
N-type substrate 1 having doping concentration of 1E11cm-3To 1E15cm-3；
The thickness of the field oxide layer 3 is 0.8 um-2 um.
The stop ring 4 is an N-type stop ring, a P-type stop ring or an N + P-type stop ring;
the isolation oxide layer 5 is made of BPSG, PSG or USG.
The process of forming the P-type field limiting ring 2 on the front surface of the N-type substrate 1 can be directly formed by adopting an oxidation, gluing, exposure, development, ion injection, degumming and high-temperature annealing process, the groove 8 can be arranged on the front surface of the N-type substrate 1, a power chip terminal structure manufactured by arranging the groove 8 is shown in fig. 9, the P-type field limiting ring 2 is formed by adopting the groove 8 and adopting the process, the depletion layer can be expanded into the body as much as possible by forming the P-type field limiting ring 2 by arranging the groove 8, and the terminal structure has small area and high efficiency.
For convenience of description, each part of the above-described apparatus is separately described as being functionally divided into various modules or units. Of course, the functionality of the various modules or units may be implemented in the same one or more pieces of software or hardware when implementing the present application.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Finally, it should be noted that: the above embodiments are only intended to illustrate the technical solution of the present invention and not to limit the same, and a person of ordinary skill in the art can make modifications or equivalents to the specific embodiments of the present invention with reference to the above embodiments, and such modifications or equivalents without departing from the spirit and scope of the present invention are within the scope of the claims of the present invention as set forth in the claims.

Claims (11)

1. A method for manufacturing a power chip terminal structure is characterized by comprising the following steps:
forming a P-type field limiting ring (2), a stop ring (4) and an oxide layer on the front surface of an N-type substrate (1);
arranging lead holes on the P-type field limiting ring (2) and the stop ring (4), and forming a built-in field plate (6) and a stop ring metal (9) on the front surface of the oxide layer based on the lead holes;
and forming a passivation layer (7) on the front surfaces of the oxide layer, the built-in field plate (6) and the stop ring metal (9).
2. The method for manufacturing the power chip terminal structure according to claim 1, wherein the forming of the P-type field limiting ring (2), the stop ring (4) and the oxide layer on the front surface of the N-type substrate (1) comprises:
forming a P-type field limiting ring (2) on the front surface of an N-type substrate (1) by adopting an oxidation, gluing, exposure, development, ion implantation, glue removal and high-temperature annealing process;
then, a field oxide layer (3) is formed by adopting a high-temperature oxidation process, and the field oxide layer (3) completely covers the P-type field limiting ring (2);
then, a diffusion process combining a Pocl3 gaseous source, a PH3 gaseous source and a P2O5 solid source is adopted, and a stop ring (4) is formed on the front surface of the N-type substrate (1) by etching the field oxide layer (3);
and forming an isolation oxide layer (5) on the front surface of the stop ring (4) and the front surface of the field oxide layer (3) by adopting a deposition and reflow process.
3. The method for manufacturing the power chip terminal structure according to claim 2, wherein the step of providing the lead holes on the P-type field limiting ring (2) and the stop ring (4) and forming the built-in field plate (6) and the stop ring metal (9) on the front surface of the oxide layer based on the lead holes comprises the steps of:
a plurality of lead holes are respectively formed on the front surfaces of the P-type field limiting ring (2) and the stop ring (4) by adopting photoetching, etching and photoresist removing processes;
and depositing metal in the lead wire hole, and forming a built-in field plate (6) and a stop ring metal (9) by adopting photoetching, etching, photoresist removing and alloy processes.
4. The method for manufacturing the power chip termination structure according to claim 3, wherein the number of the P-type field limiting rings (2) is one or more;
one lead hole of the stop ring (4);
the number of the lead holes on the P-type field limiting ring (2) is determined based on the surface charge quantity and the charge distribution condition of the power chip.
5. The method as claimed in claim 2, wherein the ion implantation dose is 1e13cm-2～1e15cm-2；
The doping concentration of the N-type substrate (1) is 1E11cm-3To 1E15cm-3；
The thickness of the field oxide layer (3) is 0.8 um-2 um.
6. The method for manufacturing the power chip termination structure according to claim 2, wherein the stop ring (4) is an N-type stop ring, a P-type stop ring or an N + P-type stop ring;
the isolation oxidation layer (5) adopts boron-phosphorus-silicon glass BPSG, phosphorus-silicon glass PSG or undoped silicon glass USG.
7. The power chip terminal structure is characterized by comprising a P-type field limiting ring (2), a stop ring (4) and an oxide layer which are arranged on the front surface of an N-type substrate (1), a built-in field plate (6) and a stop ring metal (9) which are arranged on the front surface of the oxide layer, and a passivation layer (7) which is arranged on the front surfaces of the oxide layer, the built-in field plate (6) and the stop ring metal (9).
8. The power chip termination structure according to claim 7, wherein the oxide layer comprises a field oxide layer (3) and an isolation oxide layer (5);
the field oxide layer (3) is positioned on the front surface of the N-type substrate (1);
the isolation oxide layer (5) is located on the front surfaces of the field oxide layer (3) and the stop ring (4).
9. The power chip termination structure according to claim 7, wherein the number of the P-type field limiting rings (2) is one or more;
one lead hole of the stop ring (4);
the number of the lead holes on the P-type field limiting ring (2) is determined based on the surface charge quantity and the charge distribution condition of the power chip.
10. The power chip termination structure according to claim 7, wherein the N-type substrate (1) has a doping concentration of 1E11cm-3To 1E15cm-3；
The thickness of the field oxide layer (3) is 0.8 um-2 um.
11. The device for manufacturing the power chip termination structure according to claim 8, wherein the stop ring (4) is an N-type stop ring, a P-type stop ring or an N + P-type stop ring;
the isolation oxidation layer (5) adopts boron-phosphorus-silicon glass BPSG, phosphorus-silicon glass PSG or undoped silicon glass USG.
CN201911250604.0A 2019-12-09 2019-12-09 Power chip terminal structure, and manufacturing method and device of power chip terminal structure Pending CN111129110A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116153969A (en) * 2023-03-03 2023-05-23 深圳吉华微特电子有限公司 High-voltage fast recovery diode resistant to single particle burning and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116153969A (en) * 2023-03-03 2023-05-23 深圳吉华微特电子有限公司 High-voltage fast recovery diode resistant to single particle burning and manufacturing method thereof

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