CN106409890B - The forming method of fin bipolar junction transistor - Google Patents
The forming method of fin bipolar junction transistor Download PDFInfo
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- CN106409890B CN106409890B CN201510451932.2A CN201510451932A CN106409890B CN 106409890 B CN106409890 B CN 106409890B CN 201510451932 A CN201510451932 A CN 201510451932A CN 106409890 B CN106409890 B CN 106409890B
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- 238000000034 method Methods 0.000 title claims abstract description 52
- 239000004065 semiconductor Substances 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 150000002500 ions Chemical class 0.000 claims description 225
- 238000005516 engineering process Methods 0.000 claims description 38
- 238000002513 implantation Methods 0.000 claims description 34
- 238000005468 ion implantation Methods 0.000 claims description 32
- 239000000463 material Substances 0.000 claims description 31
- 239000007943 implant Substances 0.000 claims description 20
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 7
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical group [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 description 18
- 230000000694 effects Effects 0.000 description 10
- 230000005540 biological transmission Effects 0.000 description 8
- 238000002955 isolation Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
- 230000005669 field effect Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000002243 precursor Substances 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910052986 germanium hydride Inorganic materials 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6625—Lateral transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
- H01L29/0808—Emitter regions of bipolar transistors of lateral transistors
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- Power Engineering (AREA)
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Abstract
A kind of forming method of fin bipolar junction transistor, comprising: semiconductor substrate is provided；Collector fin, base fin and emitter fin are formed in semiconductor substrate surface, for base fin between collector fin and emitter fin, the collector fin, base fin and emitter fin are parallel to each other；Base epitaxial layer is formed on the base fin surface；Collector epitaxial layer is formed on collector fin surface；The impure base fin ion in the base fin and base epitaxial layer；The impure collecting electrode fin ion in the collector fin and collector epitaxial layer；The first emitter ion and the second emitter ion are adulterated in the emitter fin, the second emitter ion is located at the top of emitter fin, the first emitter ion is located at the bottom of the second emitter ion, and the concentration of the second emitter ion is greater than the concentration of the first emitter ion.The forming method of the fin bipolar junction transistor improves the performance of fin bipolar junction transistor.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of forming methods of fin bipolar junction transistor.
Background technique
Bipolar junction transistor (Bipolar Junction Transistor, BJT) is also known as transistor, it
It is to be closely adjacent to each other by two and back-to-back PN junction is bonded, is divided into two kinds of composite structures of PNP and NPN.Dipole is brilliant
There are three poles for body pipe tool: collector, emitter and base stage.Bipolar junction transistor plays the role of amplified signal, relies primarily on hair
Emitter current can reach what collecting zone was realized by base transport.Bipolar junction transistor because can amplified signal, preferably
Power control, high speed operation and endurance, thus be widely used.
MOS transistor is one of most important element in modern integrated circuits.MOS transistor is adjusted by applying voltage
Switching signal is generated by the electric current of channel.
In general, bipolar junction transistor and MOS transistor integrate composition semiconductor devices.
With the development of semiconductor technology, the MOS transistor of traditional plane formula dies down to the control ability of channel current,
Cause serious leakage current.Fin formula field effect transistor (Fin FET) is a kind of emerging multi-gate device, it generally comprises protrusion
In the fin of semiconductor substrate surface, the top of fin and the gate structure of side wall described in covering part are located at gate structure one
The drain region in source region and gate structure other side fin in lateral fin portion.Fin formula field effect transistor is because can significantly improve electricity
Road and the MOS transistor for reducing leakage current and substitutive patterns formula.
In order to enable the technique for preparing bipolar junction transistor is mutually compatible with the technique for preparing fin formula field effect transistor, it is existing
Have in technology using preparation fin bipolar junction transistor and by fin bipolar junction transistor and fin formula field effect transistor collection
At together.
But as characteristic size further reduces, the prior art formed fin bipolar junction transistor performance compared with
Difference.
Summary of the invention
Problems solved by the invention is to provide a kind of forming method of fin bipolar junction transistor, improves fin bipolar junction
The performance of transistor npn npn.
To solve the above problems, the present invention provides a kind of forming method of fin bipolar junction transistor, comprising: provide half
Conductor substrate；Collector fin, base fin and emitter fin, base fin, which are formed, in the semiconductor substrate surface is located at collector fin
Between emitter fin, the collector fin, base fin and emitter fin are parallel to each other；Base stage is formed on the base fin surface
Epitaxial layer；Collector epitaxial layer is formed on collector fin surface；The impure base in the base fin and base epitaxial layer
Fin ion；The impure collecting electrode fin ion in the collector fin and collector epitaxial layer；Is adulterated in the emitter fin
One emitter ion and the second emitter ion, the second emitter ion are located at the top of emitter fin, first hair
Emitter-base bandgap grading ion is located at the bottom of the second emitter ion, and the concentration of the second emitter ion is greater than the first emitter ion
Concentration.
Optionally, the base fin surrounds emitter fin, and the collector fin surrounds the base fin.
Optionally, when the quantity of the base fin is multiple, the multiple base fin is parallel to each other；When the collector
When the quantity of fin is multiple, the multiple collector fin is parallel to each other；It is described more when the quantity of the emitter fin is multiple
A emitter fin is parallel to each other.
Optionally, the fin bipolar junction transistor is positive-negative-positive fin bipolar junction transistor.
Optionally, the concentration of the second emitter ion is 1E15atom/cm2~3E15atom/cm2；First hair
The concentration of emitter-base bandgap grading ion is 3E14atom/cm2~1E15atom/cm2。
Optionally, the first emitter ion and the second emitter ion are P-type ion.
Optionally, the technique for adulterating the first emitter ion to the emitter fin is the first emitter ion implanting work
Skill；The technique for adulterating the second emitter ion to the emitter fin is the second emitter ion implantation technology.
Optionally, the ion that the first emitter ion implantation technology uses for B ion, Implantation Energy be 3KeV~
5KeV, implantation dosage 3E14atom/cm2~1E15atom/cm2, implant angle is 0 degree~7 degree.
Optionally, the ion that the first emitter ion implantation technology uses is BF2Ion, Implantation Energy be 8KeV~
15KeV, implantation dosage 3E14atom/cm2~1E15atom/cm2, implant angle is 0 degree~7 degree.
Optionally, the ion that the second emitter ion implantation technology uses for B ion, Implantation Energy be 1KeV~
3KeV, implantation dosage 1E15atom/cm2~3E15atom/cm2, implant angle is 0 degree~7 degree.
Optionally, the ion that the second emitter ion implantation technology uses is BF2Ion, Implantation Energy be 4KeV~
7KeV, implantation dosage 1E15atom/cm2~3E15atom/cm2, implant angle is 0 degree~7 degree.
Optionally, the material of the collector epitaxial layer is SiGe；The material of the base epitaxial layer is silicon carbide.
Optionally, the base fin ion is N-type ion；The collector fin ion is P-type ion.
Optionally, the concentration of the base fin ion is 5E14atom/cm2~1E15atom/cm2；The collector fin from
The concentration of son is 3E14atom/cm2~1E15atom/cm2。
It optionally, is base fin ion implanting work to the technique of the base fin and base epitaxial layer impure base fin ion
Skill；Technique to the collector fin and collector epitaxial layer impure collecting electrode fin ion is collector fin ion implantation technology.
Optionally, for the ion that the base fin ion implantation technology uses for P ion, Implantation Energy is 6KeV~10KeV,
Implantation dosage is 5E14atom/cm2~1E15atom/cm2, implant angle is 0 degree Celsius~7 degrees Celsius.
Optionally, the ion that the collector fin ion implantation technology uses for B ion, Implantation Energy be 3KeV~
5KeV, implantation dosage 3E14atom/cm2~1E15atom/cm2, implant angle is 0 degree Celsius~7 degrees Celsius.
Optionally, the semiconductor substrate includes the first well region and the second trap for being connected in the horizontal direction with the first well region
Area, the ionic type adulterated in second well region and the first well region on the contrary, the collector fin is located at the first well region surface, and
The ionic type adulterated in collector fin ion and the first well region is identical, and the base fin and the emitter fin are located at the second trap
Area surface.
Compared with prior art, technical solution of the present invention has the advantage that
The forming method of fin bipolar junction transistor provided by the invention is emitted using forming first in emitter fin
Pole ion and the second emitter ion, the second emitter ion are located at the top of emitter fin and the second emitter ion
Concentration is greater than the concentration of the first emitter ion, and the second emitter ion can reduce subsequent in emitter fin top surface
Contact berrier between the electrode and emitter fin of formation.
Further, when the quantity of the emitter fin is multiple, due to being not necessarily formed on emitter fin surface
Emitter epitaxial layer can effectively avoid causing to connect between the epitaxial layer of adjacent transmission pole because needing to form emitter epitaxial layer
The phenomenon that connecing, to effectively avoid through the total current reduction of emitter fin and fin bipolar junction transistor stability
The problem of decline.
Detailed description of the invention
Fig. 1 to Fig. 3 is the schematic diagram of fin bipolar junction transistor forming process in one embodiment of the invention；
Fig. 4 to Fig. 9 is the schematic diagram of fin bipolar junction transistor forming process in another embodiment of the present invention.
Specific embodiment
As characteristic size further reduces, the performance for the fin bipolar junction transistor that the prior art is formed is poor.
One embodiment of the invention provides a kind of forming method of fin bipolar junction transistor, and referring to figs. 1 to Fig. 3, Fig. 2 is
Along the sectional view of Y1-Y2 axis in Fig. 1, Fig. 3 is the schematic diagram formed on the basis of Fig. 2, comprising: provides semiconductor substrate
100；Multiple parallel emitter fins 110, multiple parallel base fins 120 and more are formed on 100 surface of semiconductor substrate
A parallel collector fin 130, the multiple base fin 120 surround the multiple emitter fin 110, the multiple collector fin
130 surround the multiple base fin 120, and emitter fin 110, base fin 120 and collector fin 130 are parallel to each other；Described
110 surface of emitter fin forms emitter epitaxial layer 111；Base epitaxial layer 121 is formed on 120 surface of base fin；Institute
It states 130 surface of collector fin and forms collector epitaxial layer 131.
In the semiconductor substrate 100 include well region 101, the well region 101 include the first well region 1011 and with the first trap
The second well region 1012 that area 1011 is connected in the horizontal direction, 130 1011 surfaces of the first well region of the collector fin, the base
Pole fin 120 and emitter fin 110 are located at 1012 surface of the second well region.100 surface of semiconductor substrate also has isolation structure
102, the surface of isolation structure 102 is lower than emitter fin 110, the top surface of base fin 120 and collector fin 130, isolation junction
Structure 102 is used for electric isolation emitter fin 110, base fin 120 and collector fin 130.
Since the area of the emitter epitaxial layer 111 is larger, the emitter epitaxial layer 111 can reduce subsequent sending out
The resistance between electrode and emitter fin 110 that 111 top surface of emitter-base bandgap grading epitaxial layer is formed.When the fin bipolar junction transistor
When pipe is positive-negative-positive fin bipolar junction transistor, the material of the emitter epitaxial layer 111 is SiGe.
The study found that the fin bipolar junction transistor that the above method is formed still remains the reason of Performance And Reliability difference
It is:
The emitter fin is located at the central area of semiconductor substrate, relative to emitter fin in the position of semiconductor substrate
It sets, base fin and collector fin are located at the region of semiconductor substrate periphery.Forming emitter epitaxial layer, base epitaxial layer sum aggregate
During electrode epitaxial layer, it is used to form each precursor gas of emitter epitaxial layer, base epitaxial layer and collector epitaxial layer
The distribution of body has the characteristics that common: the precursor gas volume density of heart overlying regions is greater than in the semiconductor substrate serves as a contrast in semiconductor
Precursor gas volume density above the peripheral region of bottom, therefore the rate for forming emitter epitaxial layer is larger, so that adjacent emitter
Epitaxial layer is easy to be connected with each other.On the other hand, due to the quantity of the emitter fin in the section by Y1-Y2 axis in Fig. 1
More, the probability for causing adjacent transmission pole epitaxial layer to connect is larger, connects as long as adjacent transmission pole epitaxial layer occurs at one
The phenomenon that connecing will accelerate the rate to form emitter epitaxial layer, may cause entire emitter epitaxial layer connection.Another side
Face, when the fin bipolar junction transistor is positive-negative-positive fin bipolar junction transistor, the material of emitter epitaxial layer is germanium
SiClx, SiGe is variant in the rate that different directions are grown, and emitter epitaxial layer is perpendicular to emitter fin sidewall direction
Section shape is hexagon, so that adjacent emitter epitaxial layer is easy to be connected with each other.Epitaxial layer connection in adjacent transmission pole is led
Show lower drawback: so that the total current by emitter fin reduces；It not can control and emit in different fin bipolar junction transistors
The situation of pole epitaxial layer connection, causes the bad stability of fin bipolar junction transistor performance.
On this basis, another embodiment of the present invention provides a kind of forming methods of fin bipolar junction transistor, comprising:
Semiconductor substrate is provided；Collector fin, base fin and multiple parallel emitter fins, base are formed in the semiconductor substrate surface
Pole fin is located between collector fin and the multiple emitter fin, and the collector fin, base fin and emitter fin are parallel to each other；
Base epitaxial layer is formed on the base fin surface；Collector epitaxial layer is formed on collector fin surface；In the base stage
Impure base fin ion in fin and base epitaxial layer；In the collector fin and collector epitaxial layer impure collecting electrode fin from
Son；The first emitter ion and the second emitter ion are adulterated in the emitter fin, the second emitter ion is located at
The top of emitter fin, the first emitter ion are located at the bottom of the second emitter ion, and second emitter from
The concentration of son is greater than the concentration of the first emitter ion.
Compared to previous embodiment, due to using formed in emitter fin the first emitter ion and the second emitter from
Son, the concentration that the second emitter ion is located at the top of emitter fin and the second emitter ion be greater than the first emitter from
The concentration of son, the second emitter ion can reduce the subsequent electrode and emitter fin formed in emitter fin top surface
Between contact berrier.In addition, can effectively be avoided due to not necessarily forming emitter epitaxial layer on emitter fin surface
Lead to the phenomenon that connecting between the epitaxial layer of adjacent transmission pole because needing to form emitter epitaxial layer, to effectively avoid logical
The problem of total current for crossing emitter fin reduces and fin bipolar junction transistor stability declines.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
In conjunction with reference Fig. 4 and Fig. 5, wherein Fig. 5 is the sectional view along Y3-Y4 axis in Fig. 4, provides semiconductor substrate
200；Collector fin 230, base fin 220 and emitter fin 210 are formed on 200 surface of semiconductor substrate, base fin 220
Between collector fin 230 and emitter fin 210, the emitter fin 210, base fin 220 and collector fin 230 are put down each other
Row.
The quantity of the base fin 220 is one or more；The quantity of the collector fin 230 is one or more, institute
The quantity of emitter fin 210 is stated as one or more.When the quantity of the base fin 220 be it is multiple when, each base fin 220 that
This is parallel；When the quantity of the collector fin 230 is multiple, each collector fin 230 is parallel to each other, when the emitter fin
When 210 quantity is multiple, each emitter fin 210 is parallel to each other.
In the present embodiment, the arrangement of the emitter fin 210, base fin 220 and collector fin 230 are as follows: base fin 220 is enclosed
Around emitter fin 210, collector fin 230 surrounds base fin 220, and the mode of the arrangement enables collector fin 210 from each
Direction collected current, the total current by collector fin 210 is larger, reduces leakage current；In another embodiment, the transmitting
The arrangement of pole fin 210, base fin 220 and collector fin 230 are as follows: base fin 220 is only positioned at the side of emitter fin 210, current collection
Pole fin 230 is only positioned at the side of base fin 220, and base fin 220 is between emitter fin 210 and emitter fin 210.
In the present embodiment, illustrated for forming positive-negative-positive fin bipolar junction transistor, it in other embodiments, can also be with
Form NPN type fin bipolar junction transistor.
The semiconductor substrate 200 provides technique platform to be subsequently formed fin bipolar junction transistor.
The semiconductor substrate 200 can be monocrystalline silicon, polysilicon or amorphous silicon；Semiconductor substrate 200 be also possible to silicon,
The semiconductor materials such as germanium, SiGe, GaAs；The semiconductor substrate 200 can be body material, be also possible to composite construction,
Such as silicon-on-insulator；The semiconductor substrate 200 can also be other semiconductor materials, no longer illustrate one by one here.This implementation
In example, the material of the semiconductor substrate 200 is silicon.
In the semiconductor substrate 200 have well region 201, the well region 201 include the first well region 2011 and with the first trap
Adulterated in the second well region 2012 that area 2011 is connected in the horizontal direction, second well region 2012 and the first well region 2011 from
Subtype is opposite.
The effect of first well region 2011 and the second well region 2012 are as follows: first well region 2011 and the collector that is subsequently formed
Fin is connected, and collectively forms collecting zone；Second well region 2012 is connected with the base fin and emitter fin being subsequently formed, the second well region
2012 collectively form base area with base fin.
In the present embodiment, since the type of the fin bipolar junction transistor is positive-negative-positive, so the first well region 2011 is
P-well, the second well region 2012 are N trap.
In the present embodiment, doped with ion in first well region 2011 and the second well region 2012.
Wherein, doped with P-type ion in first well region 2011, such as B ion or In ion.In the present embodiment, first
The P-type ion adulterated in well region 2011 is B ion.The concentration for the P-type ion adulterated in first well region 2011 is 1E13atom/
cm2~1E14atom/cm2。
Wherein, in second well region 2012 doped with N-type ion, such as P (phosphorus) ion or As ion, in the present embodiment,
The N-type ion of middle doping is P ion in second well region 2012.The concentration for the N-type ion adulterated in second well region 2012 is
1E13atom/cm2~1E14atom/cm2。
Form the effect of the emitter fin 210, base fin 220 and collector fin 230 are as follows: the emitter fin 210 is used
In a part for forming subsequent transmission area, the base fin 220 is used to form a part of subsequent base area, the collector fin
230 are used to form collecting zone, and enable the technique and fin formula field effect transistor of the fin bipolar junction transistor to be formed
Technique be mutually compatible with.
In the present embodiment, the material of the emitter fin 210, base fin 220 and collector fin 230 is silicon；In other realities
It applies in example, the emitter fin 210, base fin 220 and collector fin 230 can choose other semiconductor materials.
The emitter fin 210 is respectively positioned on 2012 surface of the second well region with base fin 220, so that emitter fin 210 and base
Pole fin 220 is electrically connected with the second well region 2012；The collector fin 230 is located at 2011 surface of the first well region, so that current collection
Pole fin 230 is electrically connected with the first well region 2011.
The step of forming the emitter fin 210, base fin 220 and collector fin 230 are as follows: in 200 table of semiconductor substrate
Face forms fin material layer (not shown)；Patterned photoresist is formed in the fin material surface, it is described patterned
Photoresist defines the position of emitter fin 210, base fin 220 and collector fin 230；It is to cover with the patterned photoresist
Film etches the fin material layer until exposing 200 surface of semiconductor substrate, forms emitter fin 210,220 and of base fin
Collector fin 230.
In the present embodiment, in the section by Y3-Y4 axis in Fig. 4, with the quantity of the emitter fin 210 be 7,
The quantity of base fin 220 is 3, the quantity of collector fin 230 is 3 and passes through Y3- in actual process as an example, not representing
The number of Y4 axis emitter fin 210, base fin 220 and collector fin 230.In actual process, in cuing open by Y3-Y4 axis
In face, appropriate number of emitter fin 210, base fin 220 and collector fin 230 can be according to circumstances selected.
It should be noted that the amplification factor of fin bipolar junction transistor be by the total current of emitter fin 210 with
By the ratio of the total current of base fin 220, in order to enable the amplification factor of fin bipolar junction transistor is larger, passing through
In the section of Y3-Y4 axis, the quantity of emitter fin 210 is greater than the quantity of base fin 220.And for point of collector fin 230
Cloth needs to guarantee that the area of collecting zone is larger, therefore collector fin 230 is distributed in the peripheral region of semiconductor substrate 200, for
The quantity of collector fin 230, it is contemplated that the factor for reducing cost of manufacture selects collector in the section by Y3-Y4 axis
The quantity of fin 230 is less than the quantity of emitter fin 210.
200 surface of semiconductor substrate also has isolation structure 202, and the surface of isolation structure 202 is lower than emitter fin
210, the top surface of base fin 220 and collector fin 230, isolation structure 202 are used for electric isolation emitter fin 210, base stage
Fin 220 and collector fin 230.
With reference to Fig. 6, base epitaxial layer 221 is formed on 220 surface of base fin；In the 230 surface shape of collector fin
At collector epitaxial layer 231.
Form the effect of the base epitaxial layer 221 are as follows: since the area of base epitaxial layer 221 is larger, outside the base stage
Prolonging layer 221 can reduce base fin 220 and the subsequent resistance between the electrode that 221 surface of base epitaxial layer is formed.
Form the effect of the collector epitaxial layer 231 are as follows: since the area of collector epitaxial layer 231 is larger, the base
Pole epitaxial layer 221 can reduce collector fin 230 and the subsequent electricity between the electrode that 231 surface of collector epitaxial layer is formed
Resistance.
In the present embodiment, since the type for the fin bipolar junction transistor being used to form is positive-negative-positive, select institute
The material for stating base epitaxial layer 221 is silicon carbide, and the material of the collector epitaxial layer 231 is SiGe.In other embodiments
In, the material of base epitaxial layer 221 can be other materials, and the material of the collector epitaxial layer 231 can be other materials.
It can be initially formed base epitaxial layer 221, it is rear to form collector epitaxial layer 231；Collector extension can also be initially formed
Layer 231, it is rear to form base epitaxial layer 221.In the present embodiment, it is initially formed base epitaxial layer 221, forms collector epitaxial layer afterwards
231。
It when forming base epitaxial layer 221, needs to form the first barrier layer (not shown), first barrier layer exposes
Total amount of base fin 220, for each base fin 220, first barrier layer can expose each base fin 220
Area, can also expose the entire area of each base fin 220, in the present embodiment, for each base fin 220, institute
State the area that the first barrier layer exposes each base fin 220.In addition, first barrier layer covers collector fin 230
With emitter fin 210.First barrier layer is to protect collector fin 230 and emitter when forming base epitaxial layer 221
Fin 210.After forming base epitaxial layer 221, first barrier layer is removed.
In the present embodiment, the material on first barrier layer is silicon nitride, in other embodiments, first barrier layer
Material can be other materials.
The method for forming base epitaxial layer 221 is epitaxial growth technology.
In the present embodiment, the material of the base epitaxial layer 221 is silicon carbide, the tool of epitaxial growth base epitaxial layer 221
Body technology parameter are as follows: the gas used is SiH4、CH4And H2, SiH4Flow be 800sccm~1000sccm, CH4Flow be
800sccm~1000sccm, H2Flow be 50sccm~1000sccm, chamber pressure is 5mtorr~50mtorr, and temperature is
500 degrees Celsius~800 degrees Celsius.
When forming collector epitaxial layer 231, the second barrier layer (for diagram), the second barrier layer exposure are needed to form
Total amount of collector fin 230 out, for each collector fin 230, second barrier layer can expose each current collection
The area of pole fin 230, can also expose the entire area of each collector fin 230, in the present embodiment, for each collection
Electrode fin 230, second barrier layer expose the entire area of each collector fin 230.In addition, second barrier layer is covered
Lid base fin 220 and emitter fin 210.Second barrier layer is to protect base fin when forming collector epitaxial layer 231
220 and emitter fin 210.After forming collector epitaxial layer 231, second barrier layer is removed.
In the present embodiment, the material on second barrier layer is silicon nitride, in other embodiments, second barrier layer
Material can be other materials.
The method for forming collector epitaxial layer 231 is epitaxial growth technology.
In the present embodiment, the material of the collector epitaxial layer 231 is SiGe, epitaxial growth collector epitaxial layer 231
Specific process parameter are as follows: the gas used is GeH4、SiH4And H2, GeH4Flow be 800sccm~1000sccm, SiH4's
Flow is 800sccm~1000sccm, H2Flow be 50sccm~1000sccm, chamber pressure be 5mtorr~50mtorr,
Temperature is 500 degrees Celsius~800 degrees Celsius.
With reference to Fig. 7, the impure base fin ion 222 in the base fin 220 and base epitaxial layer 221,；In the current collection
Impure collecting electrode fin ion 232 in pole fin 230 and collector epitaxial layer 231.
The effect of the base fin ion 222 are as follows: reduce the resistance of base fin 220 and base epitaxial layer 221；The current collection
The effect of pole fin ion 232 are as follows: reduce the resistance of collector fin 230 and collector epitaxial layer 231.
The concentration of the base fin ion 222 is 5E14atom/cm2~1E15atom/cm2；The collector fin ion
232 concentration is 3E14atom/cm2~1E15atom/cm2。
In the present embodiment, first the impure base fin ion 222 in the base fin 220 and base epitaxial layer 221, then exists
Impure collecting electrode fin ion 232 in the collector fin 230 and collector epitaxial layer 231.In other embodiments, can first exist
Impure collecting electrode fin ion 232 in the collector fin 230 and collector epitaxial layer 231, then in the base fin 220 and base
Impure base fin ion 222 in pole epitaxial layer 221.In the present embodiment, using base fin ion implantation technology in the base fin
220 and base epitaxial layer 221 in impure base fin ion 222, the base fin ion 222 be N-type ion, such as P or As.One
In a specific embodiment, the technological parameter of the base fin ion implantation technology are as follows: the ion used injects energy for P ion
Amount is 6KeV~10KeV, implantation dosage 5E14atom/cm2~1E15atom/cm2, implant angle is 0 degree Celsius~7 Celsius
Degree, the implant angle are the angle between 200 normal direction of semiconductor substrate.
It should be noted that the base fin ion 222 is infused in entire base fin 220 and base stage in the present embodiment
In epitaxial layer 221；In other embodiments, base fin ion 222 can be injected in part base fin 220 and base epitaxial layer
In 221, during subsequent anneal processing, the base fin ion 222 is distributed in entire base fin 220 and base stage after spreading
In epitaxial layer 221.
In other embodiments, the base stage can be adulterated in situ while base epitaxial layer 221 described in epitaxial growth
Fin ion 222, during subsequent anneal processing, the base fin ion 222 is diffused into entire base fin 220.
In the present embodiment, using collector fin ion implantation technology in the collector fin 230 and collector epitaxial layer 231
Middle impure collecting electrode fin ion 232, the collector fin ion 232 is P-type ion, such as B or In.In a specific embodiment
In, the technological parameter of the collector fin ion implantation technology are as follows: the ion used for B ion, Implantation Energy be 3KeV~
5KeV, implantation dosage 3E14atom/cm2~1E15atom/cm2, implant angle is 0 degree Celsius~7 degrees Celsius, the injection
Angle is the angle between 200 normal direction of semiconductor substrate.
It should be noted that the collector fin ion 232 is infused in entire 230 He of collector fin in the present embodiment
In collector epitaxial layer 231；In other embodiments, the collector fin ion 232 can be injected in part collector fin 230
In part collector epitaxial layer 231, during subsequent anneal processing, the collector fin ion 232 is distributed after spreading
In entire collector fin 230 and collector epitaxial layer 231.
In other embodiments, the collection can be adulterated in situ while collector epitaxial layer 231 described in epitaxial growth
Electrode fin ion 232, during subsequent anneal processing, the collector fin ion 232 diffuses into entire collector fin
In 230.
It should also be noted that fin bipolar junction transistor has base area and collecting zone, in the present embodiment, second trap
Area 2012, the base fin 220 of impure base fin ion 222 and base epitaxial layer 221 constitute the base of fin bipolar junction transistor
Area, first well region 2011, collector fin 230 and collector epitaxial layer 231 and composition doped with collector fin ion 232
The collecting zone of fin bipolar junction transistor.
It should be noted that in the present invention, base epitaxial layer 221 can not be formed on 220 surface of base fin, but
The first base fin ion and the second base fin ion are adulterated in base fin 220, the second base fin ion is located at the top of base fin 220
Portion, the first base fin ion is located at the bottom of the second base fin ion, and the concentration of the second base fin ion is greater than the first base stage
The concentration of fin ion.In a specific embodiment, the concentration of the second base fin ion is 1E15atom/cm2~
3E15atom/cm2, the concentration of the first base fin ion is 5E14atom/cm2~1E15atom/cm2.Second base stage
The effect of fin ion and the first base fin ion are as follows: reduce the resistance of base fin 220, and form concentration ladder in base fin 220
Degree reduces base fin 220 and the subsequent contact berrier between the electrode that 220 surface of base fin is formed.
In the present invention, collector epitaxial layer 231 can not be formed on 230 surface of collector fin, but in collector fin
The first collector fin ion and the second collector fin ion are adulterated in 230, the second collector fin ion is located at collector fin 230
Top, the first collector fin ion is located at the bottom of the second collector fin ion, and the concentration of the second collector fin ion is greater than
The concentration of first collector fin.In a specific embodiment, the concentration of the second collector fin ion is 1E15atom/
cm2~3E15atom/cm2, the concentration of the first collector fin ion is 3E14atom/cm2~1E15atom/cm2.It is described
The effect of second collector fin ion and the first collector fin ion are as follows: reduce the resistance of collector fin 230, and in collector fin
Concentration gradient is formed in 230, reduces collector fin 230 and the subsequent contact between the electrode that 230 surface of collector fin is formed
Potential barrier.
With reference to Fig. 8, the first emitter ion is adulterated in the emitter fin 210, forms the first emitter ion area
211；The second emitter ion is adulterated in the emitter fin 210, forms the second emitter ion area 212, second hair
Emitter-base bandgap grading ion area 212 is located at the top of emitter fin 210, and the first emitter ion area 211 is located at the second emitter ion
The bottom in area 212, the concentration of the second emitter ion are greater than the concentration of the first emitter ion.
The effect of the first emitter ion are as follows: so that the emitter fin 210 doped with the first emitter ion and
PN junction is formed between two well regions 2012.The effect of the second emitter ion are as follows: so that forming concentration in emitter fin 210
Gradient reduces emitter fin 210 and the subsequent contact berrier between the electrode that 210 surface of emitter fin is formed.
In the present embodiment, due to without 210 surface of emitter fin formed emitter epitaxial layer, can effectively avoid because
The phenomenon that being connected caused by emitter epitaxial layer between emitter epitaxial layer is needed to form, is effectively avoided in emitter fin
The problem of reduction of electric current and fin bipolar junction transistor stability decline.
In addition, using the first emitter ion and the second emitter ion, second hair is formed in emitter fin 210
The concentration that emitter-base bandgap grading ion is located at the top of emitter fin 210 and the second emitter ion is greater than the concentration of the first emitter ion,
Due to forming concentration gradient in the emitter fin 210, the subsequent electricity formed in 210 top surface of emitter fin can reduce
Contact berrier between pole and emitter fin 210.
First emitter ion is adulterated in emitter fin 210 using the first emitter ion implantation technology, using second
Emitter ion implantation technology adulterates the second emitter ion in emitter fin 210, in the present embodiment, first carries out the second transmitting
Pole ion implantation technology, it is rear to carry out the first emitter ion implantation technology；In other embodiments, the first transmitting can first be carried out
Pole ion implantation technology, it is rear to carry out the second emitter ion implantation technology.
In the present embodiment, since the type for the fin bipolar junction transistor being used to form is positive-negative-positive, the first hair
Emitter-base bandgap grading ion and the second emitter ion are P-type ion, and such as B or In, the concentration of the first emitter ion is 3E14atom/
cm2~1E15atom/cm2, the concentration of the second emitter ion is 1E15atom/cm2~3E15atom/cm2。
In a specific embodiment, the technological parameter of the first emitter ion implantation technology are as follows: use from
Son is B ion, and Implantation Energy is 3KeV~5KeV, implantation dosage 3E14atom/cm2~1E15atom/cm2, implant angle is
0 degree Celsius~7 degrees Celsius；In another specific embodiment, the technological parameter of the first emitter ion implantation technology
Are as follows: the ion used is BF2Ion, Implantation Energy are 8KeV~15KeV, implantation dosage 3E14atom/cm2~1E15atom/
cm2, implant angle is 0 degree Celsius~7 degrees Celsius.The implant angle is the angle between 200 normal of semiconductor substrate.
In a specific embodiment, the technological parameter of the second emitter ion implantation technology are as follows: use from
Son is B ion, and Implantation Energy is 1KeV~3KeV, implantation dosage 1E15atom/cm2~3E15atom/cm2, implant angle is
0 degree Celsius~7 degrees Celsius；In another specific embodiment, the technological parameter of the second emitter ion implantation technology
Are as follows: the ion used is BF2Ion, Implantation Energy are 4KeV~7KeV, 1E15atom/cm2~3E15atom/cm2, injector angle
Degree is 0 degree Celsius~7 degrees Celsius.The implant angle is the angle between 200 normal of semiconductor substrate.
In the present embodiment, the first emitter ion is injected into the emitter of 212 bottom of the second emitter ion area
The whole volume in 210 region of fin；In other embodiments, the first emitter ion implanting is to the second emitter ion area
In the partial volume in 210 region of emitter fin of 212 bottoms.When the first emitter ion implanting to the second emitter ion area
It is subsequent after annealing in the partial volume in 210 region of emitter fin of 212 bottoms, the first emitter ion meeting
Diffusion, and be distributed in 210 region of emitter fin of 212 bottom of the second emitter ion area.
It should be noted that fin bipolar junction transistor has emitter region, in the present embodiment, the first emitter of doping from
The emitter fin 210 of son and the second emitter ion constitutes the emitter region of fin bipolar junction transistor.
It should be noted that in the present embodiment, the first impure base fin in the base fin 220 and base epitaxial layer 221
Ion, the impure collecting electrode fin ion in the collector fin 230 and collector epitaxial layer 231, then in the emitter fin
The first emitter ion and the second emitter ion are adulterated in 210；It in other embodiments, can be first in the emitter fin
The first emitter ion and the second emitter ion are adulterated in 210, then in the base fin 220 and base epitaxial layer 221
Impure base fin ion, the impure collecting electrode fin ion in the collector fin 230 and collector epitaxial layer 231.Alternatively, working as institute
State collector fin ion concentration it is identical with the first emitter ion when, can simultaneously impure collecting electrode fin ion and first hair
Emitter-base bandgap grading ion.Alternatively, can be mixed simultaneously when the first collector fin ion concentration is identical with the first emitter ion
Miscellaneous first collector fin ion and the first emitter ion；When the second collector fin ion concentration and the second emitter from
When the concentration of son is identical, the second collector fin ion and the second emitter ion can be adulterated simultaneously.
In the present embodiment, further includes: complete impure base fin ion, collector fin ion, the first emitter ion and the
After two emitter ions, each ion of doping is made annealing treatment together, to activate Doped ions.In other embodiments,
It may is that and made annealing treatment after completing impure base fin ion, and made annealing treatment after completing impure collecting electrode fin ion,
And it is made annealing treatment after completing the first emitter ion and the second emitter ion.
With reference to Fig. 9, in 210 top surface of emitter fin, 221 top surface of base epitaxial layer and collector epitaxial layer
231 top surfaces form electrode 240；
The electrode 240 is used for transmission electrical signal.
The material of the electrode 240 is metal, such as copper, aluminium or tungsten.In the present embodiment, the material of the electrode 240 is tungsten.
The formation process of the electrode 240 is depositing operation, such as physical vapour deposition (PVD), the formation work of the electrode 240
Skill can also be electroplating technology, and details are not described herein.
In conclusion technical solution of the present invention has the advantage that
The forming method of fin bipolar junction transistor provided by the invention is emitted using forming first in emitter fin
Pole ion and the second emitter ion, the second emitter ion are located at the top of emitter fin and the second emitter ion
Concentration is greater than the concentration of the first emitter ion, and the second emitter ion can reduce subsequent in emitter fin top surface
Contact berrier between the electrode and emitter fin of formation.
Further, when the quantity of the emitter fin is multiple, due to being not necessarily formed on emitter fin surface
Emitter epitaxial layer can effectively avoid causing to connect between the epitaxial layer of adjacent transmission pole because needing to form emitter epitaxial layer
The phenomenon that connecing, to effectively avoid through the total current reduction of emitter fin and fin bipolar junction transistor stability
The problem of decline.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (18)
1. a kind of forming method of fin bipolar junction transistor characterized by comprising
Semiconductor substrate is provided；
Collector fin, base fin and emitter fin, base fin, which are formed, in the semiconductor substrate surface is located at collector fin and hair
Between emitter-base bandgap grading fin, the collector fin, base fin and emitter fin are parallel to each other；
Base epitaxial layer is formed on the base fin surface；
Collector epitaxial layer is formed on collector fin surface；
The impure base fin ion in the base fin and base epitaxial layer；
The impure collecting electrode fin ion in the collector fin and collector epitaxial layer；
The first emitter ion and the second emitter ion are adulterated in the emitter fin, the second emitter ion is located at
The top of emitter fin, the first emitter ion are located at the bottom of the second emitter ion, and second emitter from
The concentration of son is greater than the concentration of the first emitter ion.
2. the forming method of fin bipolar junction transistor according to claim 1, which is characterized in that the base fin is enclosed
Around emitter fin, the collector fin surrounds the base fin.
3. the forming method of fin bipolar junction transistor according to claim 1, which is characterized in that when the base fin
Quantity be it is multiple when, the multiple base fin is parallel to each other；When the quantity of the collector fin is multiple, the multiple collection
Electrode fin is parallel to each other；When the quantity of the emitter fin is multiple, the multiple emitter fin is parallel to each other.
4. the forming method of fin bipolar junction transistor according to claim 1, which is characterized in that the fin is bipolar
Junction transistor is positive-negative-positive fin bipolar junction transistor.
5. the forming method of fin bipolar junction transistor according to claim 4, which is characterized in that second transmitting
The concentration of pole ion is 1E15atom/cm2~3E15atom/cm2；The concentration of the first emitter ion is 3E14atom/
cm2~1E15atom/cm2。
6. the forming method of fin bipolar junction transistor according to claim 4, which is characterized in that first transmitting
Pole ion and the second emitter ion are P-type ion.
7. the forming method of fin bipolar junction transistor according to claim 4, which is characterized in that the emitter
The technique that fin adulterates the first emitter ion is the first emitter ion implantation technology；To the second transmitting of emitter fin doping
The technique of pole ion is the second emitter ion implantation technology.
8. the forming method of fin bipolar junction transistor according to claim 7, which is characterized in that first transmitting
For the ion that pole ion implantation technology uses for B ion, Implantation Energy is 3KeV~5KeV, implantation dosage 3E14atom/cm2~
1E15atom/cm2, implant angle is 0 degree~7 degree.
9. the forming method of fin bipolar junction transistor according to claim 7, which is characterized in that first transmitting
The ion that pole ion implantation technology uses is BF2Ion, Implantation Energy are 8KeV~15KeV, implantation dosage 3E14atom/cm2
~1E15atom/cm2, implant angle is 0 degree~7 degree.
10. the forming method of fin bipolar junction transistor according to claim 7, which is characterized in that second hair
For the ion that emitter-base bandgap grading ion implantation technology uses for B ion, Implantation Energy is 1KeV~3KeV, implantation dosage 1E15atom/cm2
~3E15atom/cm2, implant angle is 0 degree~7 degree.
11. the forming method of fin bipolar junction transistor according to claim 7, which is characterized in that second hair
The ion that emitter-base bandgap grading ion implantation technology uses is BF2Ion, Implantation Energy are 4KeV~7KeV, implantation dosage 1E15atom/
cm2~3E15atom/cm2, implant angle is 0 degree~7 degree.
12. the forming method of fin bipolar junction transistor according to claim 4, which is characterized in that the collector
The material of epitaxial layer is SiGe；The material of the base epitaxial layer is silicon carbide.
13. the forming method of fin bipolar junction transistor according to claim 4, which is characterized in that the base fin
Ion is N-type ion；The collector fin ion is P-type ion.
14. the forming method of fin bipolar junction transistor according to claim 4, which is characterized in that the base fin
The concentration of ion is 5E14atom/cm2~1E15atom/cm2；The concentration of the collector fin ion is 3E14atom/cm2~
1E15atom/cm2。
15. the forming method of fin bipolar junction transistor according to claim 4, which is characterized in that the base stage
The technique of fin and base epitaxial layer impure base fin ion is base fin ion implantation technology；To the collector fin and collector
The technique of epitaxial layer impure collecting electrode fin ion is collector fin ion implantation technology.
16. the forming method of fin bipolar junction transistor according to claim 15, which is characterized in that the base fin
For the ion that ion implantation technology uses for P ion, Implantation Energy is 6KeV~10KeV, implantation dosage 5E14atom/cm2~
1E15atom/cm2, implant angle is 0 degree~7 degree.
17. the forming method of fin bipolar junction transistor according to claim 15, which is characterized in that the collector
For the ion that fin ion implantation technology uses for B ion, Implantation Energy is 3KeV~5KeV, implantation dosage 3E14atom/cm2~
1E15atom/cm2, implant angle is 0 degree~7 degree.
18. the forming method of fin bipolar junction transistor according to claim 1, which is characterized in that the semiconductor
Substrate includes the first well region and the second well region for being connected in the horizontal direction with the first well region, second well region and the first well region
The ionic type of middle doping is on the contrary, the collector fin is located at the first well region surface, and in collector fin ion and the first well region
The ionic type of doping is identical, and the base fin and the emitter fin are located at the second well region surface.
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| CN108807515B (en) * | 2017-05-05 | 2022-07-05 | 联华电子股份有限公司 | Bipolar transistor |
| CN109786246A (en) * | 2017-11-10 | 2019-05-21 | 中芯国际集成电路制造(上海)有限公司 | Fin bipolar junction transistor and forming method thereof |
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| CN101609812A (en) * | 2008-06-20 | 2009-12-23 | 台湾积体电路制造股份有限公司 | The formation method of electrostatic discharging element |
| CN103187438A (en) * | 2011-12-28 | 2013-07-03 | 台湾积体电路制造股份有限公司 | Fin-like BJT |
| CN103489863A (en) * | 2012-06-12 | 2014-01-01 | 台湾积体电路制造股份有限公司 | Homo-junction diode structures using fin field effect transistor processing |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101609812A (en) * | 2008-06-20 | 2009-12-23 | 台湾积体电路制造股份有限公司 | The formation method of electrostatic discharging element |
| CN103187438A (en) * | 2011-12-28 | 2013-07-03 | 台湾积体电路制造股份有限公司 | Fin-like BJT |
| CN103489863A (en) * | 2012-06-12 | 2014-01-01 | 台湾积体电路制造股份有限公司 | Homo-junction diode structures using fin field effect transistor processing |
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