CN106409890A - Method for forming fin-type bipolar junction transistor - Google Patents
Method for forming fin-type bipolar junction transistor Download PDFInfo
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- CN106409890A CN106409890A CN201510451932.2A CN201510451932A CN106409890A CN 106409890 A CN106409890 A CN 106409890A CN 201510451932 A CN201510451932 A CN 201510451932A CN 106409890 A CN106409890 A CN 106409890A
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- 238000000034 method Methods 0.000 title claims abstract description 56
- 239000004065 semiconductor Substances 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000005516 engineering process Methods 0.000 claims description 38
- 238000002513 implantation Methods 0.000 claims description 35
- 238000005468 ion implantation Methods 0.000 claims description 30
- 239000000463 material Substances 0.000 claims description 28
- 239000007943 implant Substances 0.000 claims description 22
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 8
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 3
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- 230000004888 barrier function Effects 0.000 description 18
- 230000008569 process Effects 0.000 description 10
- 238000002955 isolation Methods 0.000 description 7
- 238000000137 annealing Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000005669 field effect Effects 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 229910052986 germanium hydride Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6625—Lateral transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
- H01L29/0808—Emitter regions of bipolar transistors of lateral transistors
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Abstract
A method for forming a fin-type bipolar junction transistor comprises the steps of providing a semiconductor substrate; forming collector fins, base fins and emitter fins on the surface of the semiconductor substrate, the base fins being located between the collector fins and the emitter fins, and the collector fins, the base fins and the emitter fins being parallel to one another; forming a base epitaxial layer on the surface of each base fin; forming a collector epitaxial layer on the surface of each collector fin; doping base fin ions in the base fins and the base epitaxial layers; doping collector fin ions in the collector fins and the collector epitaxial layers; and doping first and second emitter ions in the emitter fins, the second emitter ions being located at the top of the emitter fins, the first emitter ions being located at the bottom of the second emitter ions, and the second emitter ions having a concentration greater than that of the first emitter ions. The method of forming the fin-type bipolar junction transistor improves the performance of the fin-type bipolar junction transistor.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, to a kind of formation of fin bipolar junction transistor
Method.
Background technology
Bipolar junction transistor (Bipolar Junction Transistor, BJT) is also called transistor,
It is closely adjacent to each other by two and back-to-back PN junction is bonded, and is divided into two kinds of groups of PNP and NPN
Close structure.Bipolar junction transistor has three poles：Colelctor electrode, emitter stage and base stage.Dipole is brilliant
Body pipe plays the role of to amplify signal, relies primarily on emitter current and can reach collecting zone by base transport
And realize.Bipolar transistor because can amplify signal, preferable Power Control, high speed operation with
And endurance, thus be widely used.
MOS transistor is one of most important element in modern integrated circuits.MOS transistor passes through to apply
Voltage and adjust and switching signal produced by the electric current of raceway groove.
Generally, bipolar junction transistor and MOS transistor integrate composition semiconductor devices.
With the development of semiconductor technology, the control to channel current of the MOS transistor of traditional plane formula
Ability dies down, and causes serious leakage current.Fin formula field effect transistor (Fin FET) is a kind of emerging
Multi-gate device, it generally comprises the fin protruding from semiconductor substrate surface, fin described in covering part
Top and the grid structure of side wall, the source region in the fin of grid structure side and grid structure opposite side
Drain region in fin.Fin formula field effect transistor replaces because can significantly improve circuit and reduce leakage current
MOS transistor for plane formula.
So that preparing the technique of bipolar junction transistor and preparing the technique phase of fin formula field effect transistor
Compatibility, in prior art using preparation fin bipolar junction transistor and by fin bipolar junction transistor and
Fin formula field effect transistor integrates.
But, reduce further with characteristic size, the fin bipolar junction transistor that prior art is formed
Poor-performing.
Content of the invention
The problem that the present invention solves is to provide a kind of forming method of fin bipolar junction transistor, improves fin
The performance of formula bipolar junction transistor.
For solving the above problems, the present invention provides a kind of forming method of fin bipolar junction transistor, bag
Include：Semiconductor substrate is provided；Form colelctor electrode fin, base fin and transmitting in described semiconductor substrate surface
Pole fin, base fin is located between colelctor electrode fin and emitter stage fin, described colelctor electrode fin, base fin and transmitting
Pole fin is parallel to each other；Form base epitaxial layer on described base fin surface；In described colelctor electrode fin surface shape
Become collector epitaxial layer；Impure base fin ion in described base fin and base epitaxial layer；In described collection
Impure collecting electrode fin ion in electrode fin and collector epitaxial layer；Described emitter stage fin adulterates first
Emitter-base bandgap grading ion and the second emitter stage ion, described second emitter stage ion is located at the top of emitter stage fin, institute
State the bottom that the first emitter stage ion is located at the second emitter stage ion, and described second emitter stage ion is dense
Degree is more than the concentration of the first emitter stage ion.
Optionally, around emitter stage fin, described colelctor electrode fin is around described base fin for described base fin.
Optionally, when the quantity of described base fin is multiple, the plurality of base fin is parallel to each other；When
When the quantity of described colelctor electrode fin is multiple, the plurality of colelctor electrode fin is parallel to each other；When described emitter stage
When the quantity of fin is multiple, the plurality of emitter stage fin is parallel to each other.
Optionally, described fin bipolar junction transistor is positive-negative-positive fin bipolar junction transistor.
Optionally, the concentration of described second emitter stage ion is 1E15atom/cm2～3E15atom/cm2；Institute
The concentration stating the first emitter stage ion is 3E14atom/cm2～1E15atom/cm2.
Optionally, described first emitter stage ion and the second emitter stage ion are p-type ion.
Optionally, the technique to described emitter stage fin doping the first emitter stage ion is the first emitter stage ion
Injection technology；Technique to described emitter stage fin doping the second emitter stage ion is the second emitter stage ion note
Enter technique.
Optionally, the ion that described first emitter stage ion implantation technology adopts is B ion, and Implantation Energy is
3KeV～5KeV, implantation dosage is 3E14atom/cm2～1E15atom/cm2, implant angle be 0 degree～7 degree.
Optionally, the ion that described first emitter stage ion implantation technology adopts is BF2Ion, Implantation Energy
For 8KeV～15KeV, implantation dosage is 3E14atom/cm2～1E15atom/cm2, implant angle is 0 degree～7
Degree.
Optionally, the ion that described second emitter stage ion implantation technology adopts is B ion, and Implantation Energy is
1KeV～3KeV, implantation dosage is 1E15atom/cm2～3E15atom/cm2, implant angle be 0 degree～7 degree.
Optionally, the ion that described second emitter stage ion implantation technology adopts is BF2Ion, Implantation Energy
For 4KeV～7KeV, implantation dosage is 1E15atom/cm2～3E15atom/cm2, implant angle is 0 degree～7
Degree.
Optionally, the material of described collector epitaxial layer is SiGe；The material of described base epitaxial layer is
Carborundum.
Optionally, described base fin ion is N-type ion；Described colelctor electrode fin ion is p-type ion.
Optionally, the concentration of described base fin ion is 5E14atom/cm2～1E15atom/cm2；Described collection
The concentration of electrode fin ion is 3E14atom/cm2～1E15atom/cm2.
Optionally, be base fin to the technique of described base fin and base epitaxial layer impure base fin ion from
Sub- injection technology；Technique to described colelctor electrode fin and collector epitaxial layer impure collecting electrode fin ion is collection
Electrode fin ion implantation technology.
Optionally, the ion that described base fin ion implantation technology adopts is P ion, and Implantation Energy is
6KeV～10KeV, implantation dosage is 5E14atom/cm2～1E15atom/cm2, implant angle be 0 degree Celsius
～7 degrees Celsius.
Optionally, the ion that described colelctor electrode fin ion implantation technology adopts is B ion, and Implantation Energy is
3KeV～5KeV, implantation dosage is 3E14atom/cm2～1E15atom/cm2, implant angle be 0 degree Celsius
～7 degrees Celsius.
Optionally, described Semiconductor substrate is included the first well region and is connected in the horizontal direction with the first well region
The second well region, in described second well region and the first well region, the ionic type of doping is contrary, described colelctor electrode
Fin is located at the first well region surface, and colelctor electrode fin ion is identical with the ionic type of doping in the first well region,
Described base fin and described emitter stage fin are located at the second well region surface.
Compared with prior art, technical scheme has advantages below：
The forming method of the fin bipolar junction transistor that the present invention provides, forms using in emitter stage fin
First emitter stage ion and the second emitter stage ion, described second emitter stage ion is located at the top of emitter stage fin
The concentration of portion and the second emitter stage ion be more than the first emitter stage ion concentration, described second emitter stage from
Son can reduce follow-up contact gesture between the electrode that emitter stage fin top surface is formed and emitter stage fin
Build.
Further, when the quantity of described emitter stage fin is multiple, due on described emitter stage fin surface
Not necessarily form emitter epitaxial layer, can effectively avoid leading to phase because needing to form emitter epitaxial layer
The phenomenon connecting between adjacent emitter epitaxial layer, thus effectively avoid the total current by emitter stage fin
Reduction and the problem of fin bipolar junction transistor stability decline.
Brief description
Fig. 1 to Fig. 3 is the schematic diagram of fin bipolar junction transistor forming process in one embodiment of the invention；
Fig. 4 to Fig. 9 is the signal of fin bipolar junction transistor forming process in another embodiment of the present invention
Figure.
Specific embodiment
Reduce further with characteristic size, the performance of the fin bipolar junction transistor that prior art is formed
Poor.
One embodiment of the invention provides a kind of forming method of fin bipolar junction transistor, referring to figs. 1 to figure
3, Fig. 2 is the profile along Y1-Y2 axis in Fig. 1, and Fig. 3 is the schematic diagram being formed on the basis of Fig. 2,
Including：Semiconductor substrate 100 is provided；Form multiple parallel transmittings on described Semiconductor substrate 100 surface
Pole fin 110, multiple parallel base fin 120 and multiple parallel colelctor electrode fins 130, the plurality of base fin
120 around the plurality of emitter stage fin 110, and the plurality of colelctor electrode fin 130 is around the plurality of base fin
120, and emitter stage fin 110, base fin 120 and colelctor electrode fin 130 are parallel to each other；In described emitter stage fin
110 surfaces form emitter epitaxial layer 111；Form base epitaxial layer 121 on described base fin 120 surface；
Form collector epitaxial layer 131 on described colelctor electrode fin 130 surface.
Described Semiconductor substrate 100 includes well region 101, described well region 101 include the first well region 1011 and with
The second well region 1012 that first well region 1011 is connected in the horizontal direction, described 130 the first traps of colelctor electrode fin
Area 1011 surface, described base fin 120 and emitter stage fin 110 are located at the second well region 1012 surface.Described half
Conductor substrate 100 surface also has an isolation structure 102, the surface of isolation structure 102 be less than emitter stage fin 110,
Base fin 120 and the top surface of colelctor electrode fin 130, isolation structure 102 is used for electric isolation emitter stage fin
110th, base fin 120 and colelctor electrode fin 130.
Because the area of described emitter epitaxial layer 111 is larger, described emitter epitaxial layer 111 can reduce
Follow-up resistance between the electrode that emitter epitaxial layer 111 top surface is formed and emitter stage fin 110.When
When described fin bipolar junction transistor is positive-negative-positive fin bipolar junction transistor, described emitter stage extension
The material of layer 111 is SiGe.
Research finds, the fin bipolar junction transistor that said method is formed still has Performance And Reliability
The reason difference, is：
Described emitter stage fin is located at the central area of Semiconductor substrate, serves as a contrast in semiconductor with respect to emitter stage fin
The position at bottom, base fin and colelctor electrode fin are located at the region of Semiconductor substrate periphery.Formed outside emitter stage
During prolonging layer, base epitaxial layer and collector epitaxial layer, for forming emitter epitaxial layer, base stage
The distribution of each precursor gas of epitaxial layer and collector epitaxial layer all has the characteristics that common：In semiconductor lining
Precursor gas volume density above the central area of bottom is more than the presoma above Semiconductor substrate outer peripheral areas
Gas density, thus formed emitter epitaxial layer speed larger so that adjacent emitter epitaxial layer is held very much
Easily it is connected with each other.On the other hand, due to the emitter stage fin in the section of Y1-Y2 axis in Fig. 1
Quantity is more, leads to adjacent transmission pole epitaxial layer to occur the probability connecting larger, as long as there is phase at one
The phenomenon that adjacent emitter epitaxial layer connects, will accelerate to form the speed of emitter epitaxial layer, may lead to
Whole emitter epitaxial layer connects.Another aspect, when described fin bipolar junction transistor is positive-negative-positive fin
During formula bipolar junction transistor, the material of emitter epitaxial layer is SiGe, and SiGe is given birth in different directions
Long speed is variant, and emitter epitaxial layer is six in the section shape perpendicular to emitter stage fin sidewall direction
Angular so that adjacent emitter epitaxial layer is easy to be connected with each other.Adjacent transmission pole epitaxial layer connects leads
Show lower drawback：So that being reduced by the total current of emitter stage fin；Different fin dipoles can not be controlled
The situation that in transistor, emitter epitaxial layer connects, causes the stability of fin bipolar junction transistor performance
It is deteriorated.
On this basis, another embodiment of the present invention provides a kind of formation side of fin bipolar junction transistor
Method, including：Semiconductor substrate is provided；Form colelctor electrode fin, base fin in described semiconductor substrate surface
With multiple parallel emitter stage fins, base fin be located between colelctor electrode fin and the plurality of emitter stage fin, institute
State colelctor electrode fin, base fin and emitter stage fin parallel to each other；Form base stage extension on described base fin surface
Layer；Form collector epitaxial layer on described colelctor electrode fin surface；In described base fin and base epitaxial layer
Impure base fin ion；Impure collecting electrode fin ion in described colelctor electrode fin and collector epitaxial layer；?
Adulterate in described emitter stage fin the first emitter stage ion and the second emitter stage ion, described second emitter stage from
Son is located at the top of emitter stage fin, and described first emitter stage ion is located at the bottom of the second emitter stage ion,
And the concentration of described second emitter stage ion is more than the concentration of the first emitter stage ion.
Compare previous embodiment, due to using forming the first emitter stage ion and second in emitter stage fin
Emitter-base bandgap grading ion, described second emitter stage ion is located at the top of emitter stage fin and the dense of the second emitter stage ion
More than the concentration of the first emitter stage ion, described second emitter stage ion can reduce subsequently in emitter stage degree
Contact berrier between the electrode of fin top surface formation and emitter stage fin.Further, since in described transmitting
Pole fin surface not necessarily forms emitter epitaxial layer, can effectively avoid because needing to form emitter epitaxial layer
And lead to the phenomenon connecting between the epitaxial layer of adjacent transmission pole, thus effectively avoiding by emitter stage fin
Total current reduce and fin bipolar junction transistor stability decline problem.
Understandable for enabling the above objects, features and advantages of the present invention to become apparent from, below in conjunction with the accompanying drawings
The specific embodiment of the present invention is described in detail.
In conjunction with reference to Fig. 4 and Fig. 5, wherein, Fig. 5 is the profile along Y3-Y4 axis in Fig. 4,
Semiconductor substrate 200 is provided；Form colelctor electrode fin 230, base fin on described Semiconductor substrate 200 surface
220 and emitter stage fin 210, base fin 220 is located between colelctor electrode fin 230 and emitter stage fin 210, institute
State emitter stage fin 210, base fin 220 and colelctor electrode fin 230 parallel to each other.
The quantity of described base fin 220 is one or more；The quantity of described colelctor electrode fin 230 is one
Or multiple, the quantity of described emitter stage fin 210 is one or more.Quantity when described base fin 220
For multiple when, each base fin 220 is parallel to each other；When the quantity of described colelctor electrode fin 230 is multiple,
Each colelctor electrode fin 230 is parallel to each other, when the quantity of described emitter stage fin 210 is multiple, each
Emitter-base bandgap grading fin 210 is parallel to each other.
In the present embodiment, the arrangement of described emitter stage fin 210, base fin 220 and colelctor electrode fin 230 is:
, around emitter stage fin 210, colelctor electrode fin 230 is around base fin 220, the mode of this arrangement for base fin 220
Enable colelctor electrode fin 210 from all directions collected current, by the total current of colelctor electrode fin 210 relatively
Greatly, reduce leakage current；In another embodiment, described emitter stage fin 210, base fin 220 and current collection
The arrangement of pole fin 230 is：Base fin 220 is only positioned at the side of emitter stage fin 210, colelctor electrode fin 230
Be only positioned at the side of base fin 220, base fin 220 be located at emitter stage fin 210 and emitter stage fin 210 it
Between.
In the present embodiment, taking form positive-negative-positive fin bipolar transistor as a example illustrate, in other embodiments
In it is also possible to formed NPN type fin bipolar transistor.
Described Semiconductor substrate 200 provides technique platform for being subsequently formed fin bipolar junction transistor.
Described Semiconductor substrate 200 can be monocrystalline silicon, polysilicon or non-crystalline silicon；Semiconductor substrate 200
Can also be the semi-conducting materials such as silicon, germanium, SiGe, GaAs；Described Semiconductor substrate 200 is permissible
It is body material or composite construction, such as silicon-on-insulator；Described Semiconductor substrate 200 is acceptable
It is other semi-conducting material, no longer illustrate one by one here.In the present embodiment, described Semiconductor substrate 200
Material be silicon.
There is in described Semiconductor substrate 200 well region 201, described well region 201 include the first well region 2011 and with
The second well region 2012 that first well region 2011 is connected in the horizontal direction, described second well region 2012 and first
In well region 2011, the ionic type of doping is contrary.
The acting as of described first well region 2011 and the second well region 2012：First well region 2011 be subsequently formed
Colelctor electrode fin be connected, collectively form collecting zone；Second well region 2012 and the base fin being subsequently formed and send out
Emitter-base bandgap grading fin is connected, and the second well region 2012 collectively forms base with base fin.
In the present embodiment, because the type of described fin bipolar junction transistor is positive-negative-positive, so the first trap
Area 2011 is p-well, and the second well region 2012 is N trap.
In the present embodiment, doped with ion in described first well region 2011 and the second well region 2012.
Wherein, doped with p-type ion in described first well region 2011, such as B ion or In ion.This enforcement
In example, in the first well region 2011, the p-type ion of doping is B ion.In first well region 2011 doping p-type from
The concentration of son is 1E13atom/cm2～1E14atom/cm2.
Wherein, doped with N-type ion in described second well region 2012, such as P (phosphorus) ion or As ion,
In the present embodiment, in the second well region 2012, the N-type ion of middle doping is P ion.Mix in second well region 2012
The concentration of miscellaneous N-type ion is 1E13atom/cm2～1E14atom/cm2.
Form acting as of described emitter stage fin 210, base fin 220 and colelctor electrode fin 230：Described emitter stage
Fin 210 is used for forming the part in subsequent transmission area, and described base fin 220 is used for forming the one of follow-up base
Part, described colelctor electrode fin 230 is used for being formed collecting zone, and makes the fin bipolar junction transistor being formed
Technique can be mutually compatible with the technique of fin formula field effect transistor.
In the present embodiment, the material of described emitter stage fin 210, base fin 220 and colelctor electrode fin 230 is silicon；
In other embodiments, described emitter stage fin 210, base fin 220 and colelctor electrode fin 230 can select it
Its semi-conducting material.
Described emitter stage fin 210 and base fin 220 are respectively positioned on the second well region 2012 surface so that emitter stage
Fin 210 and base fin 220 are all electrically connected with the second well region 2012；Described colelctor electrode fin 230 is located at the
One well region 2011 surface is so that colelctor electrode fin 230 is electrically connected with the first well region 2011.
The step forming described emitter stage fin 210, base fin 220 and colelctor electrode fin 230 is：In semiconductor
Substrate 200 surface forms fin material layer (not shown)；Form patterning in described fin material surface
Photoresist, the photoresist of described patterning defines emitter stage fin 210, base fin 220 and colelctor electrode fin
230 position；With the photoresist of described patterning as mask, etch described fin material layer until exposing
Semiconductor substrate 200 surface, forms emitter stage fin 210, base fin 220 and colelctor electrode fin 230.
In the present embodiment, in the section of Y3-Y4 axis in by Fig. 4, with described emitter stage fin 210
Quantity be 7, the quantity of base fin 220 be 3, the quantity of colelctor electrode fin 230 be 3 conducts
Example, does not represent and passes through Y3-Y4 axis emitter stage fin 210, base fin 220 and collection in actual process
The number of electrode fin 230.In actual process, in the section by Y3-Y4 axis, can be according to feelings
Condition selects appropriate number of emitter stage fin 210, base fin 220 and colelctor electrode fin 230.
It should be noted that the multiplication factor of fin bipolar junction transistor is by emitter stage fin 210
Total current with by the ratio of the total current of base fin 220 so that fin bipolar junction transistor
Multiplication factor is larger, and in the section by Y3-Y4 axis, the quantity of emitter stage fin 210 is more than base stage
The quantity of fin 220.And the distribution for colelctor electrode fin 230, need to ensure that the area of collecting zone is larger,
Therefore colelctor electrode fin 230 is distributed in the outer peripheral areas of Semiconductor substrate 200, for colelctor electrode fin 230
Quantity, it is contemplated that reducing the factor of cost of manufacture, in the section by Y3-Y4 axis, selects current collection
The quantity of pole fin 230 is less than the quantity of emitter stage fin 210.
Described Semiconductor substrate 200 surface also has isolation structure 202, and the surface of isolation structure 202 is less than to be sent out
The top surface of emitter-base bandgap grading fin 210, base fin 220 and colelctor electrode fin 230, isolation structure 202 be used for electricity every
From emitter stage fin 210, base fin 220 and colelctor electrode fin 230.
With reference to Fig. 6, form base epitaxial layer 221 on described base fin 220 surface；In described colelctor electrode fin
230 surfaces form collector epitaxial layer 231.
Form acting as of described base epitaxial layer 221：Because the area of base epitaxial layer 221 is larger,
Described base epitaxial layer 221 can reduce base fin 220 and subsequently be formed on base epitaxial layer 221 surface
Electrode between resistance.
Form acting as of described collector epitaxial layer 231：Due to collector epitaxial layer 231 area relatively
Greatly, described base epitaxial layer 221 can reduce colelctor electrode fin 230 with follow-up in collector epitaxial layer 231
Resistance between the electrode that surface is formed.
In the present embodiment, because the type of the fin bipolar junction transistor for being formed is positive-negative-positive, because
This, the material selecting described base epitaxial layer 221 is carborundum, the material of described collector epitaxial layer 231
Expect for SiGe.In other embodiments, the material of base epitaxial layer 221 can be other materials, institute
The material stating collector epitaxial layer 231 can be other materials.
Base epitaxial layer 221 can be initially formed, form collector epitaxial layer 231 afterwards；Collection can also be initially formed
Electrode epitaxial layer 231, forms base epitaxial layer 221 afterwards.In the present embodiment, it is initially formed base epitaxial layer 221,
Form collector epitaxial layer 231 afterwards.
When forming base epitaxial layer 221, need to be formed the first barrier layer (not shown), described first resistance
Barrier exposes total amount of base fin 220, and for each base fin 220, described first barrier layer can
To expose the area of each base fin 220 it is also possible to expose the whole of each base fin 220
Area, in the present embodiment, for each base fin 220, described first barrier layer exposes each base fin
220 area.In addition, described first barrier layer covers colelctor electrode fin 230 and emitter stage fin 210.
Described first barrier layer is in order to protection colelctor electrode fin 230 and emitter stage fin when forming base epitaxial layer 221
210.After forming base epitaxial layer 221, described first barrier layer is removed.
In the present embodiment, the material on described first barrier layer is silicon nitride, in other embodiments, described
The material on the first barrier layer can be other materials.
The method forming base epitaxial layer 221 is epitaxial growth technology.
In the present embodiment, the material of described base epitaxial layer 221 is carborundum, epitaxial growth base stage extension
Layer 221 specific process parameter be：Using gas be SiH4、CH4And H2, SiH4Flow be
800sccm～1000sccm, CH4Flow be 800sccm～1000sccm, H2Flow be
50sccm～1000sccm, chamber pressure is 5mtorr～50mtorr, and temperature is Celsius for 500 degrees Celsius～800
Degree.
When forming collector epitaxial layer 231, need to be formed the second barrier layer (for diagram), described second
Barrier layer exposes total amount of colelctor electrode fin 230, for each colelctor electrode fin 230, described second resistance
Barrier can expose the area of each colelctor electrode fin 230 it is also possible to expose each colelctor electrode fin
230 entire area, in the present embodiment, for each colelctor electrode fin 230, described second barrier layer exposes
Go out the entire area of each colelctor electrode fin 230.In addition, described second barrier layer covers base fin 220 He
Emitter stage fin 210.Described second barrier layer in order to protect base fin when forming collector epitaxial layer 231
220 and emitter stage fin 210.After forming collector epitaxial layer 231, described second barrier layer is removed.
In the present embodiment, the material on described second barrier layer is silicon nitride, in other embodiments, described
The material on the second barrier layer can be other materials.
The method forming collector epitaxial layer 231 is epitaxial growth technology.
In the present embodiment, the material of described collector epitaxial layer 231 is SiGe, epitaxial growth colelctor electrode
The specific process parameter of epitaxial layer 231 is：Using gas be GeH4、SiH4And H2, GeH4Stream
Measure as 800sccm～1000sccm, SiH4Flow be 800sccm～1000sccm, H2Flow be
50sccm～1000sccm, chamber pressure is 5mtorr～50mtorr, and temperature is Celsius for 500 degrees Celsius～800
Degree.
Reference Fig. 7, impure base fin ion 222 in described base fin 220 and base epitaxial layer 221,；
Impure collecting electrode fin ion 232 in described colelctor electrode fin 230 and collector epitaxial layer 231.
The acting as of described base fin ion 222：Reduce the electricity of base fin 220 and base epitaxial layer 221
Resistance；The acting as of described colelctor electrode fin ion 232：Reduce colelctor electrode fin 230 and collector epitaxial layer 231
Resistance.
The concentration of described base fin ion 222 is 5E14atom/cm2～1E15atom/cm2；Described colelctor electrode
The concentration of fin ion 232 is 3E14atom/cm2～1E15atom/cm2.
In the present embodiment, first impure base fin ion in described base fin 220 and base epitaxial layer 221
222, then impure collecting electrode fin ion 232 in described colelctor electrode fin 230 and collector epitaxial layer 231.
In other embodiments, can first adulterate in described colelctor electrode fin 230 and collector epitaxial layer 231 collection
Electrode fin ion 232, then impure base fin ion in described base fin 220 and base epitaxial layer 221
222.In the present embodiment, using base fin ion implantation technology in described base fin 220 and base epitaxial layer
Impure base fin ion 222 in 221, described base fin ion 222 is N-type ion, such as P or As.
In a specific embodiment, the technological parameter of described base fin ion implantation technology is：Using from
Son is P ion, and Implantation Energy is 6KeV～10KeV, and implantation dosage is
5E14atom/cm2～1E15atom/cm2, implant angle be 0 degree Celsius～7 degrees Celsius, described implant angle
It is the angle and Semiconductor substrate 200 normal direction between.
It should be noted that in the present embodiment, described base fin ion 222 is infused in whole base fin
220 and base epitaxial layer 221 in；In other embodiments, base fin ion 222 can be infused in part
In base fin 220 and base epitaxial layer 221, subsequent anneal process during, described base fin from
It is distributed in whole base fin 220 and base epitaxial layer 221 after son 222 diffusion.
In other embodiments, can adulterate in situ while base epitaxial layer described in epitaxial growth 221
Described base fin ion 222, during subsequent anneal is processed, described base fin ion 222 diffuses into
Enter in whole base fin 220.
In the present embodiment, using colelctor electrode fin ion implantation technology in described colelctor electrode fin 230 and colelctor electrode
Impure collecting electrode fin ion 232 in epitaxial layer 231, described colelctor electrode fin ion 232 is p-type ion, such as
B or In.In a specific embodiment, the technological parameter of described colelctor electrode fin ion implantation technology is：
Using ion be B ion, Implantation Energy is 3KeV～5KeV, and implantation dosage is
3E14atom/cm2～1E15atom/cm2, implant angle be 0 degree Celsius～7 degrees Celsius, described implant angle
It is the angle and Semiconductor substrate 200 normal direction between.
It should be noted that in the present embodiment, described colelctor electrode fin ion 232 is infused in whole current collection
In pole fin 230 and collector epitaxial layer 231；In other embodiments, described colelctor electrode fin ion 232
Can be infused in part colelctor electrode fin 230 and part collector epitaxial layer 231, process in subsequent anneal
During, it is distributed in whole colelctor electrode fin 230 and colelctor electrode after described colelctor electrode fin ion 232 diffusion
In epitaxial layer 231.
In other embodiments, original position can mix while collector epitaxial layer described in epitaxial growth 231
Miscellaneous described colelctor electrode fin ion 232, during subsequent anneal is processed, described colelctor electrode fin ion 232
Diffuse in whole colelctor electrode fin 230.
Another it should be noted that, fin bipolar junction transistor has base and collecting zone, in the present embodiment,
Described second well region 2012, the base fin 220 of impure base fin ion 222 and base epitaxial layer 221 structure
Become the base of fin bipolar junction transistor, described first well region 2011, doped with colelctor electrode fin ion 232
Colelctor electrode fin 230 and collector epitaxial layer 231 and the collecting zone constituting fin bipolar junction transistor.
It should be noted that in the present invention, base epitaxial layer can not formed on base fin 220 surface
221, but adulterate in base fin 220 first base fin ion and the second base fin ion, the second base stage
Fin ion is located at the top of base fin 220, and the first base fin ion is located at the bottom of the second base fin ion,
And second base fin ion concentration be more than the first base fin ion concentration.In a specific embodiment
In, the concentration of described second base fin ion is 1E15atom/cm2～3E15atom/cm2, described first base
The concentration of pole fin ion is 5E14atom/cm2～1E15atom/cm2.Described second base fin ion and first
The acting as of base fin ion：Reduce the resistance of base fin 220, and form concentration in base fin 220
Gradient, reduces base fin 220 and follow-up contact berrier between the electrode that base fin 220 surface is formed.
In the present invention, collector epitaxial layer 231 can not formed on colelctor electrode fin 230 surface, but
Adulterate in colelctor electrode fin 230 first colelctor electrode fin ion and the second colelctor electrode fin ion, the second colelctor electrode fin
Ion is located at the top of colelctor electrode fin 230, and the first colelctor electrode fin ion is located at the second colelctor electrode fin ion
Bottom, and the concentration of the second colelctor electrode fin ion is more than the concentration of the first colelctor electrode fin.Specific at one
In embodiment, the concentration of described second colelctor electrode fin ion is 1E15atom/cm2～3E15atom/cm2, institute
The concentration stating the first colelctor electrode fin ion is 3E14atom/cm2～1E15atom/cm2.Described second colelctor electrode
The acting as of fin ion and the first colelctor electrode fin ion：Reduce the resistance of colelctor electrode fin 230, and in current collection
Form concentration gradient in pole fin 230, reduce colelctor electrode fin 230 and subsequently in colelctor electrode fin 230 surface shape
Contact berrier between the electrode becoming.
With reference to Fig. 8, adulterate in described emitter stage fin 210 first emitter stage ion, forms the first emitter stage
Ion area 211；Adulterate in described emitter stage fin 210 second emitter stage ion, formed the second emitter stage from
Sub-district 212, described second emitter stage ion area 212 is located at the top of emitter stage fin 210, described first
Emitter-base bandgap grading ion area 211 is located at the bottom in the second emitter stage ion area 212, described second emitter stage ion
Concentration is more than the concentration of the first emitter stage ion.
The acting as of described first emitter stage ion：So that the emitter stage fin doped with the first emitter stage ion
210 and second form PN junction between well region 2012.The acting as of described second emitter stage ion：So that
Form concentration gradient in emitter stage fin 210, reduce emitter stage fin 210 and subsequently in emitter stage fin 210
Contact berrier between the electrode that surface is formed.
In the present embodiment, due to emitter epitaxial layer, Ke Yiyou need not be formed on emitter stage fin 210 surface
The phenomenon connecting between the emitter epitaxial layer avoiding leading to because needing to form emitter epitaxial layer of effect,
Effectively avoid the reduction of electric current in emitter stage fin and fin bipolar junction transistor stability declines
Problem.
In addition, using forming the first emitter stage ion and the second emitter stage ion in emitter stage fin 210,
The concentration at top and the second emitter stage ion that described second emitter stage ion is located at emitter stage fin 210 is more than
The concentration of the first emitter stage ion, due to forming concentration gradient in described emitter stage fin 210, can drop
Low follow-up contact berrier between the electrode that emitter stage fin 210 top surface is formed and emitter stage fin 210.
Adulterated in emitter stage fin 210 first emitter stage ion using the first emitter stage ion implantation technology,
Adulterated in emitter stage fin 210 second emitter stage ion using the second emitter stage ion implantation technology, this reality
Apply in example, first carry out the second emitter stage ion implantation technology, after carry out the first emitter stage ion implantation technology；
In other embodiments, can first carry out the first emitter stage ion implantation technology, after carry out the second emitter stage
Ion implantation technology.
In the present embodiment, because the type of the fin bipolar junction transistor for being formed is positive-negative-positive, because
This, the first emitter stage ion and the second emitter stage ion are p-type ion, such as B or In, described first
The concentration of emitter-base bandgap grading ion is 3E14atom/cm2～1E15atom/cm2, the concentration of described second emitter stage ion
For 1E15atom/cm2～3E15atom/cm2.
In a specific embodiment, the technological parameter of described first emitter stage ion implantation technology is：
Using ion be B ion, Implantation Energy is 3KeV～5KeV, and implantation dosage is
3E14atom/cm2～1E15atom/cm2, implant angle be 0 degree Celsius～7 degrees Celsius；Concrete at another
Embodiment in, the technological parameter of described first emitter stage ion implantation technology is：Using ion be BF2
Ion, Implantation Energy is 8KeV～15KeV, and implantation dosage is 3E14atom/cm2～1E15atom/cm2,
Implant angle is 0 degree Celsius～7 degrees Celsius.Described implant angle is and Semiconductor substrate 200 normal between
Angle.
In a specific embodiment, the technological parameter of described second emitter stage ion implantation technology is：
Using ion be B ion, Implantation Energy is 1KeV～3KeV, and implantation dosage is
1E15atom/cm2～3E15atom/cm2, implant angle be 0 degree Celsius～7 degrees Celsius；Concrete at another
Embodiment in, the technological parameter of described second emitter stage ion implantation technology is：Using ion be BF2
Ion, Implantation Energy is 4KeV～7KeV, 1E15atom/cm2～3E15atom/cm2, implant angle is 0
Degree Celsius～7 degrees Celsius.Described implant angle is the angle and Semiconductor substrate 200 normal between.
In the present embodiment, described first emitter stage ion is injected into the second emitter stage ion area 212 bottom
Emitter stage fin 210 region whole volume；In other embodiments, described first emitter stage ion note
Enter in the partial volume in emitter stage fin 210 region of the second emitter stage ion area 212 bottom.When first
The part body in emitter stage fin 210 region to the second emitter stage ion area 212 bottom for the emitter stage ion implanting
In long-pending, subsequently after annealing, described first emitter stage ion can spread, and in the second emitter stage
All it is distributed in emitter stage fin 210 region of ion area 212 bottom.
It should be noted that fin bipolar junction transistor has launch site, in the present embodiment, doping the
The emitter stage fin 210 of one emitter stage ion and the second emitter stage ion constitutes fin bipolar junction transistor
Launch site.
It should be noted that in the present embodiment, first in described base fin 220 and base epitaxial layer 221
Impure base fin ion, impure collecting electrode fin in described colelctor electrode fin 230 and collector epitaxial layer 231
Ion, then adulterate in described emitter stage fin 210 first emitter stage ion and the second emitter stage ion；
In other embodiments, can first adulterate in described emitter stage fin 210 first emitter stage ion and second
Emitter stage ion, then impure base fin ion in described base fin 220 and base epitaxial layer 221,
Impure collecting electrode fin ion in described colelctor electrode fin 230 and collector epitaxial layer 231.Or, work as institute
State colelctor electrode fin ion concentration identical with described first emitter stage ion when, can impure collecting electrode fin simultaneously
Ion and the first emitter stage ion.Or, as described first colelctor electrode fin ion concentration and described first
When emitter-base bandgap grading ion is identical, can adulterate the first colelctor electrode fin ion and the first emitter stage ion simultaneously；Work as institute
State the second colelctor electrode fin ion concentration identical with the concentration of the second emitter stage ion when, can adulterate simultaneously
Second colelctor electrode fin ion and the second emitter stage ion.
In the present embodiment, also include：Complete impure base fin ion, colelctor electrode fin ion, the first transmitting
After pole ion and the second emitter stage ion, each ion of doping is made annealing treatment in the lump, mixed with activating
Heteroion.In other embodiments, Ke Yishi：Made annealing treatment after completing impure base fin ion,
And made annealing treatment after completing impure collecting electrode fin ion, and complete the first emitter stage ion and second
Made annealing treatment after emitter-base bandgap grading ion.
With reference to Fig. 9, in described emitter stage fin 210 top surface, base epitaxial layer 221 top surface and collection
Electrode epitaxial layer 231 top surface forms electrode 240；
Described electrode 240 is used for transmitting electrical signal.
The material of described electrode 240 is metal, such as copper, aluminium or tungsten.In the present embodiment, described electrode 240
Material be tungsten.
The formation process of described electrode 240 is depositing operation, such as physical vapour deposition (PVD), described electrode 240
Formation process can also be electroplating technology, will not be described here.
In sum, technical scheme has advantages below：
The forming method of the fin bipolar junction transistor that the present invention provides, forms using in emitter stage fin
First emitter stage ion and the second emitter stage ion, described second emitter stage ion is located at the top of emitter stage fin
The concentration of portion and the second emitter stage ion be more than the first emitter stage ion concentration, described second emitter stage from
Son can reduce follow-up contact gesture between the electrode that emitter stage fin top surface is formed and emitter stage fin
Build.
Further, when the quantity of described emitter stage fin is multiple, due on described emitter stage fin surface
Not necessarily form emitter epitaxial layer, can effectively avoid leading to phase because needing to form emitter epitaxial layer
The phenomenon connecting between adjacent emitter epitaxial layer, thus effectively avoid the total current by emitter stage fin
Reduction and the problem of fin bipolar junction transistor stability decline.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
Shield scope should be defined by claim limited range.
Claims (18)
1. a kind of forming method of fin bipolar junction transistor is it is characterised in that include：
Semiconductor substrate is provided；
Form colelctor electrode fin, base fin and emitter stage fin in described semiconductor substrate surface, base fin is located at collection
Between electrode fin and emitter stage fin, described colelctor electrode fin, base fin and emitter stage fin are parallel to each other；
Form base epitaxial layer on described base fin surface；
Form collector epitaxial layer on described colelctor electrode fin surface；
Impure base fin ion in described base fin and base epitaxial layer；
Impure collecting electrode fin ion in described colelctor electrode fin and collector epitaxial layer；
Adulterate in described emitter stage fin the first emitter stage ion and the second emitter stage ion, described second transmitting
Pole ion is located at the top of emitter stage fin, and described first emitter stage ion is located at the second emitter stage ion
Bottom, and the concentration of described second emitter stage ion is more than the concentration of the first emitter stage ion.
2. the forming method of fin bipolar junction transistor according to claim 1 is it is characterised in that institute
State base fin around emitter stage fin, described colelctor electrode fin is around described base fin.
3. the forming method of fin bipolar junction transistor according to claim 1 is it is characterised in that work as
When the quantity of described base fin is multiple, the plurality of base fin is parallel to each other；When described colelctor electrode fin
Quantity be multiple when, the plurality of colelctor electrode fin is parallel to each other；When the quantity of described emitter stage fin is
When multiple, the plurality of emitter stage fin is parallel to each other.
4. the forming method of fin bipolar junction transistor according to claim 1 is it is characterised in that institute
Stating fin bipolar junction transistor is positive-negative-positive fin bipolar junction transistor.
5. the forming method of fin bipolar junction transistor according to claim 4 is it is characterised in that institute
The concentration stating the second emitter stage ion is 1E15atom/cm2～3E15atom/cm2；Described first transmitting
The concentration of pole ion is 3E14atom/cm2～1E15atom/cm2.
6. the forming method of fin bipolar junction transistor according to claim 4 is it is characterised in that institute
Stating the first emitter stage ion and the second emitter stage ion is p-type ion.
7. the forming method of fin bipolar junction transistor according to claim 4 is it is characterised in that right
The technique of described emitter stage fin doping the first emitter stage ion is the first emitter stage ion implantation technology；Right
The technique of described emitter stage fin doping the second emitter stage ion is the second emitter stage ion implantation technology.
8. the forming method of fin bipolar junction transistor according to claim 7 is it is characterised in that institute
The ion stating the first emitter stage ion implantation technology employing is B ion, and Implantation Energy is
3KeV～5KeV, implantation dosage is 3E14atom/cm2～1E15atom/cm2, implant angle be 0 degree
～7 degree.
9. the forming method of fin bipolar junction transistor according to claim 7 is it is characterised in that institute
The ion stating the first emitter stage ion implantation technology employing is BF2Ion, Implantation Energy is
8KeV～15KeV, implantation dosage is 3E14atom/cm2～1E15atom/cm2, implant angle be 0 degree
～7 degree.
10. the forming method of fin bipolar junction transistor according to claim 7 is it is characterised in that institute
The ion stating the second emitter stage ion implantation technology employing is B ion, and Implantation Energy is
1KeV～3KeV, implantation dosage is 1E15atom/cm2～3E15atom/cm2, implant angle be 0 degree
～7 degree.
The forming method of 11. fin bipolar junction transistors according to claim 7 is it is characterised in that institute
The ion stating the second emitter stage ion implantation technology employing is BF2Ion, Implantation Energy is
4KeV～7KeV, implantation dosage is 1E15atom/cm2～3E15atom/cm2, implant angle be 0 degree
～7 degree.
The forming method of 12. fin bipolar junction transistors according to claim 4 is it is characterised in that institute
The material stating collector epitaxial layer is SiGe；The material of described base epitaxial layer is carborundum.
The forming method of 13. fin bipolar junction transistors according to claim 4 is it is characterised in that institute
Stating base fin ion is N-type ion；Described colelctor electrode fin ion is p-type ion.
The forming method of 14. fin bipolar junction transistors according to claim 4 is it is characterised in that institute
The concentration stating base fin ion is 5E14atom/cm2～1E15atom/cm2；Described colelctor electrode fin ion
Concentration be 3E14atom/cm2～1E15atom/cm2.
The forming method of 15. fin bipolar junction transistors according to claim 4 is it is characterised in that right
The technique of described base fin and base epitaxial layer impure base fin ion is base fin ion implantation technology；
Technique to described colelctor electrode fin and collector epitaxial layer impure collecting electrode fin ion is colelctor electrode fin ion
Injection technology.
The forming method of 16. fin bipolar junction transistors according to claim 15 is it is characterised in that institute
The ion stating the employing of base fin ion implantation technology is P ion, and Implantation Energy is 6KeV～10KeV,
Implantation dosage is 5E14atom/cm2～1E15atom/cm2, implant angle be 0 degree Celsius～7 degrees Celsius.
The forming method of 17. fin bipolar junction transistors according to claim 15 is it is characterised in that institute
The ion stating the employing of colelctor electrode fin ion implantation technology is B ion, and Implantation Energy is 3KeV～5KeV,
Implantation dosage is 3E14atom/cm2～1E15atom/cm2, implant angle be 0 degree Celsius～7 degrees Celsius.
The forming method of 18. fin bipolar junction transistors according to claim 1 is it is characterised in that institute
State Semiconductor substrate and include the first well region and the second well region being connected in the horizontal direction with the first well region,
In described second well region and the first well region, the ionic type of doping is contrary, and described colelctor electrode fin is located at first
Well region surface, and colelctor electrode fin ion is identical with the ionic type of doping in the first well region, described base stage
Fin and described emitter stage fin are located at the second well region surface.
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| CN108695374A (en) * | 2017-04-10 | 2018-10-23 | 中芯国际集成电路制造(上海)有限公司 | Bipolar transistor and forming method thereof |
| CN109786246A (en) * | 2017-11-10 | 2019-05-21 | 中芯国际集成电路制造(上海)有限公司 | Fin bipolar junction transistor and forming method thereof |
| US20190267478A1 (en) * | 2017-05-05 | 2019-08-29 | United Microelectronics Corp. | Bipolar junction transistor |
| EP4386856A4 (en) * | 2021-10-28 | 2024-10-16 | Huawei Tech Co Ltd | Fin-bipolar junction transistor and preparation method therefor, and electronic device |
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| CN108695374A (en) * | 2017-04-10 | 2018-10-23 | 中芯国际集成电路制造(上海)有限公司 | Bipolar transistor and forming method thereof |
| CN108695374B (en) * | 2017-04-10 | 2021-07-13 | 中芯国际集成电路制造(上海)有限公司 | Bipolar transistor and method of forming the same |
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| EP4386856A4 (en) * | 2021-10-28 | 2024-10-16 | Huawei Tech Co Ltd | Fin-bipolar junction transistor and preparation method therefor, and electronic device |
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| CN106409890B (en) | 2019-07-30 |
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