CN103578981B - Field terminates the preparation method of insulated gate bipolar transistor - Google Patents
Field terminates the preparation method of insulated gate bipolar transistor Download PDFInfo
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- CN103578981B CN103578981B CN201210250474.2A CN201210250474A CN103578981B CN 103578981 B CN103578981 B CN 103578981B CN 201210250474 A CN201210250474 A CN 201210250474A CN 103578981 B CN103578981 B CN 103578981B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 32
- 238000005468 ion implantation Methods 0.000 claims abstract description 14
- 239000010410 layer Substances 0.000 claims description 109
- 238000000034 method Methods 0.000 claims description 31
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- 239000011241 protective layer Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 8
- 125000006850 spacer group Chemical group 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 5
- 238000003475 lamination Methods 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 235000012431 wafers Nutrition 0.000 description 46
- 239000004065 semiconductor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005352 clarification Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The present invention provides a kind of the preparation method terminating insulated gate bipolar transistor, belongs to insulated gate bipolar transistor (IGBT) technical field.In this preparation method, including step: provide the wafer having basically formed the Facad structure that field terminates insulated gate bipolar transistor；The Facad structure of described wafer deposits front protecting layer；Make it carry on the back implanter facing to the front the upset of described wafer, and use this front implanter that the field stop layer at the back side of described wafer is carried out ion implantation doping to form collector layer；And remove described front protecting layer.Front implanter can be used in this preparation method to realize the ion implanting of collector layer so that it is easily compatible with front road processing line, and the Facad structure of FS IGBT is effectively protected, the yield of FS IGBT and reliability are high.
Description
Technical field
The invention belongs to insulated gate bipolar transistor (Insulated Gate Bipolar Transistor; IGBT) technical field; relate to field and terminate (Field Stop; FS) IGBT, particularly relate to a kind of front wafer surface formed front protecting layer with realize can use front implanter that the back side of wafer is carried out the IGBT preparation method of ion implantation technology.
Background technology
IGBT is a kind of common power-type device, including a kind of FS-IGBT.In the front road technique of the customary preparation methods of FS-IGBT, the most first after the back side of wafer (wafer) forms FS layer, carry out flow according still further to conventional IGBT road technological process just in front, then on the FS layer at its back side, ion implantation doping is carried out, to form the collector layer of such as P+ layer.
But, when carrying out the ion implanting of collector layer, it usually needs use back side implanter to complete the ion implantation technology of this step.And in semiconductor fabrication, back side implanter and front implanter are the equipment that both are different, back side implanter is generally arranged on postchannel process line, and front implanter is typically to arrange in front road processing line；If using back side implanter that FS layer is carried out ion implanting in front road technique, this would be required to forward to flow of wafers complete on the back side implanter of postchannel process line, return again in front road processing line, so, arise that rear road returns now, is difficult to and the problem of front road processing line compatibility, process is complicated, and this is generally also in semiconductor process flow design and needs to be avoided.
Front implanter is directly used to carry out ion implanting during if carried out the ion implanting of collector layer, so it is easily caused loading end damage and/or pollution that front wafer surface is contacted, the yield etc. of postchannel process in front may decline, be unfavorable for the realization of the normal function of FS-IGBT.
In view of this, it is necessary to propose a kind of novel FS-IGBT preparation method.
Summary of the invention
An object of the present invention is, makes the collector layer ion implanting at the back side of FS-IGBT can be completed by front ion implantation apparatus, thus is allowed to easy to be compatible with front road processing line.
A further object of the present invention is, prevents the Facad structure of FS-IGBT be damaged in the collector layer ion implantation process at its back side and/or pollute.
For realizing object above or other purposes, the present invention provides a kind of the preparation method terminating insulated gate bipolar transistor, and it comprises the following steps:
The wafer having basically formed the Facad structure that field terminates insulated gate bipolar transistor is provided；
The Facad structure of described wafer deposits front protecting layer；
Make it carry on the back implanter facing to the front the upset of described wafer, and use this front implanter that the field stop layer at the back side of described wafer is carried out ion implantation doping to form collector layer；And
Remove described front protecting layer.
According to the preparation method of one embodiment of the invention, wherein, it is provided that described wafer in, including the spacer medium layer being positioned on gate electrode being complete in Facad structure；Wherein, described front protecting layer is deposited on this spacer medium layer.
According to the preparation method of one embodiment of the invention, wherein, it is provided that described wafer in, on the field stop layer at the back side of described wafer, be formed with the back-protective layer for described field stop layer being protected during preparing described Facad structure.
Further, before described wafer overturning step, further comprise the steps of:
Remove described back-protective layer.
According to the preparation method of one embodiment of the invention, wherein, described front protecting layer is the lamination layer structure at least formed by oxide layer and silicon nitride layer, and described oxide deposition is formed on described silicon nitride layer.
Further, remove in the step of described front protecting layer, use fully stripped method to remove described silicon nitride layer, thus remove described front protecting layer.
Further, the thickness range of described oxide layer is 100nm to 700nm, and the thickness range of described silicon nitride layer is 30nm to 200nm.
According to the preparation method of one embodiment of the invention, wherein, depositing in the step of front protecting layer on the Facad structure of described wafer, the while of also, the backside deposition at described wafer has essentially identical front protecting layer.
Further, before described wafer overturning step, further comprise the steps of:
Remove the front protecting layer at the back side of described wafer.
According to the preparation method of one embodiment of the invention, wherein, after removing the step of described front protecting layer, the preparation of metal electrode has been further comprised the steps of:.
According to the preparation method of one embodiment of the invention, wherein, the doping content scope of described collector layer is 1E16 ion/cm3To 1E20 ion/cm3。
The solution have the advantages that; front protecting layer on the Facad structure being formed at wafer that preparation process is used; such that it is able to use front implanter to realize the ion implanting of collector layer so that it is easily compatible with front road processing line, be conducive to simplifying preparation technology flow process；Further, this front protecting layer is possible to prevent the Facad structure of FS-IGBT be damaged in the collector layer ion implantation process at its back side and/or pollute, it is ensured that the yield of FS-IGBT and reliability.
Accompanying drawing explanation
From combine accompanying drawing described further below, it will making the above and other purpose of the present invention and advantage be more fully apparent from, wherein, same or analogous key element is adopted and is indicated by the same numeral.
Fig. 1 is the schematic flow sheet of the FS-IGBT preparation method according to one embodiment of the invention.
Fig. 2 to Fig. 8 corresponds to the structure change schematic diagram of the method flow of embodiment illustrated in fig. 1.
Detailed description of the invention
Be described below is that the multiple of the present invention may some in embodiments, it is desirable to provide the basic understanding to the present invention, it is no intended to confirms the crucial of the present invention or conclusive key element or limits scope of the claimed.Easy to understand, according to technical scheme, under the connotation not changing the present invention, one of ordinary skill in the art can propose other implementations that can mutually replace.Therefore, detailed description below and accompanying drawing are only the exemplary illustrations to technical scheme, and are not to be construed as the whole of the present invention or are considered as defining or limiting technical solution of the present invention.
In the accompanying drawings, for the sake of clarity, the thickness in layer and region is exaggerated, and, the mellow and full shape facility such as grade caused due to etching illustrates not in the drawings.
Herein, in the wafer preparing FS-IGBT, its back side is defined as the one side for forming FS layer, and its front is defined as at least for forming the one side of the grid end of FS-IGBT；Wherein, " front implanter " refers to when wafer is normally put, and can be opposite in the ion implantation device that the front of wafer is arranged, and it can carry out front ion implanting to the front of the normal wafer put；" back side implanter " refers to when wafer is normally put, and can be opposite in the ion implantation device that the back side of wafer is arranged, and it can carry out front ion implanting to the back side of the normal wafer put.
In the de-scription, use directional terminology (such as " on ", D score etc.) and the parts of various embodiments that describe of similar terms represent the direction shown in accompanying drawing or the direction that can be readily appreciated by one skilled in the art.These directional terminology are for relative description and clarification rather than the orientation of any embodiment are limited to concrete direction or orientation.
Fig. 1 show the schematic flow sheet of the FS-IGBT preparation method according to one embodiment of the invention.Fig. 2 to Fig. 8 show the structure change schematic diagram of the method flow corresponding to embodiment illustrated in fig. 1.In the embodiment shown in the drawings, to be perpendicular to wafer surface and to point to the direction of front implanter from wafer surface and be defined as z direction, the direction being parallel to wafer surface is defined as x direction.Below in conjunction with Fig. 1 to Fig. 8, the photoetching method of the embodiment of the present invention is illustrated.
First, step S10, it is provided that basically formed the wafer of the Facad structure of FS-IGBT.As in figure 2 it is shown, the Semiconductor substrate that wafer 100 adulterates for N-, its doping content is the doping content of the drift layer of the IGBT to be formed, and therefore, the doping content scope of wafer 100 is chosen as 8E12 ion/cm3To 1E13 ion/cm3, for example, 9E12 ion/cm3.On the back side of wafer 100, ion implantation doping is to form FS layer 120, in this embodiment, for preventing ion implanting from causing semiconductor substrate lattice to damage, forms thin oxide layer 121 at the back side of wafer 100.The thickness range of thin oxide layer 120 is 10nm to 200nm(for example, 100nm).In the present invention, front road technique is distinguished according to the definition of those skilled in the art with postchannel process.In one embodiment of this invention, Facad structure includes P-body district 140, emitter layer 142, gate dielectric layer 143, polygate electrodes 144 and spacer medium floor 145, and spacer medium layer 145 is used for realizing the isolation between polygate electrodes 144 and emission electrode (not shown in Fig. 2).In this embodiment, Facad structure is the Facad structure of plane IGBT, but, the Facad structure of IGBT is not limited by the embodiment of the present invention, and in other embodiments, Facad structure can also be the Facad structure of groove-shaped IGBT.The front road process of Facad structure is not restrictive, and it can use various front roads process to complete the preparation of Facad structure.In such an embodiment, it is preferable be complete the spacer medium layer 145 of covering grid electrode 144.
Continue as in figure 2 it is shown, in such an embodiment, it is preferable in completing the front road technical process of Facad structure of FS-IGBT, it would however also be possible to employ back-protective layer 122 prevents FS layer 120 be damaged and/or pollute.Therefore it provides wafer be included on the FS layer 120 at its back side formed back-protective layer 122.In one example, back-protective layer 122 can be, but not limited to as polysilicon layer, and its thickness range is 100nm to 2000nm, for example, 500nm.
Further, step S20, the Facad structure of wafer deposits front protecting layer.As it is shown on figure 3, in this embodiment, front protecting layer 150 is chosen as lamination layer structure, and it includes the silicon nitride layer (SiN) 151 on oxide layer 152 and oxide layer 152；The thickness range of oxide layer 152 is 100-700nm, such as, is chosen as 300nm；The thickness range of silicon nitride layer 151 is 30-200nm, such as, is chosen as 70nm.The concrete lamination layer structure of front protecting layer 150 is not limited by diagram embodiment, and it can be it can also be provided that other have the lamination layer structure of defencive function；Even, front protecting layer is in other embodiments it can also be provided that single layer structure.Those skilled in the art can select to arrange material type and the structure of front protecting layer 150 according to the condition etc. of concrete front road processing line.
In this embodiment; the front of wafer is deposited form front protecting layer 150 time, also the most on the back side, namely on back-protective layer 122; deposition defines the silicon nitride layer 151a on the structure identical with front protecting layer 150, i.e. oxide layer 152a and oxide layer 152a.
Further, step S30, as shown in Figure 4, the front protecting layer segment of chip back surface is removed.In this embodiment, for oxide layer 152a and silicon nitride layer 151a, the method that can first pass through wet etching is removed removing oxide layer 152a, then is removed silicon nitride layer 151a by fully stripped method.
Further, step S40, as it is shown in figure 5, remove the back-protective layer of chip back surface, to be ready for collector layer ion implanting.Specifically, can be, but not limited to the back-protective layer 122 using dry etching to remove polysilicon.
Further, step S50, wafer upset is made the back of the body implanter facing to the front of wafer, and uses front implanter that the FS layer at the back side of wafer is carried out ion implanting to form collector layer.As shown in Figure 6, after overturning wafer, FS layer 120, towards front implanter (now wafer is improper storing), therefore, it can use front implanter that it is carried out ion implanting smoothly；Meanwhile, the front protecting layer 150 on the front of wafer can realize the protection of the Facad structure to FS-IGBT, prevents during it, and it is caused damage and/or pollution by the workbench (such as crystal chip bearing platform) of front implanter etc..Specifically, ion implanting can be, but not limited to use boron ion implanting, and forms P+ layer 130, namely collector layer 130 by pushing away trap technique.Certainly, push away trap technique to carry out again after front protecting layer 150 is removed.
Therefore, this step can use front implanter to realize the ion implanting of collector layer, thus easily compatible with front road processing line, can avoid using the backside particulate implanter of postchannel process line.Further, front protecting layer 150 is possible to prevent the Facad structure of FS-IGBT be damaged in the collector layer ion implantation process at its back side and/or pollute, it is ensured that the yield of FS-IGBT and reliability.
Specifically, the doping content scope of collector layer 11 is 1E16 ion/cm3To 1E20 ion/cm3, for example, 1E19 ion/cm3.The concrete ion implantation technology condition of collector layer 130, such as Implantation Energy etc. are not restrictive, and it can select to arrange the various process conditions that various fronts implanter can be done by and realize ion implanting.
Further, step S60, as it is shown in fig. 7, remove the front protecting layer 150 of front wafer surface.In this embodiment, use fully stripped method to remove silicon nitride layer 151, thus remove whole front protecting layer 150, the convenient Facad structure that can't damage FS-IGBT of removal process, be conducive to improving the reliability preparing yield and FS-IGBT of FS-IGBT.
Further, step S70, complete the preparation of metal electrode.In this embodiment, as shown in Figure 8, completing at the back side of wafer to carry on the back gold process, to form colelctor electrode 135, the front composition at wafer prepares metal electrode to form emission electrode 148.
So far, the FS-IGBT of one embodiment of the invention is defined basically.
Example above primarily illustrates the preparation method of the FS-IGBT of the present invention.Although being only described some of them embodiments of the present invention, but those of ordinary skill in the art are it is to be appreciated that the present invention can be implementing with other forms many with in scope without departing from its spirit.Therefore, the example shown and embodiment are considered illustrative and not restrictive, and in the case of without departing from spirit and scope of the present invention as defined in appended claims, the present invention may contain various amendments and replacement.
Claims (8)
1. the preparation method of a field termination insulated gate bipolar transistor, it is characterised in that comprise the following steps:
Thering is provided the wafer having formed the Facad structure that field terminates insulated gate bipolar transistor, wherein said wafer includes the spacer medium layer being covered on gate electrode being complete in Facad structure；
Depositing front protecting layer on the spacer medium layer of the Facad structure of described wafer, wherein said front protecting layer is the lamination layer structure at least formed by oxide layer and silicon nitride layer, and described oxide deposition is formed on described silicon nitride layer；
Make it carry on the back implanter facing to the front the upset of described wafer, and use this front implanter that the field stop layer at the back side of described wafer is carried out ion implantation doping to form collector layer；And
Use fully stripped method to remove described silicon nitride layer, thus remove described front protecting layer.
2. preparation method as claimed in claim 1, it is characterised in that in the described wafer of offer, on the field stop layer at the back side of described wafer, be formed with the back-protective layer for described field stop layer being protected during preparing described Facad structure.
3. preparation method as claimed in claim 2, it is characterised in that before described wafer overturning step, further comprise the steps of:
Remove described back-protective layer.
4. preparation method as claimed in claim 1, it is characterised in that the thickness range of described oxide layer is 100nm to 700nm, and the thickness range of described silicon nitride layer is 30nm to 200nm.
5. preparation method as claimed in claim 1, it is characterised in that depositing in the step of front protecting layer on the Facad structure of described wafer, the while of also, the backside deposition at described wafer has the back-protective layer identical with front protecting Rotating fields.
6. preparation method as claimed in claim 5, it is characterised in that before described wafer overturning step, further comprise the steps of:
Remove the back-protective layer identical with front protecting Rotating fields at the back side of described wafer.
7. preparation method as claimed in claim 1, it is characterised in that after removing the step of described front protecting layer, further comprised the steps of: the preparation of metal electrode.
8. preparation method as claimed in claim 1, it is characterised in that the doping content scope of described collector layer is 1E16 ion/cm3To 1E20 ion/cm3。
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| CN201210250474.2A CN103578981B (en) | 2012-07-19 | 2012-07-19 | Field terminates the preparation method of insulated gate bipolar transistor |
| PCT/CN2013/078545 WO2014012426A1 (en) | 2012-07-19 | 2013-06-30 | Method for manufacturing field stop igbt |
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| CN201210250474.2A CN103578981B (en) | 2012-07-19 | 2012-07-19 | Field terminates the preparation method of insulated gate bipolar transistor |
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| CN103578981B true CN103578981B (en) | 2016-09-07 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101017850A (en) * | 2007-02-14 | 2007-08-15 | 上海富华微电子有限公司 | VDMOS and IGBT power unit using the PSG doping technology and its making process |
| CN101419970A (en) * | 2007-10-24 | 2009-04-29 | 富士电机电子技术株式会社 | Semiconductor device with control circuit |
| CN102087956A (en) * | 2009-12-08 | 2011-06-08 | 上海华虹Nec电子有限公司 | Method for back implanting to substrate in ion implantation technology |
| CN102184854A (en) * | 2011-04-14 | 2011-09-14 | 电子科技大学 | Method for protecting front face metal pattern during thermal annealing of back face of power device |
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| DE10205323B4 (en) * | 2001-02-09 | 2011-03-24 | Fuji Electric Systems Co., Ltd. | Method for producing a semiconductor component |
| JP2008085050A (en) * | 2006-09-27 | 2008-04-10 | Renesas Technology Corp | Manufacturing method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101017850A (en) * | 2007-02-14 | 2007-08-15 | 上海富华微电子有限公司 | VDMOS and IGBT power unit using the PSG doping technology and its making process |
| CN101419970A (en) * | 2007-10-24 | 2009-04-29 | 富士电机电子技术株式会社 | Semiconductor device with control circuit |
| CN102087956A (en) * | 2009-12-08 | 2011-06-08 | 上海华虹Nec电子有限公司 | Method for back implanting to substrate in ion implantation technology |
| CN102184854A (en) * | 2011-04-14 | 2011-09-14 | 电子科技大学 | Method for protecting front face metal pattern during thermal annealing of back face of power device |
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| WO2014012426A1 (en) | 2014-01-23 |
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