CN110649094A - GCT chip structure and preparation method thereof - Google Patents
GCT chip structure and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 238000009792 diffusion process Methods 0.000 claims description 56
- 238000000151 deposition Methods 0.000 claims description 41
- 238000005468 ion implantation Methods 0.000 claims description 40
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- 230000008021 deposition Effects 0.000 claims description 30
- 239000002184 metal Substances 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 27
- 238000000059 patterning Methods 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 238000010030 laminating Methods 0.000 claims description 6
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- 238000004519 manufacturing process Methods 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 6
- 239000000243 solution Substances 0.000 description 5
- 238000002161 passivation Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
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- 238000002513 implantation Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
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- 238000006243 chemical reaction Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
Abstract
The invention discloses a GCT chip structure and a preparation method thereof, wherein the GCT chip structure comprises a P + emitter for leading out an anode, an n + buffer layer attached to the P + emitter, and an n drift region attached to the n + buffer layer, and the GCT chip structure further comprises: the first P + region is attached to the n drift region; the second P + region is attached to the first P + region; the n + emitter is connected with the second P + region, the n + emitter leads out a cathode, the second P + region leads out a gate pole, the cathode and the gate pole have a height difference, and the range of the height difference is 0-10 mu m.
Description
Technical Field
The invention belongs to the field of power semiconductor devices, and particularly relates to a GCT chip structure and a preparation method thereof.
Background
The IGCT device is a new generation of current control device developed on the basis of GTO, and from the aspect of a chip, the GCT chip adopts a transparent anode technology and a buffer layer design, so that the trigger current level and the conduction voltage drop of the device are reduced. From the view of a gate driving circuit and an on-off mechanism, the IGCT adopts an integrated driving circuit mode, reduces stray parameters of a current conversion loop to a nano-Henry magnitude by optimizing a circuit layout, a tube shell packaging structure and the like, enables current to be completely converted to a gate from a cathode in a short time in the device turn-off process, and then enables the PNP triode to be naturally turned off.
Referring to fig. 1, fig. 1 is a schematic diagram of a conventional GCT chip structure. As shown in fig. 1, since there is a longitudinal distance between the gate and the cathode, that is, there is a groove structure on the cathode side surface, when designing the unit, in order to ensure the process feasibility, the transverse dimension h is constrained and difficult to be further shortened, but the transverse dimension directly determines the gate resistance in the GCT unit, thereby affecting the maximum off-current capability.
Therefore, it is urgently needed to develop a GCT chip structure and a preparation method thereof, which overcome the above defects.
Disclosure of Invention
In view of the above problems, the present invention provides a GCT chip structure, which includes a P + emitter for leading out an anode, an n + buffer layer attached to the P + emitter, and an n drift region attached to the n + buffer layer, wherein the GCT chip structure further includes:
the first P + region is attached to the n drift region;
a second P + region bonded to the first P + region; and
and the n + emitter is connected with the second P + region, a cathode is led out of the n + emitter, a gate is led out of the second P + region, the cathode and the gate have a height difference, and the range of the height difference is 0-10 mu m.
The GCT chip structure further comprises a P base region, wherein the P base region is attached to the n drift region and located between the first P + region and the n drift region, and the first P + region is attached to the P base region.
In the above GCT chip structure, the thickness of the second P + region is the same as the thickness of the n + emitter.
In the above GCT chip structure, a connection between the first P + region and the n drift region has a wavy shape.
In the above GCT chip structure, the cathode and the gate are located on the same plane.
In the above GCT chip structure, the middle plane of the wavy structure protrudes toward the first P + region, and the height of the protrusion is less than 40 μm.
In the GCT chip structure, the thickness of the second P + region is 1-30 μm.
The invention also provides a preparation method of the GCT chip structure, which comprises the following steps:
step S11: forming a first P + region and a P base region on the cathode surface of the n-substrate by utilizing diffusion or deposition diffusion after ion implantation;
step S12: forming an n + buffer layer on the anode surface of the n-substrate by utilizing diffusion or deposition diffusion after ion implantation;
step S13: growing a second P + region in the first P + region by using a silicon epitaxial method;
step S14: and forming an n-type doped region in the second P + region by using a selective ion implantation or selective deposition mode, and performing propulsion through thermal diffusion to form an n + emitter.
Step S15: diffusing or depositing and diffusing after ion implantation on the n + buffer layer to form a p + emitter;
step S16: and forming two-side metal electrode contact and patterning, wherein the metal electrode on the surface of the cathode is higher than the metal electrode on the surface of the gate.
The invention also provides a preparation method of the GCT chip structure, which comprises the following steps:
step S21: forming a first P + region and a P base region on the cathode surface of the n-substrate by utilizing diffusion or deposition diffusion after ion implantation;
step S22: forming an n + buffer layer on the anode surface of the n-substrate by utilizing diffusion or deposition diffusion after ion implantation;
step S23: connecting the P-substrate or the SOI sheet with the cathode surface of the n-substrate which has finished the multi-step diffusion process by adopting the P-substrate or the SOI sheet through silicon-silicon bonding, and thinning to obtain a second P + region;
step S24: forming an n-type doped region in the second P + region by using a selective ion implantation or selective deposition mode, and pushing through thermal diffusion to form an n + emitter;
step S25: diffusing or depositing and diffusing after ion implantation on the n + buffer layer to form a p + emitter;
step S26: and forming two-side metal electrode contact and patterning, wherein the metal electrode on the surface of the cathode is higher than the metal electrode on the surface of the gate.
The invention also provides a preparation method of the GCT chip structure, which comprises the following steps:
step S31: diffusing or depositing and diffusing the implanted ions on the cathode surface of the n-substrate to form a second P + region, a first P + region and a P base region;
step S32: forming an n + buffer layer on the anode surface of the n-substrate by utilizing diffusion or deposition diffusion after ion implantation;
step S33: forming an n-type doped region in the second P + region by using a selective ion implantation or selective deposition mode, and pushing through thermal diffusion to form an n + emitter;
step S34: diffusing or depositing and diffusing after ion implantation on the n + buffer layer to form a p + emitter;
step S35: and forming two-side metal electrode contact and patterning, wherein the metal electrode on the surface of the cathode is higher than the metal electrode on the surface of the gate.
Aiming at the prior art, the invention has the following effects:
1. compared with the prior GCT chip structure, the structure has similar gate cathode breakdown voltage.
2. Compared with the conventional GCT chip structure, the design space of the transverse dimension is increased by designing the height difference between the cathode and the gate.
3. Compared with the conventional GCT chip structure, the high-power-factor low-voltage power supply has stronger current turn-off capability under the same process uniformity condition.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a conventional GCT chip structure;
FIG. 2 is a schematic diagram of the GCT chip structure and its doping structure according to the present invention;
FIG. 3 is a diagram of a GCT chip structure according to a second embodiment of the present invention;
FIG. 4 is a process diagram of a conventional GCT chip structure;
FIG. 5 is a flow chart of a first embodiment of the production method of the present invention;
FIG. 6 is a process diagram of FIG. 5;
FIG. 7 is a flow chart of a second embodiment of the production method of the present invention;
FIG. 8 is a process diagram of FIG. 7;
FIG. 8a is a diagram of a process path using an SOI wafer;
FIG. 9 is a flow chart of a third embodiment of the production method of the present invention;
fig. 10 is a process diagram of fig. 9.
Wherein the reference numerals are:
height difference: d
Transverse dimension: h is
First P + region: p1
Second P + region: p2
Wave shape: w
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
With respect to directional terminology used herein, for example: up, down, left, right, front or rear, etc., are simply directions with reference to the drawings. Accordingly, the directional terminology used is intended to be illustrative and is not intended to be limiting of the present teachings.
As used herein, the terms "comprising," "including," "having," "containing," and the like are open-ended terms that mean including, but not limited to.
The exemplary embodiments of the present invention and the description thereof are provided to explain the present invention and not to limit the present invention. Additionally, the same or similar numbered elements/components used in the drawings and the embodiments are used to represent the same or similar parts.
Referring to fig. 2, fig. 2 is a schematic diagram of a GCT chip structure and a doping structure thereof according to the present invention. As shown in fig. 2, the GCT chip structure of the present invention includes: the P + emitter of extraction Anode (Anode), the n + buffer layer of laminating with the P + emitter, the n drift region of laminating with the n + buffer layer, the first P + region P1 of laminating with the n drift region, the second P + region P2 of laminating with first P + region P1 district and the n + emitter of being connected with second P + region P2, wherein the Cathode (Cathode) is drawn forth to n + emitter, and Gate (Gate) is drawn forth to second P + region P2, the Cathode has difference in height d with the Gate, and the range of difference in height d is 0-10 mu m.
It should be noted that, in the present embodiment, it is preferable that the Cathode and the Gate are located on the same plane, so that the height difference d is 0, i.e., the side of the n + emitter extraction Cathode (Cathode) and the side of the second P + region P2 extraction Gate (Gate) are located on the same plane.
It should be noted that, in this embodiment, the right half of fig. 2 is shown in detail, the right half shows the doping concentration of each structure, the abscissa of the drawing shows the doping concentration, and it can be seen from the right half of fig. 2 that the second P + region P2 of the present invention has an approximately uniform doping concentration, so that the breakdown voltage of the J3 junction is increased, and is distinguished from the gaussian distribution or residual error distribution generated by thermal diffusion of a single impurity, and the second P + region P2 can be formed by silicon epitaxy, silicon-silicon bonding, and multiple ion implantations.
Furthermore, the GCT chip structure further comprises a P base region, the P base region is attached to the n drift region and located between the first P + region P1 and the n drift region, and the first P + region P1 is attached to the P base region.
It should be noted that, in this embodiment, the GCT chip structure includes a P-base region, but the invention is not limited thereto, and in other embodiments, in order to avoid the occurrence of process contamination, the GCT chip structure may not be provided with a P-base region structure, and the first P + region P1 is used to realize device voltage resistance.
The interior of the GCT chip is of a typical asymmetric structure, a PN junction is arranged in the GCT chip, different doping processes are adopted for the PN junction, a P-type semiconductor and an N-type semiconductor are manufactured on the same semiconductor substrate through diffusion, and a space charge region called the PN junction is formed at the interface of the P-type semiconductor and the N-type semiconductor. In order to distinguish the respective PN junctions, a PN junction formed at the junction of the n + emitter and the second P + region P2 is set to be a J3 junction, a PN junction formed at the junction of the n drift region and the first P + region P1 is set to be a J2 junction, and a PN junction formed at the junction of the P + emitter and the n + buffer layer is set to be a J1 junction, in this embodiment, the J1 junction and the J2 junction may be arranged in parallel, but the present invention is not limited thereto.
In another embodiment of the present invention, when the depth of the n + emitter is completely equal to the thickness of the second P + region P2, the n + emitter forms a PN junction with both the second P + region P2 and the first P + region P1.
Still further, the thickness of the second P + region P2 is the same as the thickness of the n + emitter; specifically, the thickness of the second P + region P2 is 1 to 30 μm, preferably 15 μm, but the present invention is not limited to specific values.
Referring to fig. 3, fig. 3 is a schematic diagram of a GCT chip structure according to a second embodiment of the present invention. The GCT chip structure shown in fig. 3 is substantially the same as the GCT chip structure shown in fig. 2, and therefore, the same parts are not described herein again, and different parts will now be described below. In the present embodiment, the edge of the first P + region P1 has a wave shape W to improve the maximum turn-off current capability, and the wave shape W can be implemented by masked injection, but the invention is not limited thereto.
Specifically, a wavy structure is arranged in the middle of the junction of the n drift region and the first P + region P1, the junctions of the two sides of the wavy structure are plane junctions, the central axis of the wavy structure corresponds to the position of the n + emitter, and the two sides of the wavy structure are smooth curved surfaces extending outwards with the end line of the middle plane as the starting point. The smooth curved surfaces on the two sides are symmetrically arranged about the central line of the middle plane, the middle plane in the wavy structure protrudes towards the first P + region P1, the height of the protrusion is less than 40 micrometers, the preferred range is 25-30 micrometers, the smooth curved surfaces on the two sides are sunken towards the n drift region, the junction of the first P + region P1 of the n drift region is wavy through the plane of the wavy structure and the arrangement of the two curved surfaces, so that the maximum turn-off current capability of the GCT chip structure is improved, meanwhile, the damage rate of the GCT chip with the wavy structure is greatly reduced compared with a GCT chip without the wavy structure, the dynamic avalanche resistance of an IGCT device can be improved through the wavy structure in the using process, and the damage rate of the IGCT device is effectively reduced.
Referring to fig. 4, fig. 4 is a process path diagram of a conventional GCT chip structure. As shown in FIG. 4, a method for manufacturing a conventional GCT chip structure will be described to be different from the following method for manufacturing the present invention. The preparation method of the conventional GCT chip structure comprises the following steps: a. selecting an n-substrate with specific resistivity and thickness; b. forming a cathode surface p + base region and a p base region by utilizing diffusion or deposition diffusion after ion implantation; c. forming an anode surface n + buffer layer by utilizing diffusion or deposition diffusion after ion implantation; d. forming a thin-layer high-concentration n-type doped region on the cathode surface by using an ion implantation or deposition mode; e. forming a groove shape on the cathode surface by using a dry method or a wet method; f. the cathode surface is pushed by thermal diffusion to form an n + emitter; g. forming an anode surface p + emitter by utilizing diffusion or deposition diffusion after ion implantation; h. forming metal electrode contacts on two sides and patterning; i. and (5) local passivation treatment.
Referring to fig. 5-6, fig. 5 is a flow chart of a first embodiment of a manufacturing method according to the present invention; fig. 6 is a process diagram of fig. 5. As shown in fig. 5 to 6, the preparation method of the present invention comprises:
step S11: forming a first P + region and a P-base region on the cathode surface of the n-substrate by diffusion after ion implantation or deposition diffusion, wherein the step S11 includes a step of selecting the n-substrate with a specific resistivity and thickness, but the invention is not limited thereto;
step S12: forming an n + buffer layer on the anode surface of the n-substrate by utilizing diffusion or deposition diffusion after ion implantation;
step S13: growing a second P + region in the first P + region by using a silicon epitaxial method;
step S14: forming an n-type doped region in the second P + region by using a selective ion implantation or selective deposition mode, and pushing through thermal diffusion to form an n + emitter;
step S15: diffusing or depositing and diffusing after ion implantation on the n + buffer layer to form a p + emitter;
step S16: and forming two-side metal electrode contact and patterning, wherein the metal electrode on the surface of the cathode is higher than the metal electrode on the surface of the gate.
In this embodiment, the method may further include forming a wave shape W at an edge of the first P + region by masked implantation.
In another embodiment of the present invention, when the GCT chip structure may not have a P-base region, step S11 may further include forming a P-type doped region on the cathode surface of the substrate by selective ion implantation or selective deposition, and performing a drive by thermal diffusion to form a first P + region that may have a waved structure.
In this embodiment, after the step S16, a step of local passivation may be further included.
Referring to fig. 7-8, fig. 7 is a flow chart illustrating a second embodiment of a manufacturing method according to the present invention; fig. 8 is a process diagram of fig. 7. As shown in fig. 7 to 8, the preparation method of the present invention comprises:
step S21: forming a first P + region and a P-base region on the cathode surface of the n-substrate by diffusion after ion implantation or deposition diffusion, wherein the step S21 includes a step of selecting the n-substrate with a specific resistivity and thickness, but the invention is not limited thereto;
step S22: forming an n + buffer layer on the anode surface of the n-substrate by utilizing diffusion or deposition diffusion after ion implantation;
step S23: adopting a P-base or an SOI sheet, connecting the P-base or the SOI sheet with the cathode surface of the n-substrate which finishes the multi-step diffusion process through silicon-silicon bonding, and obtaining a second P + region after treatment, specifically, when adopting the P-base, connecting the P-base with the cathode surface of the n-substrate which finishes the multi-step diffusion process through silicon-silicon bonding, and thinning to obtain the second P + region (refer to fig. 8); when the SOI sheet is adopted, the SOI sheet is connected with the cathode surface of the n-substrate which has finished the multi-step diffusion process through silicon-silicon bonding, and the SiO is removed by adopting corrosion treatment2Then, a second P + region is obtained, referring to fig. 8a, and fig. 8a is a process path diagram of the SOI wafer.
Among them, the soi (silicon on insulator) wafer is an insulator-based silicon wafer, and since the substrate is an insulator such as glass (the conventional wafer is a silicon crystal), electron leakage can be reduced, the current efficiency of the wafer can be effectively improved, power consumption can be reduced, and reliability can be improved.
Step S24: forming an n-type doped region in the second P + region by using a selective ion implantation or selective deposition mode, and pushing through thermal diffusion to form an n + emitter;
step S25: diffusing or depositing and diffusing after ion implantation on the n + buffer layer to form a p + emitter;
step S26: and forming two-side metal electrode contact and patterning, wherein the metal electrode on the surface of the cathode is higher than the metal electrode on the surface of the gate.
In this embodiment, the method may further include forming a wave shape W at an edge of the first P + region by masked implantation.
In this embodiment, after the step S26, a step of local passivation may be further included.
Referring to fig. 9-10, fig. 9 is a flow chart illustrating a third embodiment of a manufacturing method according to the present invention; fig. 10 is a process diagram of fig. 9. As shown in fig. 9 to 10, the preparation method of the present invention comprises:
step S31: forming a second P + region, a first P + region and a P-base region on the cathode surface of the n-substrate by diffusion after ion implantation or diffusion by deposition, wherein the step S31 includes a step of selecting the n-substrate with a specific resistivity and thickness, but the invention is not limited thereto;
step S32: forming an n + buffer layer on the anode surface of the n-substrate by utilizing diffusion or deposition diffusion after ion implantation;
step S33: forming an n-type doped region in the second P + region by using a selective ion implantation or selective deposition mode, and pushing through thermal diffusion to form an n + emitter;
step S34: diffusing or depositing and diffusing after ion implantation on the n + buffer layer to form a p + emitter;
step S35: and forming two-side metal electrode contact and patterning, wherein the metal electrode on the surface of the cathode is higher than the metal electrode on the surface of the gate.
In this embodiment, the method may further include forming a wave shape W at an edge of the first P + region by masked implantation.
In this embodiment, after the step S35, a step of local passivation may be further included.
In conclusion, the GTC chip structure and the preparation method thereof have strong applicability, can not only reach the gate cathode breakdown voltage of the conventional GCT chip structure, increase the design space of the transverse dimension and have stronger current turn-off capability under the condition of the same process uniformity, but also further simplify the manufacturing process of the GTC chip.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. The utility model provides a GCT chip architecture, including the P + projecting pole of drawing forth the positive pole, with the n + buffer layer of P + projecting pole laminating, with the n drift region of n + buffer layer looks laminating, its characterized in that, GCT chip architecture still includes:
the first P + region is attached to the n drift region;
a second P + region bonded to the first P + region; and
and the n + emitter is connected with the second P + region, a cathode is led out of the n + emitter, a gate is led out of the second P + region, the cathode and the gate have a height difference, and the range of the height difference is 0-10 mu m.
2. The GCT chip structure of claim 1, further comprising a P-base region attached to the n-drift region and located between the first P + region and the n-drift region, the first P + region attached to the P-base region.
3. The GCT chip structure of claim 1, wherein the thickness of the second P + region is the same as the thickness of the n + emitter.
4. The GCT chip structure of any of claims 1-3, wherein a junction of the first P + region and the n-drift region has a wavy shape.
5. The GCT chip structure of claim 1, wherein said cathode and said gate are coplanar.
6. The GCT chip structure of claim 4, wherein the middle plane of the wave-shaped structure protrudes towards the first P + region, and the height of the protrusion is less than 40 μm.
7. The GCT chip structure of claim 1, wherein the second P + region has a thickness of 1-30 μ ι η.
8. A preparation method of a GCT chip structure is characterized by comprising the following steps:
step S11: forming a first P + region and a P base region on the cathode surface of the n-substrate by utilizing diffusion or deposition diffusion after ion implantation;
step S12: forming an n + buffer layer on the anode surface of the n-substrate by utilizing diffusion or deposition diffusion after ion implantation;
step S13: growing a second P + region in the first P + region by using a silicon epitaxial method;
step S14: forming an n-type doped region in the second P + region by using a selective ion implantation or selective deposition mode, and pushing through thermal diffusion to form an n + emitter;
step S15: diffusing or depositing and diffusing after ion implantation on the n + buffer layer to form a p + emitter;
step S16: and forming two-side metal electrode contact and patterning, wherein the metal electrode on the surface of the cathode is higher than the metal electrode on the surface of the gate.
9. A preparation method of a GCT chip structure is characterized by comprising the following steps:
step S21: forming a first P + region and a P base region on the cathode surface of the n-substrate by utilizing diffusion or deposition diffusion after ion implantation;
step S22: forming an n + buffer layer on the anode surface of the n-substrate by utilizing diffusion or deposition diffusion after ion implantation;
step S23: connecting the P-substrate or the SOI sheet with the cathode surface of the n-substrate which has finished the multi-step diffusion process by adopting the P-substrate or the SOI sheet through silicon-silicon bonding, and thinning to obtain a second P + region;
step S24: forming an n-type doped region in the second P + region by using a selective ion implantation or selective deposition mode, and pushing through thermal diffusion to form an n + emitter;
step S25: diffusing or depositing and diffusing after ion implantation on the n + buffer layer to form a p + emitter;
step S26: and forming two-side metal electrode contact and patterning, wherein the metal electrode on the surface of the cathode is higher than the metal electrode on the surface of the gate.
10. A preparation method of a GCT chip structure is characterized by comprising the following steps:
step S31: diffusing or depositing and diffusing the implanted ions on the cathode surface of the n-substrate to form a second P + region, a first P + region and a P base region;
step S32: forming an n + buffer layer on the anode surface of the n-substrate by utilizing diffusion or deposition diffusion after ion implantation;
step S33: forming an n-type doped region in the second P + region by using a selective ion implantation or selective deposition mode, and pushing through thermal diffusion to form an n + emitter;
step S34: diffusing or depositing and diffusing after ion implantation on the n + buffer layer to form a p + emitter;
step S35: and forming two-side metal electrode contact and patterning, wherein the metal electrode on the surface of the cathode is higher than the metal electrode on the surface of the gate.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111293113A (en) * | 2020-02-21 | 2020-06-16 | 电子科技大学 | SGTO device adopting single-layer metal process and layout structure and manufacturing method thereof |
| CN111739929A (en) * | 2020-06-30 | 2020-10-02 | 电子科技大学 | MOS grid-controlled thyristor reinforced by displacement radiation resistance |
| CN111739930A (en) * | 2020-06-30 | 2020-10-02 | 电子科技大学 | Ionization radiation resistant reinforced MOS grid-controlled thyristor |
| CN116387359A (en) * | 2023-06-02 | 2023-07-04 | 清华大学 | Reverse-resistance gate pole commutation thyristor and manufacturing method thereof |
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2019
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111293113A (en) * | 2020-02-21 | 2020-06-16 | 电子科技大学 | SGTO device adopting single-layer metal process and layout structure and manufacturing method thereof |
| CN111293113B (en) * | 2020-02-21 | 2023-01-10 | 电子科技大学 | SGTO device adopting single-layer metal process and layout structure and manufacturing method thereof |
| CN111739929A (en) * | 2020-06-30 | 2020-10-02 | 电子科技大学 | MOS grid-controlled thyristor reinforced by displacement radiation resistance |
| CN111739930A (en) * | 2020-06-30 | 2020-10-02 | 电子科技大学 | Ionization radiation resistant reinforced MOS grid-controlled thyristor |
| CN111739930B (en) * | 2020-06-30 | 2021-09-24 | 电子科技大学 | Ionization radiation resistant reinforced MOS grid-controlled thyristor |
| CN111739929B (en) * | 2020-06-30 | 2022-03-08 | 电子科技大学 | MOS grid-controlled thyristor reinforced by displacement radiation resistance |
| CN116387359A (en) * | 2023-06-02 | 2023-07-04 | 清华大学 | Reverse-resistance gate pole commutation thyristor and manufacturing method thereof |
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Application publication date: 20200103 Assignee: Beijing Qingneng Xinyan Technology Co.,Ltd. Assignor: TSINGHUA University Contract record no.: X2023980032243 Denomination of invention: GCT chip structure and preparation method Granted publication date: 20221223 License type: Common License Record date: 20230216 |