CN111739930A - Ionization radiation resistant reinforced MOS grid-controlled thyristor - Google Patents
Ionization radiation resistant reinforced MOS grid-controlled thyristor Download PDFInfo
- Publication number
- CN111739930A CN111739930A CN202010612345.8A CN202010612345A CN111739930A CN 111739930 A CN111739930 A CN 111739930A CN 202010612345 A CN202010612345 A CN 202010612345A CN 111739930 A CN111739930 A CN 111739930A
- Authority
- CN
- China
- Prior art keywords
- region
- well region
- cathode
- doping
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005855 radiation Effects 0.000 title claims description 18
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 239000002184 metal Substances 0.000 claims abstract description 39
- 229910052751 metal Inorganic materials 0.000 claims abstract description 39
- 230000005865 ionizing radiation Effects 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims description 24
- 238000005468 ion implantation Methods 0.000 claims description 16
- 239000012535 impurity Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 8
- 230000008569 process Effects 0.000 claims description 6
- 230000002146 bilateral effect Effects 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000005510 radiation hardening Methods 0.000 claims description 4
- 239000002019 doping agent Substances 0.000 claims description 3
- 230000004913 activation Effects 0.000 claims description 2
- 230000002787 reinforcement Effects 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 claims 1
- 238000006073 displacement reaction Methods 0.000 abstract description 2
- 230000000903 blocking effect Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 208000032750 Device leakage Diseases 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
- H01L29/745—Gate-turn-off devices with turn-off by field effect
- H01L29/7455—Gate-turn-off devices with turn-off by field effect produced by an insulated gate structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/749—Thyristor-type devices, e.g. having four-zone regenerative action with turn-on by field effect
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thyristors (AREA)
Abstract
The invention provides a MOS grid-controlled thyristor with ionizing radiation resistance, belonging to the technical field of power devices; the MOS grid-controlled thyristor comprises a metal cathode, a first well region, a second well region, a substrate, a third well region, an anode doping layer and a metal anode from top to bottom; the third well region is in short circuit with the metal anode to realize forward voltage resistance under the condition of zero grid voltage; the substrate and the third well region are homotype doped, and the doping concentration of the third well region is higher than that of the substrate; the second well region and the third well region are graded doped regions; the substrate is a low doped region. The device structure based on the invention can improve the displacement irradiation resistance of the MOS gate-controlled thyristor.
Description
Technical Field
The invention belongs to the technical field of power devices, and particularly relates to an ionization radiation reinforcement resistant MOS grid-controlled thyristor.
Background
The MOS gate Controlled Thyristor (MOS Controlled Thyristor, abbreviated as MCT) has the advantages of high current density, no current saturation effect, low on-state power consumption, high on-speed and the like, and is widely applied to the field of pulse power, such as a satellite device energy management system and the like. Under the condition of space radiation, an electronic product is irradiated by high-energy electrons, protons, heavy ions and other rays, and after the rays bombard an electronic device, ionization defects are introduced into an oxide layer. These defects can affect carrier behavior, degrading device electrical parameters, compromising the safety of the electronics system/device. The MOS grid-controlled thyristor is reinforced against the ionizing radiation damage, and has important significance for improving the on-orbit reliability of the satellite device.
The MOS gate-controlled thyristor is a composite device, the equivalent circuit of the MOS gate-controlled thyristor mainly comprises four basic structures, as shown in figure 2, an MOS structure (On-MOS) is started, an MOS structure (Off-MOS) is turned Off, an Upper triode structure (Upper-BJT) and a Lower triode (Lower-BJT) are turned On, the working principle of the MOS gate-controlled thyristor is that after a gate electrode is higher than an On-MOS threshold voltage, current carriers are injected into a substrate from a metal cathode, the Upper-BJT and the Lower-BJT enter a positive amplification state, and the sum of direct current gains of the Upper-BJT and the Lower-BJT (common base) of a conventional device is greater than 1, namely αupper+αlowerWhen the voltage applied to the gate electrode is higher than the threshold voltage of the OFF-MOS, the OFF-MOS is started, the current carrier in the substrate region is extracted from the second doped well region through the channel, the positive feedback in the thyristor is damaged, and the device is turned OFF, namely αupper+αlower<1. At this point, the anode of the device is able to withstand a high voltage of several thousand volts, entering the forward blocking state.
Ionization defects mainly include oxide layer charges and interface states. The positively charged oxide layer charges cause the threshold voltage of the device to drift negatively. Currently, MCT is mostly prepared by a thermal diffusion process, the doping concentration of an On-MOS channel (P-well region) is non-uniformly distributed, the doping concentration measured near an N-base region is low, and the MCT is in a forward blocking stateIn the following, most of the On-MOS channel (P-well region surface) is depleted, the channel length is short, and the negative shift of threshold voltage caused by irradiation will cause the leakage through the On-MOS channel to be significantly increased, and the Lower-BJT (common base) DC gain to be increasedupper+αlowerThe device is accidentally started, so that the action error of the system is caused, and the safety of the device is endangered. In order to avoid latch-up due to leakage, the high voltage applied to the anode needs to be reduced, and the withstand voltage of the device is reduced. Generally speaking, in order to increase the turn-On speed of the device, a lower threshold voltage is required, so that the doping concentration of an On-MOS channel in the conventional MCT is difficult to reduce, the tolerance of the conventional MCT to ionizing radiation is poor, and the doping concentration is only hundreds of Gy (SiO)2)。
The chinese patent document library discloses "a gate controlled thyristor with high current rise rate" (application No. 201710706916.2), "a gate controlled thyristor device for preventing turn-off failure" (application No. 201710707119.6), "a trench gate MOS controlled thyristor and its manufacturing method" (application No. 201810977983.2), "a MOS gate controlled thyristor and its manufacturing method" (application No. 201911037622.0). These patents are focused on improving the conventional electrical performance of the MOS-gated thyristor, and have not been concerned and discussed, the radiation resistance of the device.
Disclosure of Invention
The invention aims to solve the problems and provides a displacement radiation resistant reinforced MOS grid-controlled thyristor to prolong the service life of a device in a radiation environment.
In order to achieve the purpose, the technical scheme of the invention is as follows:
an anti-ionizing radiation reinforced MOS grid-controlled thyristor comprises a metal cathode 1, a first well region 5, a second well region 6, a substrate 7, an anode doping layer 9 and a metal anode 10 from top to bottom;
the gate 2, the gate oxide layer 3, the cathode doped region 4, the first well region 5, the second well region 6, the substrate 7, the surface doped region 8 and the anode doped layer 9 form a semiconductor chip of the device; the metal cathode 1 is contacted with the upper end face of the semiconductor chip; the cathode doped region 4 is positioned at two sides above the inner part of the first well region 5; the first well region 5 is positioned above the inner part of the second well region 6; the second well region 6 is positioned above the inner part of the substrate 7; the surface doped region 8 is positioned above the inner part of the second well region 6 and on two sides of the first well region 5; the cathode doped region 4, the first well region 5, the surface doped region 8 and part of the substrate 7 are exposed on the upper end face of the semiconductor chip; the semiconductor chip is of a bilateral symmetry structure, the metal cathode 1, the grid 2, the gate oxide layer 3, the cathode doped region 4, the first well region 5, the second well region 6, the substrate 7, the surface doped region 8, the anode doped layer 9 and the metal anode 10 are all bilateral symmetry around the center of the semiconductor chip, the metal cathode 1 is in contact with the inner area of the upper end face of the semiconductor chip, and the gate oxide layer 3 is in contact with the outer area of the upper end face of the semiconductor chip; the metal cathode 1 is in contact with the cathode doped region 4 and part of the surface area of the first well region 5; the gate oxide layer 3 is contacted with the surface areas of the substrate 7 and the surface doped region 8, and is contacted with the cathode doped region 4 and part of the surface of the first well region 5; the grid 2 is arranged in the gate oxide layer 3 and is not contacted with the metal cathode 1; the grid 2 covers the surface areas of the substrate 7 and the surface doped region 8, and covers the cathode doped region 4 and part of the surface area of the first well region 5;
the anode doping layer 9 and a part of the substrate 7 are exposed at the lower end face of the chip; the metal anode 10 is contacted with the lower end face of the semiconductor chip;
the first well region 5 and the substrate 7 are doped with the same type of impurities, and the cathode doped region 4, the second well region 6, the surface doped region 8 and the metal anode 10 are doped with the other type of impurities.
Preferably, the second well region 6 is short-circuited with the metal anode 10, that is, an anode short-circuit structure is adopted to suppress the dc gain of the triode at the lower part of the device, so that under the condition of gate open or zero gate voltage, the latch-up condition of the thyristor inside the device is not satisfied, and the device can bear forward high voltage.
Preferably, the doping concentration of the surface region of the surface doping region 8 is uniformly distributed.
Preferably, the surface doped region 8 is prepared by the following method,
1) after the first well region 5 is subjected to junction pushing, preparing a surface doping region 8 and a cathode doping region 4; doping the surface doping region 8 and the cathode doping region 4 by using an ion implantation process;
2) manufacturing a mask plate 11 on the surface of the chip, wherein one mask plate 11 is used in the ion implantation process; the mask plate 11 comprises through holes with two types of specifications, a single hole 12 and a plurality of holes 13; the single hole 12 is arranged above the cathode doped region 4 and is used for realizing doping ion implantation of the cathode doped region 4; the porous 13 is arranged above the surface doping region 8 and is used for realizing the doping ion implantation of the surface doping region 8; the multiple holes 13 are a group of through holes with different apertures and are arranged at equal intervals, and the diameters of the through holes are gradually reduced along the surface of the chip from the substrate 7 to the second well region 6;
3) implementing low-energy ion implantation to realize shallow junction doping;
4)800-1000 ℃ high-temperature dopant activation.
The invention has the beneficial effects that: the invention designs and realizes the surface doping region with uniformly distributed impurities, namely the channel of the On-MOS device, so that the length of the On-MOS channel is increased in a forward blocking state, the radiation leakage of the channel is inhibited, and the radiation damage resistance of the device is improved. The embodiment result shows that the invention can improve the ionization radiation damage resistance of the MOS gate-controlled thyristor by multiple times without obviously reducing the conventional electrical performance of the device.
Drawings
FIG. 1 is a MOS gated thyristor with radiation hardening resistance provided by the present invention;
FIG. 2 is a schematic diagram of an N-type MOS gated thyristor according to an embodiment of the invention;
FIG. 3 is a method for implementing an ionization radiation resistant reinforced MOS gated thyristor, a surface doped region 8 and a cathode doped region 4 according to the present invention;
FIG. 4 is the impurity concentration distribution of the On-MOS channel of the ionization radiation resistant MOS gated thyristor and the conventional MOS thyristor provided by the invention; the abscissa numerals in fig. 4, corresponding to the numerals in fig. 1, indicate the regions of the device;
in the figure, 1 is a metal cathode, 2 is a gate, 3 is a gate oxide, 4 is a cathode doped region, 5 is a first well region, 6 is a second well region, 7 is a substrate, 8 is a surface doped region, 9 is an anode doped layer, 10 is a metal anode, 11 is a mask plate, 12 is a single hole, and 13 is a plurality of holes.
Detailed Description
In fig. 2, four basic structures in the equivalent circuit of the device are marked, namely, a MOS structure (On-MOS) is started, a MOS structure (Off-MOS) is turned Off, an Upper triode structure (Upper-BJT) and a Lower triode structure (Lower-BJT).
As shown in fig. 1 and 2, the present embodiment provides an anti-ionizing radiation hardened MOS gated thyristor, which includes, from top to bottom, a metal cathode 1, a first well region 5, a second well region 6, a substrate 7, an anode doping layer 9, and a metal anode 10;
the gate 2, the gate oxide layer 3, the cathode doped region 4, the first well region 5, the second well region 6, the substrate 7, the surface doped region 8 and the anode doped layer 9 form a semiconductor chip of the device; the metal cathode 1 is contacted with the upper end face of the semiconductor chip; the cathode doped region 4 is positioned at two sides above the inner part of the first well region 5; the first well region 5 is positioned above the inner part of the second well region 6; the second well region 6 is positioned above the inner part of the substrate 7; the surface doped region 8 is positioned above the inner part of the second well region 6 and on two sides of the first well region 5; the cathode doped region 4, the first well region 5, the surface doped region 8 and part of the substrate 7 are exposed on the upper end face of the semiconductor chip; the semiconductor chip is of a bilateral symmetry structure, the metal cathode 1, the grid 2, the gate oxide layer 3, the cathode doped region 4, the first well region 5, the second well region 6, the substrate 7, the surface doped region 8, the anode doped layer 9 and the metal anode 10 are all bilateral symmetry around the center of the semiconductor chip, the metal cathode 1 is in contact with the inner area of the upper end face of the semiconductor chip, and the gate oxide layer 3 is in contact with the outer area of the upper end face of the semiconductor chip; the metal cathode 1 is in contact with the cathode doped region 4 and part of the surface area of the first well region 5; the gate oxide layer 3 is contacted with the surface areas of the substrate 7 and the surface doped region 8, and is contacted with the cathode doped region 4 and part of the surface of the first well region 5; the grid 2 is arranged in the gate oxide layer 3 and is not contacted with the metal cathode 1; the grid 2 covers the surface areas of the substrate 7 and the surface doped region 8, and covers the cathode doped region 4 and part of the surface area of the first well region 5;
the anode doping layer 9 and a part of the substrate 7 are exposed at the lower end face of the chip; the metal anode 10 is contacted with the lower end face of the semiconductor chip;
the first well region 5 and the substrate 7 are doped with the same type of impurities, and the cathode doped region 4, the second well region 6, the surface doped region 8 and the metal anode 10 are doped with the other type of impurities.
The second well region 6 is in short circuit with the metal anode 10, namely an anode short circuit structure is adopted, and direct current gain of a triode at the lower part of the device is inhibited, so that under the condition that a grid is open or zero grid voltage is generated, the latch-up condition of a thyristor inside the device is not met, and the device can bear forward high voltage.
The doping concentration of the surface region of the surface doping region 8 is uniformly distributed, and the thickness of the surface doping region 8 is about 500 nm;
as shown in fig. 3, the surface doped region 8 is prepared as follows,
1) after the first well region 5 is subjected to junction pushing, preparing a surface doping region 8 and a cathode doping region 4; doping the surface doping region 8 and the cathode doping region 4 by using an ion implantation process;
2) manufacturing a mask plate 11 on the surface of the chip, wherein one mask plate 11 is used in the ion implantation process; the mask plate 11 comprises through holes with two types of specifications, a single hole 12 and a plurality of holes 13; the single hole 12 is used for realizing doping ion implantation of the cathode doping region 4; the multiple holes 13 are used for realizing doping ion implantation of the surface doping region 8, the multiple holes 13 are a group of through holes with different apertures which are arranged at equal intervals, and the diameters of the through holes are gradually reduced along the surface of the chip from the substrate 7 to the second well region 6; in this embodiment, the plurality of holes 13 include 3 through holes arranged at equal intervals of 200nm, and the diameters of the 3 through holes of the plurality of holes 13 are 200nm, 50nm, and 20nm, respectively, along the chip surface from the substrate 7 to the second well region 6;
3) implementing 30keV low-energy boron ion implantation to realize shallow junction doping;
4) the dopant is activated at high temperature of 1000 ℃.
The grid control thyristor device can be a P-type grid control thyristor device or an N-type grid control thyristor device. In this embodiment, the MOS gate controlled thyristor is N-type.
The forward breakdown voltage of the device was approximately 1840V, the device triggered at an anode current of approximately 1.2mA, the trigger delay was approximately 80ns, the current rise rate was approximately 25kA/μ s, and the forward voltage drop under anode current 15A was approximately 1.9V. The experimental result of the cobalt source irradiation shows that the irradiation dose which can be endured by the device is about 1500Gy (SiO)2) At this point the device leakage is about 700 μ A. In the same-grade commercial device, the breakdown voltage is about 1860V, when the anode current is about 1.0mA, the device is triggered, the trigger delay is about 50ns, the current rising rate is about 30 kA/mu s, and the forward voltage drop under the condition of the anode current 15A is about 1.6V; the surface doping region 8 is non-uniformly distributed, and the impurity concentration is 1013-1016cm-3The irradiation dose that the device can withstand is about 500Gy (SiO)2) At this point, the device leakage is about 1.1 mA.
Taking an N-type MCT as an example, the working principle of the invention is illustrated as follows: the net doping in the surface doping region 8 is the result of the combined action of the doping from the substrate 7 and the doping from the surface doping region 8, the substrate 7 is formed by a thermal diffusion process, the doping of the substrate 7 close to the chip surface along the horizontal direction is non-uniformly distributed, and in order to obtain the uniformly doped surface doping region 8, a mask plate containing a plurality of holes 13 is designed to realize the regulation and control of the doping of the surface doping region 8. The multiple holes 13 are a group of through holes with different apertures and are arranged at equal intervals, the surface doping region 8 corresponds to a region of the large aperture through hole, more ion implantation doping can be obtained, the non-uniformity of the surface doping of the substrate 7 can be compensated, the uniformly doped surface doping region 8 is finally formed, the length reduction of an On-MOS channel caused by oxide layer charges (introduced by irradiation) is inhibited, the radiation leakage of the channel is inhibited, and the radiation damage resistance of the device is improved. The embodiment result shows that the invention can improve the ionization radiation damage resistance of the MOS gate-controlled thyristor by multiple times without obviously reducing the conventional electrical performance of the device.
While the present invention has been particularly shown and described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (4)
1. The utility model provides a MOS grid-controlled thyristor of anti ionization radiation reinforcement which characterized in that: the device comprises a metal cathode (1), a first well region (5), a second well region (6), a substrate (7), an anode doping layer (9) and a metal anode (10) from top to bottom;
the semiconductor chip of the device is composed of a grid (2), a grid oxide layer (3), a cathode doped region (4), a first well region (5), a second well region (6), a substrate (7), a surface doped region (8) and an anode doped layer (9); the metal cathode (1) is contacted with the upper end face of the semiconductor chip; the cathode doped region (4) is positioned at two sides above the inner part of the first well region (5); the first well region (5) is positioned above the inner part of the second well region (6); the second well region (6) is positioned above the inner part of the substrate (7); the surface doping region (8) is positioned above the inner part of the second well region (6) and on two sides of the first well region (5); the cathode doped region (4), the first well region (5), the surface doped region (8) and partial regions of the substrate (7) are exposed on the upper end face of the semiconductor chip; the semiconductor chip is of a bilateral symmetry structure, the metal cathode (1), the grid (2), the gate oxide layer (3), the cathode doped region (4), the first well region (5), the second well region (6), the substrate (7), the surface doped region (8), the anode doped layer (9) and the metal anode (10) are bilaterally symmetrical about the center of the semiconductor chip, the metal cathode (1) is in contact with the inner region of the upper end face of the semiconductor chip, and the gate oxide layer (3) is in contact with the outer region of the upper end face of the semiconductor chip; the metal cathode (1) is in contact with the cathode doped region (4) and part of the surface area of the first well region (5); the gate oxide layer (3) is in contact with the surface regions of the substrate (7) and the surface doped region (8) and is in contact with the cathode doped region (4) and part of the surface of the first well region (5); the grid (2) is arranged in the gate oxide layer (3) and is not contacted with the metal cathode (1); the grid (2) covers the surface areas of the substrate (7) and the surface doped region (8) and covers the cathode doped region (4) and part of the surface area of the first well region (5);
the anode doping layer (9) and a part of the substrate (7) are exposed at the lower end face of the chip; the metal anode (10) is in contact with the lower end face of the semiconductor chip;
the first well region (5) and the substrate (7) are doped with impurities of the same type, and the cathode doped region (4), the second well region (6), the surface doped region (8) and the metal anode (10) are doped with impurities of another type.
2. The ionizing radiation hardening resistant MOS gated thyristor of claim 1, wherein: the second well region (6) is in short circuit with the metal anode (10), namely an anode short circuit structure is adopted, and direct current gain of a triode at the lower part of the device is inhibited, so that under the condition that a grid is open or zero grid voltage is generated, the latch-up condition of a thyristor in the device is not met, and the device can bear forward high voltage.
3. The ionizing radiation hardening resistant MOS gated thyristor of claim 1, wherein: the doping concentration of the surface region of the surface doping region (8) is uniformly distributed.
4. The ionizing radiation hardening resistant MOS gated thyristor of claim 1, wherein: the preparation method of the surface doping area (8) is as follows,
1) after the first well region (5) is subjected to junction pushing, preparing a surface doped region (8) and a cathode doped region (4); doping the surface doping region (8) and the cathode doping region (4) by using an ion implantation process;
2) manufacturing a mask plate (11) on the surface of the chip, wherein one mask plate (11) is used in the ion implantation process; the mask plate (11) comprises through holes with two types of specifications, a single hole (12) and a plurality of holes (13); the single hole (12) is arranged above the cathode doped region (4) and is used for realizing the doping ion implantation of the cathode doped region (4); the porous hole (13) is arranged above the surface doping region (8) and is used for realizing doping ion implantation of the surface doping region (8); the multiple holes (13) are a group of through holes with different apertures and are arranged at equal intervals, and the diameters of the through holes are gradually reduced along the surface of the chip from the substrate (7) to the second well region (6);
3) implementing low-energy ion implantation to realize shallow junction doping;
4)800-1000 ℃ high-temperature dopant activation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010612345.8A CN111739930B (en) | 2020-06-30 | 2020-06-30 | Ionization radiation resistant reinforced MOS grid-controlled thyristor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010612345.8A CN111739930B (en) | 2020-06-30 | 2020-06-30 | Ionization radiation resistant reinforced MOS grid-controlled thyristor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111739930A true CN111739930A (en) | 2020-10-02 |
| CN111739930B CN111739930B (en) | 2021-09-24 |
Family
ID=72653700
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010612345.8A Active CN111739930B (en) | 2020-06-30 | 2020-06-30 | Ionization radiation resistant reinforced MOS grid-controlled thyristor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111739930B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20210408265A1 (en) * | 2020-06-24 | 2021-12-30 | Electronics And Telecommunications Research Institute | Metal oxide semiconductor-controlled thyristor device having uniform turn-off characteristic and method of manufacturing the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5629535A (en) * | 1994-07-08 | 1997-05-13 | International Rectifier Corporation | Bidirectional thyristor with MOS turn-on and turn-off capability |
| CN106663693A (en) * | 2014-06-27 | 2017-05-10 | 三菱电机株式会社 | Silicon carbide semiconductor device |
| CN107452790A (en) * | 2017-08-16 | 2017-12-08 | 全球能源互联网研究院 | A kind of power semiconductor and preparation method thereof |
| CN110649094A (en) * | 2019-09-19 | 2020-01-03 | 清华大学 | GCT chip structure and preparation method thereof |
-
2020
- 2020-06-30 CN CN202010612345.8A patent/CN111739930B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5629535A (en) * | 1994-07-08 | 1997-05-13 | International Rectifier Corporation | Bidirectional thyristor with MOS turn-on and turn-off capability |
| CN106663693A (en) * | 2014-06-27 | 2017-05-10 | 三菱电机株式会社 | Silicon carbide semiconductor device |
| CN107452790A (en) * | 2017-08-16 | 2017-12-08 | 全球能源互联网研究院 | A kind of power semiconductor and preparation method thereof |
| CN110649094A (en) * | 2019-09-19 | 2020-01-03 | 清华大学 | GCT chip structure and preparation method thereof |
Non-Patent Citations (1)
| Title |
|---|
| LEI LI, ET AL: "Experimental Study on Displacement Damage Effects of Anode-Short MOS-Controlled Thyristor", 《IEEE TRANSACTIONS ON NUCLEAR SCIENCE》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20210408265A1 (en) * | 2020-06-24 | 2021-12-30 | Electronics And Telecommunications Research Institute | Metal oxide semiconductor-controlled thyristor device having uniform turn-off characteristic and method of manufacturing the same |
| US11637192B2 (en) * | 2020-06-24 | 2023-04-25 | Electronics And Telecommunications Research Institute | Metal oxide semiconductor-controlled thyristor device having uniform turn-off characteristic and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111739930B (en) | 2021-09-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9870923B2 (en) | Semiconductor device and method of manufacturing the semiconductor device | |
| US7233031B2 (en) | Vertical power semiconductor component | |
| US7932583B2 (en) | Reduced free-charge carrier lifetime device | |
| EP2654084B1 (en) | Method of manufacturing a semiconductor device | |
| CN110504310B (en) | RET IGBT with self-bias PMOS and manufacturing method thereof | |
| SE542607C2 (en) | MOSFET in SiC with self-aligned lateral MOS channel | |
| CN111863606B (en) | Anti-radiation power transistor and preparation method thereof | |
| CN104078509A (en) | Power MOS device with single-particle burnout resistance | |
| CN110429077B (en) | Single-particle burnout resistant structure suitable for power semiconductor device | |
| CN111129119B (en) | Single particle reinforcement device structure of silicon carbide MOS and preparation method thereof | |
| CN114709263A (en) | Power VDMOS device capable of resisting single event effect grid damage | |
| CN111933705A (en) | Manufacturing method of power semiconductor device and power semiconductor device | |
| CN111739930B (en) | Ionization radiation resistant reinforced MOS grid-controlled thyristor | |
| CN112397593B (en) | Semiconductor device and method of manufacturing the same | |
| CN110610995A (en) | Half-cell structure of grid power MOSFET anti-single-particle-burning device | |
| JP4031209B2 (en) | Semiconductor device | |
| US4238761A (en) | Integrated gate assisted turn-off, amplifying gate thyristor with narrow lipped turn-off diode | |
| CN110212027B (en) | Electron injection enhanced dual-mode MOS control thyristor and manufacturing method thereof | |
| CN114695519B (en) | Groove type silicon carbide IGBT device with shielding layer state automatically switched and preparation method | |
| US4040170A (en) | Integrated gate assisted turn-off, amplifying gate thyristor, and a method for making the same | |
| WO2014086075A1 (en) | Igbt structure and manufacturing method thereof | |
| CN116230770A (en) | Silicon carbide MOSFET device of Schottky junction assisted depletion ballast resistor and preparation method | |
| Luther-King et al. | Striped anode engineering: A concept for fast switching power devices | |
| CN111697059B (en) | MOS grid-controlled thyristor reinforced by anti-displacement radiation | |
| CN111739929B (en) | MOS grid-controlled thyristor reinforced by displacement radiation resistance |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |