CN111293113B - SGTO device adopting single-layer metal process and layout structure and manufacturing method thereof - Google Patents
SGTO device adopting single-layer metal process and layout structure and manufacturing method thereof Download PDFInfo
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- 239000002184 metal Substances 0.000 title claims abstract description 207
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 207
- 238000000034 method Methods 0.000 title claims abstract description 65
- 230000008569 process Effects 0.000 title claims abstract description 59
- 239000002356 single layer Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 44
- 239000010410 layer Substances 0.000 claims abstract description 40
- 238000005530 etching Methods 0.000 claims abstract description 19
- 238000005468 ion implantation Methods 0.000 claims description 24
- SWZLHQKRIGCCEU-UHFFFAOYSA-N (1-dodecylpyridin-2-ylidene)methyl-oxoazanium;iodide Chemical compound [I-].CCCCCCCCCCCC[N+]1=CC=CC=C1\C=N\O SWZLHQKRIGCCEU-UHFFFAOYSA-N 0.000 claims description 23
- 210000004027 cell Anatomy 0.000 claims description 23
- 238000002161 passivation Methods 0.000 claims description 19
- 239000012535 impurity Substances 0.000 claims description 14
- 238000002347 injection Methods 0.000 claims description 8
- 239000007924 injection Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 238000001465 metallisation Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 210000003850 cellular structure Anatomy 0.000 claims description 5
- 230000004913 activation Effects 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 abstract description 9
- 230000008021 deposition Effects 0.000 abstract description 2
- 230000001960 triggered effect Effects 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000001413 cellular effect Effects 0.000 description 2
- 238000000742 single-metal deposition Methods 0.000 description 2
- VMXJCRHCUWKQCB-UHFFFAOYSA-N NPNP Chemical compound NPNP VMXJCRHCUWKQCB-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
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Abstract
The invention relates to a power semiconductor technology, in particular to an SGTO device adopting a single-layer metal process, a layout structure and a manufacturing method thereof. The invention mainly adopts a single-layer metal process on the basis of a conventional SGTO device board diagram and process, a grid metal and a cathode metal diagram are made on the same metal layer, and the front grid and cathode metal diagram is simultaneously finished through a single deposition and etching process. Through reasonable layout structure layout, the manufacturing process of the device is simplified under the condition of not sacrificing the conduction performance of the device, the reliability of the device is improved, and the commercialization of the SGTO device is facilitated.
Description
Technical Field
The invention relates to a power semiconductor technology, in particular to an SGTO device adopting a single-layer metal process, a layout structure and a manufacturing method thereof.
Background
The power semiconductor device is used as a switching device and can be applied to two aspects of the power electronic field and the pulse power field. GTO (Gate Turn-Off Thyristor) is used as a device with high voltage resistance, low conduction voltage drop, high current density and high reliability, and is particularly suitable for the field of pulse power. Because the traditional GTO device has a loose unit structure and a low power density, in order to meet the demand of miniaturization of the device, SGTO (Super Gate Turn-off Thyristor) devices have been produced. The biggest difference between the SGTO device and the conventional GTO device lies in the process change and the cell size reduction, which brings the advantages of greatly improved power density and greatly reduced device size.
For the SGTO device applied in the field of pulse power, because the instantaneous power density of the device is large, and a large current needs to flow in a small chip area, if the conduction of the device is inconsistent, the device is easy to fail or even burn out, so how to reasonably design the cell structure and layout of the device, and thus, the uniform conduction of each cell of the device becomes a key problem. In order to solve the problem, the traditional SGTO adopts a double-layer metal process, wherein a gate metal electrode and a cathode metal electrode are formed by two metal deposition and etching processes, and the two metal deposition and etching processes are separated by an insulating medium. By adopting the method, the cells of the device can be uniformly distributed, but because metal etching is required twice, an additional mask and process steps are required, and the additional process cost is increased. Meanwhile, due to the increase of the process steps, the device is damaged in the processing process, the contamination risk is increased, and the yield and the reliability of the device are reduced.
Disclosure of Invention
The invention aims to solve the problem that the conventional SGTO cannot be well applicable to a single-layer metal process of a conventional power device due to design limitation, and provides an SGTO device adopting the single-layer metal process, a layout structure and a manufacturing method thereof, which are applicable to the current commercialized main process.
In order to achieve the purpose, the invention adopts the following technical scheme:
a single-layer metal technology adopted SGTO device comprises a cell structure, a metal layer and a metal layer, wherein the cell structure comprises an anode structure, a drift region structure, a P-type base region structure, a cathode structure, a gate structure and a surface passivation structure; the anode structure comprises a P + anode (107) and an anode metal electrode (108) positioned on the lower surface of the P + anode (107); the drift region structure comprises an N-type semiconductor drift region (106) located on the upper surface of a P + anode (107); the P-type base region structure comprises a P-type semiconductor base region (105) positioned on the upper surface of an N-type semiconductor drift region (106); the cathode structure comprises an N + cathode heavily doped region (103) positioned on the upper surface of the P-type semiconductor base region (105) and a cathode metal electrode (102) contacted with the upper surface of the N + cathode heavily doped region (103); the gate structure comprises a P + gate heavily doped region (104) positioned on the upper surface of the P-type semiconductor base region (105) and a gate metal electrode (101) contacted with the upper surface of the P + gate heavily doped region (104); the surface passivation structure comprises an insulating medium and a passivation layer (109) on the surface of the device; the method is characterized in that the gate metal electrode (101) and the cathode metal electrode (102) are positioned on the same metal layer, are formed by one-time metal deposition and etching process and are isolated from a passivation layer (109) by an insulating medium;
furthermore, the width of the device cell structure is 100-200 microns;
furthermore, the thickness of a P-type semiconductor base region (105) in the device cellular structure is 3-5 micrometers;
furthermore, the thickness of the N + cathode heavily doped region (103) in the device cellular structure is 0.5-1 micron;
furthermore, the thickness of a P + gate heavily doped region (104) in the device cellular structure is 1-3 microns;
the layout structure of the SGTO device adopting the single-layer metal process comprises a gate metal area, a cathode metal area, an N + cathode ion implantation area (206) and a P + gate ion implantation area (207); the gate metal region comprises a gate metal electrode (201), a gate bus (202) and a gate metal PAD (203); the cathode metal region comprises a cathode metal electrode (204) and a cathode metal PAD (205); the gate metal area and the cathode metal area are positioned on the same metal layer, and are formed by one-time metal etching and are isolated from the passivation layer through an insulating medium; the cathode metal PAD (205) is an exposed metal layer and is arranged in the center of the layout and used for externally connecting a cathode lead; the cathode metal electrodes (204) are distributed on two sides of the cathode metal PAD (205) in an interdigital manner; the gate metal PAD (203) is an exposed metal layer and is arranged at the lower left corner of the layout and used for externally connecting a gate lead; the gate bus (202) surrounds the edge of the layout for a circle and connects the gate metal electrode (201) with the gate metal PAD (203); the gate metal electrodes (201) are distributed on two sides of the cathode metal PAD (205) in an interdigital manner and are alternately arranged with the cathode metal electrodes (201); the N + cathode ion implantation area (206) comprises a cathode metal electrode (204) area and a cathode metal PAD (205) area surrounded by the extension line of the cathode metal electrode (204); said P + gate ion implantation regions (207) are distributed around the N + cathode ion implantation regions (206) at a distance therefrom;
furthermore, the width of the interdigital of the cathode metal electrode (204) and the interdigital of the gate metal electrode (201) which are distributed in an interdigital way corresponds to the size of the gate metal electrode (101) and the cathode metal electrode (102) in the cellular structure of the device;
furthermore, the interdigital width of the cathode metal electrodes (204) distributed in an interdigital way is 85-170 micrometers;
furthermore, the cathode metal electrodes (204) distributed in an interdigital way are all covered by the N + cathode ion implantation area (206), and the cathode metal electrodes (204) distributed in an up-down opposite way relative to the cathode metal PAD (205) are covered by the same N + cathode ion implantation area (206);
furthermore, the interdigital width of the gate metal electrode (201) distributed in an interdigital way is 10-20 microns;
further, the gate metal regions are all covered by a P + gate ion implantation region (207);
further, the dimensions of the cathode metal PAD (205) and the gate metal PAD (203) correspond to the minimum dimension meeting the requirements of a packaging lead;
the technical scheme of the invention is mainly to rearrange the device cells through reasonable layout structure design, reserve cathode metal PAD and gate metal PAD for external leads in the middle and lower left corner regions of the layout respectively, and arrange gate metal and cathode metal with interdigital structures in the device cell region. On the premise of not sacrificing the conduction performance of the device, the device process is compatible with the single-layer metal process, the process steps are reduced, the process cost is reduced, and the yield and the reliability of the device are improved.
The SGTO device manufacturing method adopting the single-layer metal process further comprises the following steps:
the first step is as follows: manufacturing a junction terminal by using a substrate silicon wafer to form an N-type semiconductor drift region (106);
the second step is that: injecting P-type impurities into the upper surface of the N-type semiconductor drift region (106) and performing junction pushing to form a P-type semiconductor base region (105);
the third step: injecting P-type impurities into a P + gate electrode ion injection region (207) on the surface of the P-type semiconductor base region and performing junction pushing to form a P-type gate electrode heavily doped region (104);
the fourth step: injecting N-type impurities into an N + cathode ion injection region (206) on the surface of the P-type semiconductor base region and pushing the N-type impurities to form an N-type cathode heavily doped region (103);
the fifth step: depositing and etching metal on the upper surface of the device to form a gate metal area and a cathode metal area;
and a sixth step: depositing and etching an insulating medium and a passivation layer on the upper surface of the device to form a gate metal PAD (203) and a cathode metal PAD (205);
the seventh step: injecting P-type impurities into the lower surface of the N-type semiconductor drift region and performing ion activation to form a P + anode (107);
eighth step: back gold, forming anode metal (108) at the bottom of the P + anode (107);
further, the metal deposition and etching process in the fifth step is a single metal deposition and etching process, and the gate metal and the cathode metal are located in the same metal layer.
The invention has the beneficial effects that the SGTO device structure, the layout structure and the manufacturing process which adopt the single-layer metal process are provided, the problems that the traditional SGTO device manufacturing process is complex, high in cost and incompatible with the mainstream single-layer metal process are solved, the device manufacturing process is simplified under the condition of not sacrificing the conduction performance of the device, and the SGTO device is beneficial to commercialization.
Drawings
FIG. 1 is a schematic diagram of a cell structure of an SGTO device using a single-layer metal process according to the present invention;
FIG. 2 is a schematic diagram of an SGTO layout structure using a single-layer metal process according to the present invention;
FIG. 3 is a schematic diagram of a cross-sectional line of an SGTO layout using a single-layer metal process according to the present invention;
FIG. 4 is a cross-sectional view of an SGTO device using a single layer metal process taken along section line AA' according to an embodiment;
FIG. 5 is a schematic cross-sectional view of an SGTO device using a single layer metal process along the cross-sectional line BB' according to an embodiment; (ii) a
FIG. 6 is a schematic cross-sectional view of an SGTO device using a single layer metal process taken along section line CC' according to an embodiment; (ii) a
FIG. 7 is a schematic cross-sectional view of an SGTO device using a single layer metal process taken along section line DD' according to one embodiment; (ii) a
Detailed Description
The technical scheme of the invention is described in detail in the following with reference to the accompanying drawings and embodiments:
fig. 1 is a schematic structural diagram of an SGTO device cell adopting a single-layer metal process, the device is manufactured by a planar process, and each doped region is realized by ion implantation, which is beneficial to controlling junction depth and doping concentration. The gate metal electrode (101) and the cathode metal electrode (102) are formed by a single metal deposition and etching process and are separated from the passivation layer (109) by an insulating medium. When the device works normally, the device is equivalent to a double-transistor model, namely a PNP tube consisting of the P + anode (107), the N-type semiconductor drift region (106) and the P-type semiconductor base region (105) is arranged on the upper layer, and an NPN tube consisting of the N-type semiconductor drift region (106), the P-type semiconductor base region (105) and the N + cathode heavily doped region (103) is arranged on the lower layer. Assuming that the common-base current gains of the two transistors are α 1 (pnp) and α 2 (npn), respectively, a forward voltage is applied between the anode and the cathode. If the gate injects a sufficiently large negative current, positive feedback between the two transistors can be triggered, where the common-base current gains α 1 and α 2 increase as the current between the anode and cathode increases. When alpha 1+ alpha 2 ≧ 1 is satisfied, SGTO is turned on. In contrast, when a positive current of sufficient magnitude is injected at the gate to trigger the negative feedback process of SGTO, the current between the anode and the cathode will decrease continuously, and when α 1+ α 2 < 1 is satisfied, the device is turned off. In the field of pulse power, the device is required to flow a large current in a short time after being turned on, so that the conduction uniformity in the initial turn-on period of the device is a very critical problem. The conventional thyristor generally uses a mesa process, the P-type semiconductor base region and the N + cathode heavily doped region are realized through a diffusion process, the precision is low, and meanwhile, the whole silicon wafer is used as a single device, the internal consistency of the silicon wafer is poor, and the silicon wafer cannot bear large di/dt. Different from the conventional thyristor, the SGTO device adopting the single-layer metal process provided by the invention adopts a planar process, the P-type semiconductor base region (105), the N + cathode heavily doped region (103) and the P + gate heavily doped region (104) of the device are all realized by using an ion implantation process, the junction depth is shallow, the adjustment precision of the doping concentration is high, and the SGTO device is very suitable for being applied to the field of pulse power. Meanwhile, the device has smaller cell width, so that the conduction area of the device is very uniform at the initial starting stage, each cell is uniformly started, and the pulse performance and the reliability of the device are improved.
Fig. 2 is a schematic diagram of an SGTO layout structure using a single-layer metal process according to the present invention, which mainly includes a gate metal region, a cathode metal region, an N + cathode ion implantation region (206), and a P + gate ion implantation region (207). Wherein the gate metal region comprises a gate metal electrode (201), a gate bus (202) and a gate metal PAD (203), and the cathode metal region comprises a cathode metal electrode (204) and a cathode metal PAD (205). The gate metal region and the cathode metal region are the same layer of metal, and are different from external electrodes, metal patterns are formed through one-time metal deposition and etching processes, and are separated through an insulating medium and a passivation layer. The N + cathode ion implantation region (206) and the P + gate ion implantation region (207) are used for defining an ion implantation window, and N-type and P-type ion implantation is carried out in corresponding regions to form an N-type cathode heavily doped region (103) and a P-type gate heavily doped region (104) in the device structure. The layout is integrally arranged in a strip-shaped cellular form, and the N + cathode ion injection region (206) and the P + gate ion injection region (207) correspond to the N-type cathode heavily doped region (103) and the P-type gate heavily doped region (104) in the device structure. The gate metal electrode (201) and the cathode metal electrode (204) correspond to the cathode metal electrode and the gate metal electrode in the cellular region, are cut off by the cathode PAD region in the middle of the layout, and are divided into two parts which are symmetrical up and down. In the area corresponding to the gate PAD, no cells are distributed below the cathode PAD. The insulating medium and the passivation layer on the surface of the metal layer in the cathode PAD and gate PAD areas are etched, and the metal layer is directly exposed to serve as a connecting area of a lead and is connected with an external electrode. When the device normally works, a current signal is applied through the gate electrode to trigger the device to be conducted, the current signal is uniformly transmitted to the gate metal electrode (201) through the gate metal PAD (203) and the gate bus (202), and the thyristor structure below the adjacent cathode metal electrode (204) is triggered to be conducted. Because the gate metal electrode (201) and the cathode metal electrode (204) which are distributed in an interdigital way are adopted, and a gate bus (202) structure is arranged, the conduction uniformity of the device is good, and the cell area in the whole chip can be effectively conducted.
Fig. 3 is a schematic diagram of cross-sectional lines of an SGTO layout structure using a single-layer metal process, wherein directions AA ', BB', CC ', and DD' are cell region cross-sectional lines, cathode metal PAD region cross-sectional lines, cathode metal electrode region cross-sectional lines, and gate metal electrode region cross-sectional lines, respectively. The layout structure and the working principle of the present invention are further illustrated by the internal structure of the semiconductor in these four directions in one embodiment.
Fig. 4 to 7 are schematic cross-sectional views of an SGTO device using a single-layer metal process along different directions of the layout structure of the present invention according to an embodiment of the present invention.
Fig. 4 is a schematic cross-sectional view taken along a cross-sectional line AA' shown in fig. 3, which shows an internal structure of the device cell region. As can be seen from the figure, the semiconductor surface covered by the gate metal electrode is a P-type gate heavily doped region, and the semiconductor surface covered by the cathode metal electrode is an N-type cathode heavily doped region. The device cell areas are distributed in the form of strip-shaped cells, and the surfaces of the device cell areas are covered by the dielectric layer and the passivation layer. When the device is started, the NPNP thyristor below the cathode metal electrode is triggered to be conducted by electrons injected by the adjacent gate metal electrode.
Fig. 5 is a schematic cross-sectional view taken along a cross-sectional line BB' shown in fig. 3, showing an internal structure of a cathode metal PAD region of the device. Different from the device cell area, the cell surface below the cathode metal PAD area is covered by the cathode metal PAD, a P-type gate heavily doped area of the area is in short circuit with an N + source area, when the device is started, the thyristor structure around the area is triggered to start by losing injected electrons, and the thyristor structure in the area is mainly triggered to be conducted by gate metal electrodes at two sides of the cathode metal PAD and close to the PAD area.
Fig. 6 is a schematic cross-sectional view taken along the cross-sectional line CC' shown in fig. 3, illustrating the internal structure at the fingers of a single cathode electrode of the device. As can be seen from the figure, the interdigital of the cathode metal electrode of the device and the PAD area of the cathode metal are positioned on the same metal layer and are directly connected, and the N + source areas are arranged on the surface of the semiconductor below the metal layer. The edge of the layout is of a gate electrode bus structure, a P-type gate electrode heavily doped region is arranged below the gate electrode bus, and gate electrode bus metal and a cathode metal electrode are isolated from each other through a dielectric layer and a passivation layer.
Fig. 7 is a schematic cross-sectional view taken along the sectional line DD' shown in fig. 2, which shows the internal structure of the device at the intersection of the individual gate metal electrodes. As can be seen from the figure, the interdigital of the device gate metal electrode comprises the semiconductor region surface below the extension line of the interdigital of the device gate metal electrode, and the surface is a heavily doped region of a P-type gate. The gate metal electrodes on two sides are isolated from the cathode metal PAD metal through a dielectric layer and a passivation layer.
The specific implementation steps for implementing the scheme are as follows:
the first step is as follows: manufacturing a junction terminal by using a substrate silicon wafer to form an N-type semiconductor drift region (106);
the second step is that: injecting P-type impurities into the upper surface of the N-type semiconductor drift region (106) and performing junction pushing to form a P-type semiconductor base region (105);
the third step: injecting P-type impurities into a P + gate electrode ion injection region (207) on the surface of the P-type semiconductor base region and performing junction pushing to form a P-type gate electrode heavily doped region (104);
the fourth step: injecting N-type impurities into an N + cathode ion injection region (206) on the surface of the P-type semiconductor base region and pushing the N-type impurities to form an N-type cathode heavily doped region (103);
the fifth step: depositing and etching metal on the upper surface of the device to form a gate metal area and a cathode metal area;
and a sixth step: depositing and etching an insulating medium and a passivation layer on the upper surface of the device to form a gate metal PAD (203) and a cathode metal PAD (205);
the seventh step: injecting P-type impurities into the lower surface of the N-type semiconductor drift region and carrying out ion activation to form a P + anode (107);
eighth step: and back gold, and forming anode metal (108) at the bottom of the P + anode (107).
The core idea of the technical scheme is that the original double-layer metal process of the SGTO is changed into a single-layer metal process, gate metal and cathode metal electrode patterns are made on the same metal layer, and front gate metal and cathode metal electrode patterning is finished simultaneously through a single deposition and etching process. Therefore, the process complexity is reduced, the device manufacturing process is simplified under the condition of not sacrificing the conduction performance of the device, the reliability of the device is improved, and the commercialization of the SGTO device is facilitated.
Claims (10)
1. The SGTO device adopting the single-layer metal process has a cellular structure comprising an anode structure, a drift region structure, a P-type base region structure, a cathode structure, a gate structure and a surface passivation structure; the anode structure comprises a P + anode (107) and an anode metal electrode (108) positioned on the lower surface of the P + anode (107); the drift region structure is an N-type semiconductor drift region (106) located on the upper surface of a P + anode (107); the P-type base region structure is a P-type semiconductor base region (105) positioned on the upper surface of the N-type semiconductor drift region (106); the cathode structure comprises an N + cathode heavily doped region (103) positioned at one end of the upper surface of the P-type semiconductor base region (105) and a cathode metal electrode (102) contacted with the upper surface of the N + cathode heavily doped region (103); the gate structure comprises a P + gate heavily doped region (104) positioned at the other end of the upper surface of the P-type semiconductor base region (105) and a gate metal electrode (101) contacted with the upper surface of the P + gate heavily doped region (104); the surface passivation structure comprises an insulating medium and a passivation layer (109) positioned on the surface of the device; the method is characterized in that the gate metal electrode (101) and the cathode metal electrode (102) are positioned on the same metal layer, are formed through one-time metal deposition and etching process, and are separated from a passivation layer (109) through an insulating medium.
2. An SGTO device using single layer metal process as claimed in claim 1 wherein said cell structure width is 100 to 200 microns.
3. An SGTO device using single layer metal process according to claim 1, wherein the P-type semiconductor base region (105) has a thickness of 3 to 5 microns.
4. An SGTO device using single layer metal process according to claim 1, characterized in that the N + cathode heavily doped region (103) has a thickness of 0.5 to 1 μm.
5. The SGTO device of claim 1 wherein said P + gate heavily doped region (104) has a thickness of 1 to 3 microns.
6. The layout structure of the SGTO device adopting the single-layer metal process comprises a gate metal area, a cathode metal area, an N + cathode ion implantation area (206) and a P + gate ion implantation area (207); the gate metal region comprises a gate metal electrode (201), a gate bus (202) and a gate metal PAD (203); the cathode metal region comprises a cathode metal electrode (204) and a cathode metal PAD (205); the gate metal area and the cathode metal area are positioned on the same metal layer, and are formed by one-time metal etching and are isolated from the passivation layer through an insulating medium; the cathode metal PAD (205) is an exposed metal layer and is arranged in the center of the layout and used for externally connecting a cathode lead; the cathode metal electrodes (204) are distributed on two sides of the cathode metal PAD (205) in an interdigital manner; the gate metal PAD (203) is an exposed metal layer and is arranged at the lower left corner of the layout and used for externally connecting a gate lead; the gate bus (202) surrounds the edge of the layout for a circle and connects the gate metal electrode (201) with the gate metal PAD (203); the gate metal electrodes (201) are distributed on two sides of the cathode metal PAD (205) in an interdigital manner and are alternately arranged with the cathode metal electrodes (201); the N + cathode ion implantation area (206) comprises a cathode metal electrode (204) area and a cathode metal PAD (205) area surrounded by the extension line of the cathode metal electrode (204); the P + gate ion implantation regions (207) are distributed around and spaced apart from the N + cathode ion implantation regions (206).
7. An SGTO device layout structure adopting a single-layer metal process as claimed in claim 6, wherein the interdigital width of the cathode metal electrodes (204) distributed like an interdigital is 85 to 170 micrometers.
8. The SGTO device layout structure adopting the single-layer metal process as claimed in claim 6, wherein the cathode metal electrodes (204) distributed in an interdigital manner are all covered by an N + cathode ion implantation region (206), the cathode metal electrodes (204) distributed oppositely on two sides of the cathode metal PAD (205) are covered by the same N + cathode ion implantation region (206), and the interdigital width of the gate metal electrodes (201) distributed in an interdigital manner is 10-20 microns.
9. An SGTO device layout structure employing single-layer metal process according to claim 6, characterized in that the gate metal regions are all covered by a P + gate ion implantation region (207).
10. The manufacturing method of the SGTO device by adopting the single-layer metal process is characterized by comprising the following steps of:
the first step is as follows: manufacturing a junction terminal by using a substrate silicon wafer to form an N-type semiconductor drift region (106);
the second step is that: injecting P-type impurities into the upper surface of the N-type semiconductor drift region (106) and performing junction pushing to form a P-type semiconductor base region (105);
the third step: injecting P-type impurities into a P + gate electrode ion injection region (207) on the surface of the P-type semiconductor base region and performing junction pushing to form a P-type gate electrode heavily doped region (104);
the fourth step: injecting N-type impurities into an N + cathode ion injection region (206) on the surface of the P-type semiconductor base region and performing junction pushing to form an N-type cathode heavily doped region (103);
the fifth step: depositing and etching metal on the upper surface of the device to form a gate metal area and a cathode metal area;
and a sixth step: depositing and etching an insulating medium and a passivation layer on the upper surface of the device to form a gate metal PAD (203) and a cathode metal PAD (205);
the seventh step: injecting P-type impurities into the lower surface of the N-type semiconductor drift region and carrying out ion activation to form a P + anode (107);
eighth step: back gold, an anode metal (108) is formed at the bottom of the P + anode (107).
Priority Applications (1)
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