CN103794645A - IGBT device and manufacturing method thereof - Google Patents
IGBT device and manufacturing method thereof Download PDFInfo
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- CN103794645A CN103794645A CN201210426232.4A CN201210426232A CN103794645A CN 103794645 A CN103794645 A CN 103794645A CN 201210426232 A CN201210426232 A CN 201210426232A CN 103794645 A CN103794645 A CN 103794645A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
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Abstract
The embodiment of the invention discloses an IGBT device, wherein a first N-type buffer layer, a second N-type buffer layer and a third N-type buffer layer are sequentially arranged on the back surface of an N-type base region of the IGBT device, doped impurities of the first N-type buffer layer are fifth main group element ions, the impurity concentration of the first N-type buffer layer is greater than that of the N-type base region, doped impurities of the second N-type buffer layer are sixth main group element ions, the impurity concentration of the second N-type buffer layer is greater than that of the N-type base region and smaller than that of the first N-type buffer layer, the doped impurities of the third N-type buffer layer are fifth main group element ions, and the impurity concentration of the third N-type buffer layer is greater than that of the first N-type buffer layer. The three buffer layers can respectively and independently optimize relevant characteristics of the IGBT device, obtain a better compromise curve of connection and disconnection, further optimize the switching characteristics of the IGBT, and accordingly improve the overall performance of the IGBT device.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly, relate to a kind of IGBT device and preparation method thereof.
Background technology
Insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, be called for short IGBT) the compound full-control type voltage driven type power semiconductor that formed by double pole triode (BJT) and insulating gate type field effect tube (MOSFET), the high input impedance and the power transistor that have MOSFET device concurrently (are huge transistor, be called for short GTR) the advantage of low conduction voltage drop two aspects, reduce because IGBT has advantages of the little and saturation pressure of driving power, IGBT is widely applied to every field as a kind of novel power electronic device at present.
The IGBT device of existing routine adopts the preparation of zone melting single-crystal silicon substrate.Under blocking-up condition, its electric field is leg-of-mutton distribution in N-type base region, its blocking voltage is along with N-type base region thickness increases and increases, and along with N-type base region thickness increases, its forward conduction voltage drop also can increase, and the turn-off time of described IGBT device also can increase, therefore, the performance of conventional IGBT device is unsatisfactory.
In addition, also has a kind of electric field blocking-up type IGBT device, compared with conventional IGBT device, electric field blocking-up type IGBT device is provided with N-type resilient coating between collector region and base region, using as electric field barrier layer, the thickness of N-type base region can be under identical blocking voltage, reduced, thereby forward conduction voltage drop and turn-off time can be reduced, but electric field blocking-up type IGBT device or not ideal enough.
Summary of the invention
The embodiment of the present invention provides a kind of IGBT device and preparation method thereof, to improve the performance of IGBT device.
For achieving the above object, the invention provides following technical scheme:
A kind of IGBT device, comprising:
N-type base region and the grid structure and the source configuration that are positioned at front, described N-type base region;
The the first N-type resilient coating that is positioned at the back side, described N-type base region, the impurity of described the first N-type resilient coating is the 5th major element ion, and the impurity concentration of described the first N-type resilient coating is greater than the impurity concentration of N-type base region;
Be positioned at the second N-type resilient coating on described the first N-type buffer-layer surface, the impurity of described the second N-type resilient coating is the 6th major element ion, and the impurity concentration of described the second N-type resilient coating is greater than the impurity concentration of N-type base region, and be less than the impurity concentration of described the first N-type resilient coating;
Be positioned at the 3rd N-type resilient coating on described the second N-type buffer-layer surface, the impurity of described the 3rd N-type resilient coating is the 5th major element ion, and the impurity concentration of described the 3rd N-type resilient coating is greater than the impurity concentration of the first N-type resilient coating;
Be positioned at the collector structure on described the 3rd N-type buffer-layer surface.
Preferably, the impurity of described the first N-type resilient coating is P ion or As ion or Sb ion.
Preferably, the impurity concentration of described the first N-type resilient coating is 1e15/cm
3~ 5e16/cm
3, and the thickness of described the first N-type resilient coating is 0.1 μ m ~ 2.0 μ m.
Preferably, the impurity of described the second N-type resilient coating is O ion or S ion or Se ion or Te ion.
Preferably, the impurity concentration of described the second N-type resilient coating is 1e12/cm
3~ 1e15/cm
3, and the thickness of described the second N-type resilient coating is 1.0 μ m ~ 20 μ m.
Preferably, the impurity of described the 3rd N-type resilient coating is P ion or As ion or Sb ion.
Preferably, the impurity concentration of described the 3rd N-type resilient coating is 5e15/cm
3~ 1e17/cm
3, and the thickness of described the 3rd N-type resilient coating is 0.5 μ m ~ 2.0 μ m.
Preferably, described N-type base region, the first N-type resilient coating, the second N-type resilient coating and the 3rd N-type resilient coating are all positioned at a monocrystalline substrate.
Preferably, described N-type base region is positioned at a monocrystalline substrate, and described the first N-type resilient coating, the second N-type resilient coating and the 3rd N-type resilient coating are all positioned at non-single crystal semiconductor layer, and described non-single crystal semiconductor layer is positioned at described monocrystalline substrate lower surface.
Preferably, described non-single crystal semiconductor layer is polysilicon layer or amorphous silicon layer or polycrystalline germanium layer or amorphous germanium layer or poly-SiGe alloy-layer or amorphous germanium silicon alloy layer.
A kind of IGBT device manufacture method, comprising:
One monocrystalline substrate is provided, in described monocrystalline substrate, comprises N-type base region;
Positive grid structure and the source configuration of forming in described N-type base region;
Form the first N-type resilient coating at the back side, described N-type base region, described the first N-type resilient coating gos deep in described monocrystalline substrate surface, and the impurity of described the first N-type resilient coating is the 5th major element ion, and its impurity concentration is greater than the impurity concentration of N-type base region;
On described the first N-type buffer-layer surface, form the second N-type resilient coating, described the second N-type resilient coating gos deep in described monocrystalline substrate surface, and the impurity of described the second N-type resilient coating is the 6th major element ion, its impurity concentration is greater than the impurity concentration of N-type base region, and is less than the impurity concentration of described the first N-type resilient coating;
On described the second N-type buffer-layer surface, form the 3rd N-type resilient coating, described the 3rd N-type resilient coating gos deep in described monocrystalline substrate surface, and the impurity of described the 3rd N-type resilient coating is the 5th major element ion, and its impurity concentration is greater than the impurity concentration of the first N-type resilient coating;
On described the 3rd N-type buffer-layer surface, form collector structure.
Preferably, form the first N-type resilient coating at the back side, described N-type base region, comprising:
Adopt energetic ion injection technology by P ion or As ion or Sb Implantation in described monocrystalline substrate, form the first N-type resilient coating at the back side, described N-type base region, its Implantation degree of depth is 2.0 μ m ~ 20 μ m, implantation dosage is 1e12/cm
2~ 1e16/cm
2.
Preferably, on described the first N-type buffer-layer surface, form the second N-type resilient coating, comprising:
Adopt energetic ion injection technology by O ion or S ion or Se ion or Te Implantation in described monocrystalline substrate, on described the first N-type buffer-layer surface, form the second N-type resilient coating, its Implantation degree of depth is between the first N-type resilient coating and the 3rd N-type resilient coating, and implantation dosage is 1e10/cm
2~ 1e16/cm
2.
Preferably, on described the second N-type buffer-layer surface, form the 3rd N-type resilient coating, comprising:
Adopt ion implantation technology by P ion or As ion or Sb Implantation in described monocrystalline substrate, on described the second N-type buffer-layer surface, form the 3rd N-type resilient coating, its Implantation degree of depth is 0.1 μ m ~ 2.0 μ m, implantation dosage is 1e12/cm
2~ 1e16/cm
2.
Preferably, on described the 3rd N-type buffer-layer surface, form collector structure, comprising:
Adopt ion implantation technology to form collector region on described the 3rd N-type buffer-layer surface;
By one or many annealing process, activate the foreign ion of collector region in the foreign ion of foreign ion, the 3rd N-type resilient coating of foreign ion, the second N-type resilient coating of described the first N-type resilient coating and collector structure, and the thickness that makes described the first N-type resilient coating is 0.1 μ m ~ 2.0 μ m, the thickness of described the second N-type resilient coating is 1.0 μ m ~ 20 μ m, and the thickness of described the 3rd N-type resilient coating is 0.5 μ m ~ 2.0 μ m;
Form collector electrode on surface, described collector region.
A kind of IGBT device manufacture method, comprising:
One monocrystalline substrate is provided, in described monocrystalline substrate, comprises N-type base region;
Positive grid structure and the source configuration of forming in described base region;
Form non-single crystal semiconductor layer at the back side, described N-type base region;
In described non-single crystal semiconductor layer, form the first N-type resilient coating, described the first N-type resilient coating gos deep in described non-single crystal semiconductor layer surface, and be positioned on surface, described and described N-type base region, the impurity of described the first N-type resilient coating is the 5th major element ion, and its impurity concentration is greater than the impurity concentration of N-type base region;
On described the first N-type buffer-layer surface, form the second N-type resilient coating, described the second N-type resilient coating gos deep in described non-single crystal semiconductor layer surface, and the impurity of described the second N-type resilient coating is the 6th major element ion, its impurity concentration is greater than the impurity concentration of N-type base region, and is less than the impurity concentration of described the first N-type resilient coating;
On described the second N-type buffer-layer surface, form the 3rd N-type resilient coating, described the 3rd N-type resilient coating gos deep in described non-single crystal semiconductor layer surface, and the impurity of described the 3rd N-type resilient coating is the 5th major element ion, and its impurity concentration is greater than the impurity concentration of the first N-type resilient coating;
On described the 3rd N-type buffer-layer surface, form collector structure.
Preferably, form the process of described the first N-type resilient coating, the second N-type resilient coating and the 3rd N-type resilient coating, comprising:
In described non-single crystal semiconductor layer, form successively the first N-type resilient coating, the second N-type resilient coating and the 3rd N-type resilient coating by ion implantation technology;
By one or many annealing process, the thickness that makes described the first N-type resilient coating is 0.1 μ m ~ 2.0 μ m, and the thickness of described the second N-type resilient coating is 1.0 μ m ~ 20 μ m, and the thickness of described the 3rd N-type resilient coating is 0.5 μ m ~ 2.0 μ m.
A kind of IGBT device manufacture method, comprising:
One monocrystalline substrate is provided, in described monocrystalline substrate, comprises N-type base region;
Positive grid structure and the source configuration of forming in described base region;
Form the first non-single crystal semiconductor layer at the back side, described N-type base region, and in described the first non-single crystal semiconductor layer, form the first N-type resilient coating, wherein, the impurity of described the first N-type resilient coating is the 5th major element ion, and its impurity concentration is greater than the impurity concentration of N-type base region;
In described the first non-monocrystalline silicon semiconductor layer surface, form the second non-single crystal semiconductor layer, and in described the second non-single crystal semiconductor layer, form the second N-type resilient coating, wherein, the impurity of described the second N-type resilient coating is the 6th major element ion, its impurity concentration is greater than the impurity concentration of N-type base region, and is less than the impurity concentration of described the first N-type resilient coating;
In described the second non-monocrystalline silicon semiconductor layer surface, form the 3rd non-single crystal semiconductor layer, and form the 3rd N-type resilient coating in described the 3rd non-single crystal semiconductor layer, wherein, the impurity of described the 3rd N-type resilient coating is the 5th major element ion, and its impurity concentration is greater than the impurity concentration of the first N-type resilient coating;
On described the 3rd N-type buffer-layer surface, form collector structure.
Preferably, described the first N-type resilient coating, the second N-type resilient coating and the 3rd N-type resilient coating all form by in-situ doped technique, and the thickness of described the first N-type resilient coating is 0.1 μ m ~ 2.0 μ m, the thickness of described the second N-type resilient coating is 1.0 μ m ~ 20 μ m, and the thickness of described the 3rd N-type resilient coating is 0.5 μ m ~ 2.0 μ m.
Preferably, described non-single crystal semiconductor layer is polysilicon layer or amorphous silicon layer or polycrystalline germanium layer or amorphous germanium layer or poly-SiGe alloy-layer or amorphous germanium silicon alloy layer.
From such scheme, the IGBT device that the application provides, between N-type base region and collector structure, be disposed with the first N-type resilient coating, the second N-type resilient coating and the 3rd N-type resilient coating, wherein, the impurity of described the first N-type resilient coating is the 5th major element ion, and the impurity concentration of described the first N-type resilient coating is greater than the impurity concentration of N-type base region, described the first N-type resilient coating can be blocked electric field, reduces thickness and the forward conduction voltage of N-type base region; The impurity of described the second N-type resilient coating is the 6th major element ion, and the impurity concentration of described the second N-type resilient coating is greater than the impurity concentration of N-type base region, and be less than the impurity concentration of described the first N-type resilient coating, the complex centre of introducing deep energy level by the method for the 6th major element doping in the second N-type resilient coating, in described the second N-type resilient coating, carrier lifetime is lower, has increased the turn-off speed of described IGBT device; The impurity of described the 3rd N-type resilient coating is the 5th major element ion, and the impurity concentration of described the 3rd N-type resilient coating is greater than the impurity concentration of the first N-type resilient coating, described the 3rd N-type resilient coating can be optimized the relevant parameters such as blocking voltage, forward conduction voltage and the mutual conductance of described IGBT device.
Visible, three resilient coatings of the IGBT device that the application provides can be distinguished the correlation properties of independent optimization IGBT device, obtain the compromise curve of better turn-on and turn-off, and then can optimize the switching characteristic of IGBT, thereby improved the overall performance of the device of IGBT.
Accompanying drawing explanation
Shown in accompanying drawing, above-mentioned and other object of the present invention, Characteristics and advantages will be more clear.In whole accompanying drawings, identical Reference numeral is indicated identical part.Deliberately do not draw accompanying drawing by actual size equal proportion convergent-divergent, focus on illustrating purport of the present invention.
The structural representation of a kind of IGBT device that Fig. 1 provides for the application;
A kind of IGBT device impurities concentration distribution figure that Fig. 2 provides for the application;
The another kind of IGBT device architecture schematic diagram that Fig. 3 provides for the application;
A kind of IGBT device manufacture method flow chart that Fig. 4 provides for the application.
Embodiment
As described in background, the device performance of existing IGBT device is unsatisfactory.Inventor studies discovery, for being provided with the electric field blocking-up type IGBT device of N-type resilient coating, under its blocking state, the electric field of device is mainly distributed in N-type base region, at the intersection of N-type base region and N-type resilient coating, interface electric-field intensity distribution is determined by interface doping content, and the voltage drop of N-type resilient coating is determined by thickness and the doping content of N-type resilient coating; In the interface, collector region of N-type resilient coating and collector structure, the doping content of collector region and N-type resilient coating has determined the injection efficiency of device, and the doping content that increases N-type resilient coating can reduce the injection efficiency of backside collector, and injection efficiency is the basic parameter of IGBT, to the blocking voltage of IGBT, forward conduction voltage drop, many parameters such as mutual conductance have impact; In the mesozone of N-type resilient coating, its doping content mainly exerts an influence to the life-span of minority carrier, and with the reduction of minority carrier lifetime, the IGBT turn-off time decreases.
Inventor further studies discovery, between the N-type base region of IGBT device and collector structure, corresponding the each performance parameter of IGBT device arranges three resilient coatings, make the described resilient coating performance of IGBT device described in independent optimization respectively, thereby promote the performance of IGBT device.
Based on this, the application provides a kind of IGBT device, comprising:
N-type base region and the grid structure and the source configuration that are positioned at front, base region;
The the first N-type resilient coating that is positioned at the back side, described N-type base region, the impurity of described the first N-type resilient coating is the 5th major element ion, and the impurity concentration of described the first N-type resilient coating is greater than the impurity concentration of N-type base region;
Be positioned at the second N-type resilient coating on described the first N-type buffer-layer surface, the impurity of described the second N-type resilient coating is the 6th major element ion, and the impurity concentration of described the second N-type resilient coating is greater than the impurity concentration of N-type base region, and be less than the impurity concentration of described the first N-type resilient coating;
Be positioned at the 3rd N-type resilient coating on described the second N-type buffer-layer surface, the impurity of described the 3rd N-type resilient coating is the 5th major element ion, and the impurity concentration of described the 3rd N-type resilient coating is greater than the impurity concentration of the first N-type resilient coating;
Be positioned at the collector structure on described the 3rd N-type buffer-layer surface.
Because the impurity of described the first N-type resilient coating is the 5th major element ion, and the impurity concentration of described the first N-type resilient coating is greater than the impurity concentration of N-type base region, described the first N-type resilient coating can be blocked electric field, reduces thickness and the forward conduction voltage of N-type base region; The impurity of described the second N-type resilient coating is the 6th major element ion, and the impurity concentration of described the second N-type resilient coating is greater than the impurity concentration of N-type base region, and be less than the impurity concentration of described the first N-type resilient coating, in described two N-type resilient coatings, carrier lifetime is lower, has increased the turn-off speed of described IGBT device; The impurity of described the 3rd N-type resilient coating is the 5th major element ion, and the impurity concentration of described the 3rd N-type resilient coating is greater than the impurity concentration of the first N-type resilient coating, described the 3rd N-type resilient coating can be optimized the relevant parameters such as blocking voltage, forward conduction voltage and the mutual conductance of described IGBT device.
Visible, three resilient coatings of the IGBT device that the application provides can be distinguished the correlation properties of independent optimization IGBT device, thereby have improved the device performance of IGBT.
It is more than the application's core concept, below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
The present invention is described in detail in conjunction with schematic diagram; in the time that the embodiment of the present invention is described in detail in detail, for ease of explanation, represent that the profile of device architecture can be disobeyed local amplification of general ratio work; and described schematic diagram is example, it should not limit the scope of protection of the invention at this.In addition in actual fabrication, should comprise, the three-dimensional space of length, width and the degree of depth.
The embodiment of the present application provides a kind of IGBT device, as shown in Figure 1, comprising:
N-type base region 11, described N-type base region 11 is lightly doped N-type base region, is positioned at the Semiconductor substrate that a monocrystalline substrate or other can be used for IGBT device, in the present embodiment, described N-type base region 11 is preferably placed in a monocrystalline substrate.
Be positioned at grid structure and the source configuration in 11 fronts, described N-type base region.
Wherein, described grid structure comprises:
Gate dielectric layer 121, described gate dielectric layer 121 is positioned on the surface of described N-type base region 11;
Grid 122, it is upper that described grid 122 is positioned at described gate dielectric layer 121 surfaces, and described grid 122 is polysilicon gate;
Grid passivation layer 123, described grid passivation layer 123 is coated on surface and the sidewall of described grid 122.
Described source configuration comprises:
P type well region 131, described P type well region 131 gos deep in 11 surfaces, described N-type base region, and this P type well region surface flushes with 11 fronts, described N-type base region;
Source region 132, described source region 132 is N-type heavy doping, gos deep in described P type well region 131, and the flush of the surface in described source region 132 and described P type well region 131;
Source electrode 133, described source electrode 133 is metal electrode, is preferably aluminium electrode, and described source electrode 133 covers the front of described N-type base region 11 and the surface of grid structure.
Be positioned at the first N-type resilient coating 141 at 11 back sides, described N-type base region, the impurity of described the first N-type resilient coating 141 is the 5th major element ion, preferably, the impurity of described the first N-type resilient coating 141 is P ion or As ion or Sb ion, and the impurity concentration of described the first N-type resilient coating 141 is greater than the impurity concentration of N-type base region, preferably, the impurity concentration of described the first N-type resilient coating 141 is 1e15/cm
3~ 5e16/cm
3, more preferably 5e15/cm of the impurity concentration of described the first N-type resilient coating 141
3~ 1e16/cm
3, and the thickness of described the first N-type resilient coating 141 is 0.1 μ m ~ 2.0 μ m, is preferably 1.0 μ m ~ 1.5 μ m.
At the intersection of N-type base region and the first N-type resilient coating 141, interface electric-field intensity distribution is determined by interface doping content, and the impurity of described the first N-type resilient coating 141 is the 5th major element ion, its impurity concentration is greater than the impurity concentration of N-type base region 11, described the first N-type resilient coating 141 can be blocked electric field, reduces thickness and the forward conduction voltage of N-type base region 11.
Be positioned at lip-deep the second N-type resilient coating 142 of described the first N-type resilient coating 141, the impurity of described the second N-type resilient coating 142 is the 6th major element ion, preferably, the impurity of described the second N-type resilient coating 142 is O ion or S ion or Se ion or Te ion, and the impurity concentration of described the second N-type resilient coating 142 is greater than the impurity concentration of N-type base region 11, and be less than the impurity concentration of described the first N-type resilient coating 141, preferably, the impurity concentration of described the second N-type resilient coating 142 is and the thickness of described the second N-type resilient coating 142 is 1.0 μ m ~ 20 μ m, be preferably 5 μ m ~ 10 μ m.
Because the 6th major element Implantation is in silicon, can produce shallow energy level donor state and deep energy level donor state simultaneously, wherein, shallow energy level donor state can make the doping content of the second N-type resilient coating 142 slightly increase.Because the 6th major element Implantation is in silicon, can produce deep energy level donor state simultaneously, there is more deep energy level donor state in the interior meeting of the second N-type resilient coating 142, and deep energy level donor state can play charge carrier composite action, reduce the life-span of minority carrier, with the reduction of minority carrier lifetime, the IGBT turn-off time decreases.Therefore the turn-off time that, can reduce described IGBT device at the second N-type resilient coating 142.
Be positioned at lip-deep the 3rd N-type resilient coating 143 of described the second N-type resilient coating 142, the impurity of described the 3rd N-type resilient coating 143 is the 5th major element ion, preferably, the impurity of described the 3rd N-type resilient coating 143 is P ion or As ion or Sb ion, and the impurity concentration of described the 3rd N-type resilient coating 143 is greater than the impurity concentration of the first N-type resilient coating 142, preferably, the impurity concentration of described the 3rd N-type resilient coating 143 is 5e15/cm
3~ 1e17/cm
3, more preferably 1e16/cm of the impurity concentration of described the 3rd N-type resilient coating 143
3~ 5e16/cm
3, and the thickness of described the 3rd N-type resilient coating 143 is 0.5 μ m ~ 2.0 μ m, is preferably 1 μ m ~ 1.5 μ m.
Be positioned at the lip-deep collector structure of described the 3rd N-type resilient coating 143.
Wherein, described collector structure comprises:
Be positioned at described the 3rd lip-deep collector region 151 of N-type resilient coating 143, described collector region 151 is the heavy doping of P type;
Be positioned at the lip-deep collector electrode 152 in described collector region 151, described collector electrode 152 is a metal electrode, is preferably the metal laminated of the alloy-layer of Al electrode or Ti electrode or Ni electrode or Ag electrode or Al/Ti/Ni/Ag or Al/Ti/Ni/Ag.
Due to 151 interfaces, collector region at the 3rd N-type resilient coating 143 and collector structure, the doping content of collector region 151 and the 3rd N-type resilient coating 143 has determined the injection efficiency of device, and the doping content that increases the 3rd N-type resilient coating 143 can reduce the injection efficiency of backside collector 151, and injection efficiency is the basic parameter of IGBT, to the blocking voltage of IGBT, forward conduction voltage drop, many parameters such as mutual conductance have impact, by the 3rd N-type resilient coating 143 can independent optimization described in the injection efficiency of IGBT device, and then optimize the blocking voltage of described IGBT device, the relevant parameters such as forward conduction voltage and mutual conductance.
Described the first N-type resilient coating 141, the second N-type resilient coating 142, the 3rd N-type resilient coating 143 and collector region 151 are all goed deep in described monocrystalline substrate surface, and 151 surfaces, described collector region flush with the described monocrystalline substrate back side, and described the first N-type resilient coating 141, the second N-type resilient coating 142, the 3rd N-type resilient coating 143 and collector region 151 all form in described monocrystalline substrate.
Fig. 2 is the impurity doping content schematic diagram in described IGBT device, and wherein, abscissa Distance is the fore-and-aft distance of described IGBT device, ordinate Doping(Log scale) be the doping content logarithmic coordinates of impurity.
Another embodiment of the application discloses another kind of IGBT device, is with above-described embodiment difference:
As shown in Figure 3, described N-type base region 11 is positioned at a monocrystalline substrate 1, and be provided with a non-single crystal semiconductor layer 2 at described monocrystalline substrate 1 lower surface, described the first N-type resilient coating 141, the second N-type resilient coating 142 and the 3rd N-type resilient coating 143 and collector region 151 are all positioned at described non-single crystal semiconductor layer 2, and described the first N-type resilient coating 141, the second N-type resilient coating 142 and the 3rd N-type resilient coating 143 and collector region 151 are all in the interior formation of described non-single crystal semiconductor layer 2.Described non-single crystal semiconductor layer 2 is polysilicon layer or amorphous silicon layer or polycrystalline germanium layer or amorphous germanium layer or poly-SiGe alloy-layer or amorphous germanium silicon alloy layer.And described non-single crystal semiconductor layer 2 can be single non-single crystal semiconductor layer, also can be respectively corresponding with described the first N-type resilient coating 141, the second N-type resilient coating 142 and the 3rd N-type resilient coating 143 be divided into three non-single crystal semiconductor layers, described non-single crystal semiconductor layer 2 is divided into the first non-single crystal semiconductor layer, the second non-single crystal semiconductor layer and the 3rd non-single crystal semiconductor layer.
Because the diffusion coefficient of impurity in the similar non-single crystal semiconductor layer such as polysilicon layer or amorphous silicon layer is greater than the diffusion coefficient in monocrystalline silicon, therefore, compared with monocrystalline substrate, form identical the first N-type resilient coating 141, the second N-type resilient coating 142 and the 3rd N-type resilient coating 143, can reduce Implantation Energy and/or the annealing temperature of ion.
In addition, above-mentioned IGBT device is the IGBT device of plane, and still, described the first N-type resilient coating 141, the second N-type resilient coating 142 and the 3rd N-type resilient coating 143 can also be applied in groove-shaped IGBT device.
The another embodiment of the application provides a kind of IGBT device manufacture method, as shown in Figure 4, comprising:
One monocrystalline substrate is provided, in described monocrystalline substrate, comprises N-type base region.
Positive grid structure and the source configuration of forming in described N-type base region.
Concrete, adopt thermal oxidation technology or CVD technique at the positive gate dielectric layer that forms of described monocrystalline substrate, the material of described gate dielectric layer can be silicon dioxide;
Adopt the techniques such as CVD, LPCVD or HDP on described gate dielectric layer surface, to form grid layer, described grid layer is polysilicon layer;
Described grid layer and gate dielectric layer are carried out to etching, form grid, concrete, adopt photoetching process to form grid.First, spin coating photoresist layer on described grid layer surface, in order to guarantee exposure accuracy, also can between photoresist layer and grid layer, form anti-reflecting layer, to reduce unnecessary reflection, adopt afterwards the mask plate with gate patterns to expose to photoresist layer, on described photoresist layer surface, form gate pattern, afterwards take the photoresist layer with gate pattern as mask, adopt the mode of dry etching or wet etching to form grid, gate dielectric layer material outside eating away grid in the same time, finally adopts the methods such as wet-chemical cleaning to remove photoresist layer.
Take grid as mask or take the photoresist layer with P type well region figure as mask, adopt ion implantation technology, in described monocrystalline substrate surface, carry out the injection of P type well region, utilize afterwards annealing process to carry out high temperature and push away trap, activate the P type well region foreign ion injecting, the P type well region pushing away after trap by high temperature can be diffused in the monocrystalline substrate of grid below in a lateral direction.Same, the photoresist layer that employing has source region figure is mask, adopts ion implantation technology, in the surface of described P type well region, injects source region foreign ion.
Form grid passivation layer in described gate surface and sidewall, the material of described grid passivation layer can be silicon dioxide or silicon nitride, and described gate dielectric layer, grid and grid passivation layer form the grid structure of described IGBT device.
Adopt annealing process, activate the foreign ion in source region, and make source region be diffused in a lateral direction grid structure below by annealing process.
Front-side metallization forms source electrode on described grid structure, source region and P type well region surface, and described source electrode is preferably aluminium electrode; afterwards; can also form source electrode passivation layer on described source electrode surface, to protect source metal, complete the making of described IGBT device source electrode structure.
The thinning back side of monocrystalline substrate, specifically can realize by chemical mechanical milling tech the thinning back side of monocrystalline substrate, to remove the oxide layer forming at the described monocrystalline substrate back side in above-mentioned steps.
Form the first N-type resilient coating at the back side, described N-type base region, described the first N-type resilient coating gos deep in described monocrystalline substrate surface, and the impurity of described the first N-type resilient coating is the 5th major element ion, and its impurity concentration is greater than the impurity concentration of N-type base region.
Concrete, at the described monocrystalline substrate back side, adopt energetic ion injection technology by P ion or As ion or Sb Implantation in described monocrystalline substrate, form the first N-type resilient coating at the back side, described N-type base region, its Implantation degree of depth is 2.0 μ m ~ 20 μ m, be preferably 6 μ m ~ 12 μ m, implantation dosage is 1e12/cm
2~ 1e16/cm
2, be preferably 1e13/cm
2~ 1e15/cm
2, ion doping concentration is preferably 1e15/cm
3~ 5e16/cm
3, more preferably 5e15/cm
3~ 1e16/cm
3.
Because the degree of depth of Implantation is larger, therefore, can also adopt proton irradiation technique that foreign ion is injected in described monocrystalline substrate.
At the intersection of N-type base region and the first N-type resilient coating, interface electric-field intensity distribution is determined by interface doping content, and the impurity of described the first N-type resilient coating is the 5th major element ion, its impurity concentration is greater than the impurity concentration of N-type base region, described the first N-type resilient coating can be blocked electric field, reduces thickness and the forward conduction voltage of N-type base region.
On described the first N-type buffer-layer surface, form the second N-type resilient coating, described the second N-type resilient coating gos deep in described monocrystalline substrate surface, and the impurity of described the second N-type resilient coating is the 6th major element ion, its impurity concentration is greater than the impurity concentration of N-type base region, and is less than the impurity concentration of described the first N-type resilient coating.
Concrete, at the described monocrystalline substrate back side, adopt energetic ion injection technology by O ion or S ion or Se ion or Te Implantation in described monocrystalline substrate, on described the first N-type buffer-layer surface, form the second N-type resilient coating, its Implantation degree of depth is between the first N-type resilient coating and the thickness of the 3rd N-type resilient coating, be preferably 1 μ m～18 μ m, implantation dosage is 1e10/cm
2~ 1e16/cm
2, be preferably 1e12/cm
2~ 1e14/cm
2, ion doping concentration is preferably 1e12/cm
3~ 1e15/cm
3, more preferably 1e13/cm
3~ 1e14/cm
3.
Because the 6th major element Implantation is in silicon, can produce shallow energy level donor state and deep energy level donor state simultaneously, wherein, shallow energy level donor state can make the doping content of the second N-type resilient coating slightly increase.Because the 6th major element Implantation is in silicon, can produce deep energy level donor state simultaneously, in the second N-type resilient coating, can there is more deep energy level donor state, and deep energy level donor state can play charge carrier composite action, reduce the life-span of minority carrier, with the reduction of minority carrier lifetime, the IGBT turn-off time decreases.Therefore the turn-off time that, can reduce described IGBT device at the second N-type resilient coating.
On described the second N-type buffer-layer surface, form the 3rd N-type resilient coating, described the 3rd N-type resilient coating gos deep in described monocrystalline substrate surface, and the impurity of described the 3rd N-type resilient coating is the 5th major element ion, and its impurity concentration is greater than the impurity concentration of the first N-type resilient coating.
Concrete, at the described monocrystalline substrate back side, adopt ion implantation technology by P ion or As ion or Sb Implantation in described monocrystalline substrate, on described the second N-type buffer-layer surface, form the 3rd N-type resilient coating, its Implantation degree of depth is 0.1 μ m ~ 2.0 μ m, be preferably 0.4 μ m ~ 1.2 μ m, implantation dosage is 1e12/cm
2~ 1e16/cm
2, be preferably 1e13/cm
2~ 1e15/cm
2, ion concentration is preferably 5e15/cm
3~ 1e17/cm
3, more preferably 1e16/cm
3~ 5e16/cm
3.
On described the 3rd N-type buffer-layer surface, form collector structure.
Concrete, adopt ion implantation technology to form collector region, described collector region is P type heavy doping collector region, the impurity of injection is B or BF
2, the surface of described collector region flushes with the described monocrystalline substrate back side.By one or many annealing process, the temperature of annealing is 350 ℃ ~ 550 ℃, be preferably 400 ℃ ~ 500 ℃, to activate the foreign ion of collector region in the foreign ion of foreign ion, the 3rd N-type resilient coating of foreign ion, the second N-type resilient coating of described the first N-type resilient coating and collector structure, and the thickness that makes described the first N-type resilient coating is 0.1 μ m ~ 2.0 μ m, the thickness of described the second N-type resilient coating is 1.0 μ m ~ 20 μ m, and the thickness of described the 3rd N-type resilient coating is 0.5 μ m ~ 2.0 μ m.Afterwards, on surface, described collector region, (being the monocrystalline substrate back side) forms collector electrode, and described current collection is Al electrode or Ti electrode or Ni electrode or Ag electrode very, completes the making of described collector structure.
Due in the 3rd N-type resilient coating and interface, collector region, the doping content of collector region and the 3rd N-type resilient coating has determined the injection efficiency of device, and the doping content that increases the 3rd N-type resilient coating can reduce the injection efficiency of backside collector, and injection efficiency is the basic parameter of IGBT, to the blocking voltage of IGBT, forward conduction voltage drop, many parameters such as mutual conductance have impact, by the 3rd N-type resilient coating can independent optimization described in the injection efficiency of IGBT device, and then optimize the blocking voltage of described IGBT device, the relevant parameters such as forward conduction voltage and mutual conductance.
Another embodiment of the application discloses the manufacture method of another kind of IGBT device, and the method comprises:
One monocrystalline substrate is provided, in described monocrystalline substrate, comprises N-type base region.
Positive grid structure and the source configuration of forming in described base region.
Be with the difference of above-described embodiment:
After the thinning back side of monocrystalline substrate, form non-single crystal semiconductor layer at the back side, described N-type base region by chemical vapor deposition method, described non-single crystal semiconductor layer is polysilicon layer or amorphous silicon layer or polycrystalline germanium layer or amorphous germanium layer or poly-SiGe alloy-layer or amorphous germanium silicon alloy layer.
In described non-single crystal semiconductor layer, form the first N-type resilient coating, described the first N-type resilient coating gos deep in described non-single crystal semiconductor layer surface, and be positioned on surface, described and described N-type base region, the impurity of described the first N-type resilient coating is the 5th major element ion, and its impurity concentration is greater than the impurity concentration of N-type base region.
On described the first N-type buffer-layer surface, form the second N-type resilient coating, described the second N-type resilient coating gos deep in described non-single crystal semiconductor layer surface, and the impurity of described the second N-type resilient coating is the 6th major element ion, its impurity concentration is greater than the impurity concentration of N-type base region, and is less than the impurity concentration of described the first N-type resilient coating.
On described the second N-type buffer-layer surface, form the 3rd N-type resilient coating, described the 3rd N-type resilient coating gos deep in described non-single crystal semiconductor layer surface, and the impurity of described the 3rd N-type resilient coating is the 5th major element ion, and its impurity concentration is greater than the impurity concentration of the first N-type resilient coating.
On described the 3rd N-type buffer-layer surface, form collector structure.
Because the diffusion coefficient of impurity in the similar non-single crystal semiconductor layer such as polysilicon layer or amorphous silicon layer is greater than the diffusion coefficient in monocrystalline silicon, therefore, can in described non-single crystal semiconductor layer, form successively the first N-type resilient coating by ion implantation technology, the second N-type resilient coating and the 3rd N-type resilient coating, afterwards again by one or many annealing process, activator impurity ion, and the thickness that makes described the first N-type resilient coating is 0.1 μ m ~ 2.0 μ m, the thickness of described the second N-type resilient coating is 1.0 μ m ~ 20 μ m, the thickness of described the 3rd N-type resilient coating is 0.5 μ m ~ 2.0 μ m.Wherein, the annealing temperature of described annealing process is 350 ℃ ~ 550 ℃, is preferably 400 ℃ ~ 500 ℃.
Said method can be avoided adopting expensive energetic ion injection device, saves production cost.
In addition, can also in described non-single crystal semiconductor layer, form successively the first N-type resilient coating, the second N-type resilient coating and the 3rd N-type resilient coating by proton irradiation technique, carry out annealing in process by one or many annealing process more afterwards.Compared with above-described embodiment, can reduce like this energy consumption of proton irradiation, reduce production costs.
The another embodiment of the application discloses the manufacture method of another IGBT device, and the method comprises:
One monocrystalline substrate is provided, in described monocrystalline substrate, comprises N-type base region.
Positive grid structure and the source configuration of forming in described base region.
Be with above-described embodiment difference:
After the thinning back side of monocrystalline substrate, form the first non-single crystal semiconductor layer at the back side, described N-type base region, and in described the first non-single crystal semiconductor layer, form the first N-type resilient coating, wherein, the impurity of described the first N-type resilient coating is the 5th major element ion, and its impurity concentration is greater than the impurity concentration of N-type base region;
On described the first non-single crystal semiconductor layer surface, form the second non-single crystal semiconductor layer, and in described the second non-single crystal semiconductor layer, form the second N-type resilient coating, wherein, the impurity of described the second N-type resilient coating is the 6th major element ion, its impurity concentration is greater than the impurity concentration of N-type base region, and is less than the impurity concentration of described the first N-type resilient coating;
On described the second non-single crystal semiconductor layer surface, form the 3rd non-single crystal semiconductor layer, and form the 3rd N-type resilient coating in described the 3rd non-single crystal semiconductor layer, wherein, the impurity of described the 3rd N-type resilient coating is the 5th major element ion, and its impurity concentration is greater than the impurity concentration of the first N-type resilient coating;
On described the 3rd N-type buffer-layer surface, form collector structure.
Wherein, described the first non-single crystal semiconductor layer, the second non-single crystal semiconductor layer and the 3rd non-single crystal semiconductor layer all form by chemical vapor deposition method, and described the first non-single crystal semiconductor layer, the second non-single crystal semiconductor layer and the 3rd non-single crystal semiconductor layer are preferably polysilicon layer or amorphous silicon layer or polycrystalline germanium layer or amorphous germanium layer or poly-SiGe alloy-layer or amorphous germanium silicon alloy layer.Described the first N-type resilient coating, the second N-type resilient coating and the 3rd N-type resilient coating all form by in-situ doped technique, and the thickness of described the first N-type resilient coating is 0.1 μ m ~ 2.0 μ m, the thickness of described the second N-type resilient coating is 1.0 μ m ~ 20 μ m, and the thickness of described the 3rd N-type resilient coating is 0.5 μ m ~ 2.0 μ m.
The method providing due to the present embodiment is to adopt in-situ doped technique to form the first resilient coating, the second resilient coating and three buffer layer, can save the process of annealing.
The above-mentioned example of executing is only take the manufacture method of N-type IGBT device as example; structure and manufacture method to IGBT device describe; if adopt P type base region; or prepare the IGBT device of other type (as groove-shaped IGBT); making step and technique may have a little difference; as long as but meet the juche idea of the embodiment of the present invention, all within the protection range of the embodiment of the present invention, and the disclosed number range of the embodiment of the present application includes end points.
Although the present invention discloses as above with preferred embodiment, but not in order to limit the present invention.Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible variations and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (20)
1. an IGBT device, is characterized in that, comprising:
N-type base region and the grid structure and the source configuration that are positioned at front, described N-type base region;
The the first N-type resilient coating that is positioned at the back side, described N-type base region, the impurity of described the first N-type resilient coating is the 5th major element ion, and the impurity concentration of described the first N-type resilient coating is greater than the impurity concentration of N-type base region;
Be positioned at the second N-type resilient coating on described the first N-type buffer-layer surface, the impurity of described the second N-type resilient coating is the 6th major element ion, and the impurity concentration of described the second N-type resilient coating is greater than the impurity concentration of N-type base region, and be less than the impurity concentration of described the first N-type resilient coating;
Be positioned at the 3rd N-type resilient coating on described the second N-type buffer-layer surface, the impurity of described the 3rd N-type resilient coating is the 5th major element ion, and the impurity concentration of described the 3rd N-type resilient coating is greater than the impurity concentration of the first N-type resilient coating;
Be positioned at the collector structure on described the 3rd N-type buffer-layer surface.
2. IGBT device according to claim 1, is characterized in that, the impurity of described the first N-type resilient coating is P ion or As ion or Sb ion.
3. IGBT device according to claim 2, is characterized in that, the impurity concentration of described the first N-type resilient coating is 1e15/cm
3~ 5e16/cm
3, and the thickness of described the first N-type resilient coating is 0.1 μ m ~ 2.0 μ m.
4. IGBT device according to claim 1, is characterized in that, the impurity of described the second N-type resilient coating is O ion or S ion or Se ion or Te ion.
5. IGBT device according to claim 4, is characterized in that, the impurity concentration of described the second N-type resilient coating is 1e12/cm
3~ 1e15/cm
3, and the thickness of described the second N-type resilient coating is 1.0 μ m ~ 20 μ m.
6. IGBT device according to claim 1, is characterized in that, the impurity of described the 3rd N-type resilient coating is P ion or As ion or Sb ion.
7. IGBT device according to claim 6, is characterized in that, the impurity concentration of described the 3rd N-type resilient coating is 5e15/cm
3~ 1e17/cm
3, and the thickness of described the 3rd N-type resilient coating is 0.5 μ m ~ 2.0 μ m.
8. IGBT device according to claim 1, is characterized in that, described N-type base region, the first N-type resilient coating, the second N-type resilient coating and the 3rd N-type resilient coating are all positioned at a monocrystalline substrate.
9. IGBT device according to claim 1, it is characterized in that, described N-type base region is positioned at a monocrystalline substrate, described the first N-type resilient coating, the second N-type resilient coating and the 3rd N-type resilient coating are all positioned at non-single crystal semiconductor layer, and described non-single crystal semiconductor layer is positioned at described monocrystalline substrate lower surface.
10. IGBT device according to claim 9, is characterized in that, described non-single crystal semiconductor layer is polysilicon layer or amorphous silicon layer or polycrystalline germanium layer or amorphous germanium layer or poly-SiGe alloy-layer or amorphous germanium silicon alloy layer.
11. 1 kinds of IGBT device manufacture methods, is characterized in that, comprising:
One monocrystalline substrate is provided, in described monocrystalline substrate, comprises N-type base region;
Positive grid structure and the source configuration of forming in described N-type base region;
Form the first N-type resilient coating at the back side, described N-type base region, described the first N-type resilient coating gos deep in described monocrystalline substrate surface, and the impurity of described the first N-type resilient coating is the 5th major element ion, and its impurity concentration is greater than the impurity concentration of N-type base region;
On described the first N-type buffer-layer surface, form the second N-type resilient coating, described the second N-type resilient coating gos deep in described monocrystalline substrate surface, and the impurity of described the second N-type resilient coating is the 6th major element ion, its impurity concentration is greater than the impurity concentration of N-type base region, and is less than the impurity concentration of described the first N-type resilient coating;
On described the second N-type buffer-layer surface, form the 3rd N-type resilient coating, described the 3rd N-type resilient coating gos deep in described monocrystalline substrate surface, and the impurity of described the 3rd N-type resilient coating is the 5th major element ion, and its impurity concentration is greater than the impurity concentration of the first N-type resilient coating;
On described the 3rd N-type buffer-layer surface, form collector structure.
12. according to method described in claim 11, it is characterized in that, forms the first N-type resilient coating at the back side, described N-type base region, comprising:
Adopt energetic ion injection technology by P ion or As ion or Sb Implantation in described monocrystalline substrate, form the first N-type resilient coating at the back side, described N-type base region, its Implantation degree of depth is 2.0 μ m ~ 20 μ m, implantation dosage is 1e12/cm
2~ 1e16/cm
2.
13. according to method described in claim 11, it is characterized in that, forms the second N-type resilient coating and comprise on described the first N-type buffer-layer surface:
Adopt energetic ion injection technology by O ion or S ion or Se ion or Te Implantation in described monocrystalline substrate, on described the first N-type buffer-layer surface, form the second N-type resilient coating, its Implantation degree of depth is between the first N-type resilient coating and the thickness of the 3rd N-type resilient coating, and implantation dosage is 1e10/cm
2~ 1e16/cm
2.
14. according to method described in claim 11, it is characterized in that, on described the second N-type buffer-layer surface, forms the 3rd N-type resilient coating, comprising:
Adopt ion implantation technology by P ion or As ion or Sb Implantation in described monocrystalline substrate, on described the second N-type buffer-layer surface, form the 3rd N-type resilient coating, its Implantation degree of depth is 0.1 μ m ~ 2.0 μ m, implantation dosage is 1e12/cm
2~ 1e16/cm
2.
15. according to method described in claim 14, it is characterized in that, on described the 3rd N-type buffer-layer surface, forms collector structure, comprising:
Adopt ion implantation technology to form collector region on described the 3rd N-type buffer-layer surface;
By one or many annealing process, activate the foreign ion of collector region in the foreign ion of foreign ion, the 3rd N-type resilient coating of foreign ion, the second N-type resilient coating of described the first N-type resilient coating and collector structure, and the thickness that makes described the first N-type resilient coating is 0.1 μ m ~ 2.0 μ m, the thickness of described the second N-type resilient coating is 1.0 μ m ~ 20 μ m, and the thickness of described the 3rd N-type resilient coating is 0.5 μ m ~ 2.0 μ m;
Form collector electrode on surface, described collector region.
16. 1 kinds of IGBT device manufacture methods, is characterized in that, comprising:
One monocrystalline substrate is provided, in described monocrystalline substrate, comprises N-type base region;
Positive grid structure and the source configuration of forming in described base region;
Form non-single crystal semiconductor layer at the back side, described N-type base region;
In described non-single crystal semiconductor layer, form the first N-type resilient coating, described the first N-type resilient coating gos deep in described non-single crystal semiconductor layer surface, and be positioned on surface, described and described N-type base region, the impurity of described the first N-type resilient coating is the 5th major element ion, and its impurity concentration is greater than the impurity concentration of N-type base region;
On described the first N-type buffer-layer surface, form the second N-type resilient coating, described the second N-type resilient coating gos deep in described non-single crystal semiconductor layer surface, and the impurity of described the second N-type resilient coating is the 6th major element ion, its impurity concentration is greater than the impurity concentration of N-type base region, and is less than the impurity concentration of described the first N-type resilient coating;
On described the second N-type buffer-layer surface, form the 3rd N-type resilient coating, described the 3rd N-type resilient coating gos deep in described non-single crystal semiconductor layer surface, and the impurity of described the 3rd N-type resilient coating is the 5th major element ion, and its impurity concentration is greater than the impurity concentration of the first N-type resilient coating;
On described the 3rd N-type buffer-layer surface, form collector structure.
17. according to method described in claim 16, it is characterized in that, forms the process of described the first N-type resilient coating, the second N-type resilient coating and the 3rd N-type resilient coating, comprising:
In described non-single crystal semiconductor layer, form successively the first N-type resilient coating, the second N-type resilient coating and the 3rd N-type resilient coating by ion implantation technology;
By one or many annealing process, the thickness that makes described the first N-type resilient coating is 0.1 μ m ~ 2.0 μ m, and the thickness of described the second N-type resilient coating is 1.0 μ m ~ 20 μ m, and the thickness of described the 3rd N-type resilient coating is 0.5 μ m ~ 2.0 μ m.
18. 1 kinds of IGBT device manufacture methods, is characterized in that, comprising:
One monocrystalline substrate is provided, in described monocrystalline substrate, comprises N-type base region;
Positive grid structure and the source configuration of forming in described base region;
Form the first non-single crystal semiconductor layer at the back side, described N-type base region, and in described the first non-single crystal semiconductor layer, form the first N-type resilient coating, wherein, the impurity of described the first N-type resilient coating is the 5th major element ion, and its impurity concentration is greater than the impurity concentration of N-type base region;
In described the first non-monocrystalline silicon semiconductor layer surface, form the second non-single crystal semiconductor layer, and in described the second non-single crystal semiconductor layer, form the second N-type resilient coating, wherein, the impurity of described the second N-type resilient coating is the 6th major element ion, its impurity concentration is greater than the impurity concentration of N-type base region, and is less than the impurity concentration of described the first N-type resilient coating;
In described the second non-monocrystalline silicon semiconductor layer surface, form the 3rd non-single crystal semiconductor layer, and form the 3rd N-type resilient coating in described the 3rd non-single crystal semiconductor layer, wherein, the impurity of described the 3rd N-type resilient coating is the 5th major element ion, and its impurity concentration is greater than the impurity concentration of the first N-type resilient coating;
On described the 3rd N-type buffer-layer surface, form collector structure.
19. according to method described in claim 18, it is characterized in that, described the first N-type resilient coating, the second N-type resilient coating and the 3rd N-type resilient coating all form by in-situ doped technique, and the thickness of described the first N-type resilient coating is 0.1 μ m ~ 2.0 μ m, the thickness of described the second N-type resilient coating is 1.0 μ m ~ 20 μ m, and the thickness of described the 3rd N-type resilient coating is 0.5 μ m ~ 2.0 μ m.
20. according to method described in claim 16 or 18, it is characterized in that, described non-single crystal semiconductor layer is polysilicon layer or amorphous silicon layer or polycrystalline germanium layer or amorphous germanium layer or poly-SiGe alloy-layer or amorphous germanium silicon alloy layer.
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| CN113921602A (en) * | 2020-07-09 | 2022-01-11 | 华大半导体有限公司 | Power semiconductor device |
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