CN104167356A - Insulated gate bipolar transistor and preparation method thereof - Google Patents
Insulated gate bipolar transistor and preparation method thereof Download PDFInfo
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- CN104167356A CN104167356A CN201410356503.2A CN201410356503A CN104167356A CN 104167356 A CN104167356 A CN 104167356A CN 201410356503 A CN201410356503 A CN 201410356503A CN 104167356 A CN104167356 A CN 104167356A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 238000009792 diffusion process Methods 0.000 claims abstract description 51
- 239000011248 coating agent Substances 0.000 claims description 29
- 238000000576 coating method Methods 0.000 claims description 29
- 238000001465 metallisation Methods 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 2
- 238000011946 reduction process Methods 0.000 claims description 2
- 230000000903 blocking effect Effects 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000000227 grinding Methods 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 230000009471 action Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- -1 phosphonium ion Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses an insulated gate bipolar transistor (IGBT) and a preparation method thereof. The IGBT includes an N-type base region, a P-type base region, a back P+ collecting electrode region, back N+ collecting electrode regions, an N+ emitting electrode region, a gate oxide layer, an emitting electrode, a P- buffer layer, a gate electrode and a collecting electrode. The N-type base region includes an N+ diffusion residual layer, an N- base region and an N+ buffer layer, which are sequentially laminated. Doping concentrations of the N+ diffusion residual layer and the N+ buffer layer gradually increase outwards from the boundaries of the N- base region. The N+ residual layer is arranged on the N- base region of the IGBT so that an ion doping concentration at an N-type front face is effectively improved and a current processing capability of the device is effectively improved and thus a switch-on saturation voltage drop is reduced; and the N+ buffer layer, the P- buffer layer, the back P+ collecting electrode region and the back N+ collecting electrode region, which are arranged sequentially on a back face from top to bottom, form an embedded NPN transistor so that a role of rapid channel of a minority carrier is played and the minority carrier is helped to scan the N- base region as soon as possible and thus switch-off time and switch-off loss of the device are reduced.
Description
Technical field
The present invention relates to field of high voltage power semiconductor devices, relate in particular to a kind of insulated gate bipolar transistor (IGBT).
Background technology
As the compound full-control type power semiconductor of latest generation, insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, be called for short IGBT) advantage of power MOSFET and bipolar transistor is rolled into one, there is voltage control, input impedance is large, driving power is little, control circuit is simple, switching loss is little, fast and the operating frequency advantages of higher of break-make speed, it is the internationally recognized power electronic technology the most representative product of revolution for the third time, Electric Machine Control, new forms of energy, high ferro, intelligent grid, requisite power " core is dirty " in the middle of the fields such as electric automobile.Little of PDP switch, arrive greatly high ferro construction, the appearance that has IGBT figure without exception.The features such as large, the withstand voltage height of IGBT power, good energy-conserving effect have determined that it is still not present, are also the mainstream technologys of high-end power semiconductor within the following quite a long time, and market prospects are very wide.
Since IGBT device is succeeded in developing, through the development of three more than ten years, its technology and indices are updated and are improved, and IGBT device developed into for the 6th generation by the first generation, and its various performance parameters also reach its maturity.But aspect the development to high-frequency high-power, still need reduce on-state voltage drop and improve between switching speed and trade off.
The difference that IGBT distributes according to the back side, can be divided into punch (PT-IGBT) and non-punch (NPT-IGBT) two kinds of structures.PT-IGBT can form N+ resilient coating and N-base by epitaxially grown mode on the P+ of Uniform Doped substrate, and then on N-base, makes required Facad structure.In the N-single crystalline substrate that NPT-IGBT is is hundreds of microns at the thickness of Uniform Doped, first make Facad structure, then the back side is thinned to the required thickness of forward blocking voltage by grinding the processes such as etching by N-base, then adopts the mode of Implantation to form overleaf back of the body P+ collector electrode.Distinguishingly with PT-IGBT be, NPT type IGBT does not need thick-layer extension, be applicable to manufacturing the IGBT of high forward blocking voltage, but owing to there is no N+ resilient coating, therefore reach the required N-base of identical forward blocking voltage thicker than PT-IGBT, this can cause its forward conduction voltage drop larger than PT-IGBT.But because the collector electrode doping content of PT-IGBT is too high, make its conductivity modulation effect in the time opening more obvious with respect to NPT type, while shutoff, hole in drift region can be more, therefore in turn off process, a large amount of holes can not obtain compound in time, makes its turn-off time longer, and turn-offing power consumption also can be larger.For this reason, must reduce minority carrier life time by minority carrier life time control technology, so just make amplitude and the duration of device current tail in turn off process all reduce, and the transparent collector of NPT-IGBT can make few son arrive rapidly metal electrode in the time turn-offing, therefore reduce carrier lifetime without technology such as adopting irradiation.
Chinese patent application CN201010290339.1 discloses the new construction of a kind of IGBT, as shown in Figure 1.Comprising collector electrode 10, back of the body P+ collector area 11, back of the body N+ resilient coating 12, N-base 13, gate oxide 14, gate electrode 15, N+ emitter region 16, emitter 17, P+ emitter region 18, the N+ residual layer 19 at the back side.The described structure of this invention can weaken the impact of JFET resistance effectively by use N+ to spread residual layer in front, thereby the conduction voltage drop of device is reduced, and collector current is improved.But this structure for the turn-off time performance of device without any improvement, do not form at conduction voltage drop and between the turn-off time one effectively compromise.
Summary of the invention
The invention provides a kind of insulated gate bipolar transistor and preparation method thereof, it is by deeply tying diffusion at front high temperature, the diffusion residual layer that forms after attenuate can effectively improve positive carrier concentration again; The NPN pipe embedding overleaf has played the effect of a few sub express passway, helps few son can scan out as soon as possible N-base.Device is able to form better trading off at conduction voltage drop and turn-off time, is more suitable for high-speed switch application.
A kind of insulated gate bipolar transistor, comprises N-type base, P type base, back of the body P+ collector area, N+ emitter region, gate oxide, emitter, gate electrode and collector electrode; Described N-type base comprises the N+ diffusion residual layer, N-base and the N+ resilient coating that stack gradually, described N+ diffusion residual layer and N+ resilient coating increase gradually from the initial outside doping content in border of N-base, described insulated gate bipolar transistor is further provided with P-resilient coating, back of the body N+ collector area, described P-resilient coating is between N+ resilient coating and back of the body P+ collector area, and described back of the body N+ collector area is positioned at the two ends of back of the body P+ collector area.
Described N-base is doping content constant region, and its thickness and doping content determine by the required forward blocking voltage of device, and forward blocking voltage and its thickness positive correlation, with doping content negative correlation.
Described N+ diffusion residual layer, if thickness is too small, the impurity doping content on surface can be lower, electricity lead modulating action a little less than, conduction voltage drop decline degree is lower; If thickness is excessive, the impurity doping content on surface can be higher, and it is stronger that electricity is led modulating action, although that conduction voltage drop declines is more, this also can cause the reduction of forward blocking voltage, also can cause the increase of turn-off time simultaneously.Therefore, the thickness of N+ diffusion residual layer is advisable with 5 ~ 15um.
Described P-resilient coating, if thickness is too small, P type collector region will be compressed, and therefore the injection of collector electrode will reduce when conducting, and therefore conduction voltage drop will increase to some extent; If thickness is excessive, P type collector region will be expanded to some extent, now conductivity modulation effect will be strengthened, conduction voltage drop will decrease, but on the other hand, because the expansion of NPN pipe base embedding overleaf can limit the extraction of few son, the turn-off time also can rise accordingly, and therefore the thickness of P-resilient coating is advisable with 1 ~ 5um.
The present invention also provides the preparation method of this insulated gate bipolar transistor, comprising:
(1) form respectively a N+ diffusion region and the 2nd N+ diffusion region in n type single crystal silicon both sides by High temperature diffusion;
(2) respectively a N+ diffusion region and the 2nd N+ diffusion region are processed to form to N+ diffusion residual layer and N+
Resilient coating;
(3) on N+ diffusion residual layer, form P type base, N+ emitter region, emitter;
(4) on N+ resilient coating, form P-resilient coating, back of the body P+ collector area, back of the body N+ collector area by injecting ion, after the metallization of back of the body Yu BeiN+ collector area, P+ collector area, form collector electrode.
Insulated gate bipolar transistor of the present invention, because its special preparation method: N+ diffusion residual layer and N+ resilient coating are deeply to tie diffusion at the two-sided high temperature of same step, and the diffusion residual layer forming through attenuate respectively; N+ diffusion residual layer on N-base, has improved the foreign ion doping content in front, N-type base, has formed stronger electricity and has led modulating action, thereby effectively reduced the conduction voltage drop of IGBT, improves the current capacity of IGBT.Meanwhile, by the embedding NPN transistor that N+ resilient coating forms by series of process step overleaf, play the effect of a few sub express passway, in the time turn-offing, helped few son can scan out as soon as possible N-base, thereby reduced the turn-off time of device.
The formation of the N+ diffusion residual layer of insulated gate bipolar transistor of the present invention and the N+ resilient coating at the back side is with a high temperature ties after diffusion deeply, form through reduction process such as grinding, polishings again, these all belong to original normal process, do not need additionally to increase processing step and form, thereby reduced manufacturing cost.And the N+ resilient coating that the diffusion residual layer at the back side is forming after attenuate, can make the thickness of IGBT required N-base in the time reaching identical forward blocking voltage less, and the NPN transistor that the back side embeds can reduce turn-off time and the turn-off power loss of device.
Brief description of the drawings
Fig. 1 is the cross-sectional view of existing IGBT.
Fig. 2 is the cross-sectional view of IGBT of the present invention.
Fig. 3 a-3g is that IGBT manufacture process of the present invention is illustrated each section of structure; Wherein, Fig. 3 a is the profile of original N-type silicon chip, and Fig. 3 b is that shown in Fig. 3 a, silicon chip High temperature diffusion forms the profile behind two diffusion regions; Fig. 3 c is the profile of front side of silicon wafer diffusion region shown in Fig. 3 b after processing; Fig. 3 d is that silicon chip shown in Fig. 3 c forms the profile after IGBT Facad structure; Fig. 3 e is the structural representation after the processing of silicon chip back side diffusion region shown in Fig. 3 d; Fig. 3 f is the profile that silicon chip back side shown in Fig. 3 e injects ion formation back of the body P+ collector area; Fig. 3 g is profile after the back of the body of silicon chip shown in Fig. 3 f P+ collector area back face metalization formation collector electrode.
Fig. 4 is the conduction voltage drop simulation comparison figure of conventional P T-IGBT device and IGBT device of the present invention.
Fig. 5 is the shutoff simulation waveform figure of conventional P T-IGBT device and IGBT device of the present invention.
Embodiment
In order to make technical problem to be solved by this invention, technical scheme and improvement effect clearer, below in conjunction with accompanying drawing, the present invention is described in further detail.
As shown in Figure 2, insulated gate bipolar transistor, comprises N-type base, P type base 30, back of the body P+ collector area 22, back of the body N+ collector area 21, N+ emitter region 28, gate oxide 26, emitter 29, gate electrode 27 and collector electrode 20; Described N-type base is made up of the N+ diffusion residual layer 31, N-base 25 and the N+ resilient coating 24 that stack gradually, and this insulated gate bipolar transistor manufacture process is as shown in Figure 3 a-3g, specific as follows:
Select the N-type single crystalline substrate 32 that crystal orientation is as shown in Figure 3 a <100>, its doping content is 4.2 × 10
13cm
-3, substrate thickness is 400um, is withstand voltage demand (such as 1700V, lower same) according to forward blocking voltage, capable of regulating doping content to 1 × 10
13cm
-3~ 1 × 10
14cm
-3.
As shown in Figure 3 b, N-type single crystalline substrate forms the N+ diffusion region 34, N-base 25 and the 2nd N+ diffusion region 33 that stack gradually after once two-sided high temperature is tied diffusion deeply, wherein N-base 25 thickness are adjustable to 100 ~ 300um according to the requirement of forward blocking voltage, and a N+ diffusion region 34 and the 2nd N+ diffusion region 33 are non-uniform doping.
As shown in Figure 3 c, a N+ diffusion region 34 forms N+ diffusion residual layer 31 after the processing steps such as grinding and polishing, and this layer thickness is controlled at (between 5 ~ 15um, being good) within several microns.Attenuate back substrate thickness is not less than 280um, can ensure that like this in post-production, silicon chip is not easily broken.
As shown in Figure 3 d, on N+ diffusion residual layer 31, first form P type base 30 by processing steps such as oxidation, the photoetching of P+ base, etching, boron Implantation, diffusions, then form gate oxide 26 at its surface oxidation, then on gate oxide, depositing polysilicon forms gate electrode 27, form N+ emitter region 28 by steps such as the photoetching of N+ emitter region, etching, arsenic ion injection, diffusions again, finally, again by photoetching, etching depositing metal formation emitter 29 on N+ collector area afterwards, the Facad structure of IGBT has substantially just formed like this.
As shown in Fig. 3 e, 3f, the 2nd N+ diffusion region 33 has formed the N+ resilient coating 24 at the back side after the attenuate such as grinding back surface and polishing, its THICKNESS CONTROL is tens of microns of left and right (8 ~ 20um is advisable), first form respectively P-resilient coating 23 by processing steps such as boron Implantation, diffusions, P-buffer layer thickness THICKNESS CONTROL (1 ~ 5um is advisable) within several microns, form back of the body P+ collector area 22 by processing steps such as boron Implantation, activation again, and then form back of the body N+ collector area 21 by processing steps such as photoetching, etching, phosphonium ion injection, diffusions.
As shown in Fig. 3 g, on back of the body P+ collector area 22 and back of the body N+ collector area 21, after depositing metal, form collector electrode 20, so far, a complete IGBT has just completed.
The present invention has used device simulation software Medici to carry out simulating, verifying to present embodiment.
Fig. 4 has compared the current processing disposal ability of conventional P T-IGBT and the present embodiment device, as can be seen from the figure, is all 100A/cm in Collector Current Density
2time, the conduction voltage drop of conventional P T-IGBT is 1.65V, the conduction voltage drop of the present embodiment device is 1.52V.The conduction voltage drop of the present embodiment device has reduced by 9%, and this is because positive N+ residual layer has increased surperficial electron concentration, thereby has improved conductivity modulation effect.
Fig. 5 has compared the turn-off time of conventional P T-IGBT and the present embodiment device, as can be seen from the figure, drops to 10% as basis for estimation taking current density, and the turn-off time of NFS-IGBT and traditional PT-IGBT is respectively 0.33u and 0.7us.That is to say, the turn-off speed of NFS is faster more than 1 times than traditional PT-IGBT, has also realized better the trade-off relation of conduction voltage drop and turn-off time, is specially adapted to high-speed switch application.
The foregoing is only preferred embodiment of the present invention, any amendment of doing within every the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.
Claims (6)
1. an insulated gate bipolar transistor, comprises N-type base, P type base, back of the body P+ collector area, N+ emitter region, gate oxide, emitter, gate electrode and collector electrode; Described N-type base comprises the N+ diffusion residual layer, N-base and the N+ resilient coating that stack gradually, described N+ diffusion residual layer and N+ resilient coating increase gradually from the initial outside doping content in border of N-base, it is characterized in that: described insulated gate bipolar transistor is further provided with P-resilient coating, back of the body N+ collector area, described P-resilient coating is between N+ resilient coating and back of the body P+ collector area, and described back of the body N+ collector area is positioned at the two ends of back of the body P+ collector area.
2. insulated gate bipolar transistor according to claim 1, is characterized in that: described N-base doping concentration is constant.
3. insulated gate bipolar transistor according to claim 1, is characterized in that: the thickness of described N+ diffusion residual layer is 5 ~ 15um.
4. insulated gate bipolar transistor according to claim 1, is characterized in that: described P-buffer layer thickness is 1 ~ 5um.
5. a preparation method for insulated gate bipolar transistor according to claim 1, is characterized in that: comprising:
(1) form respectively a N+ diffusion region and the 2nd N+ diffusion region in n type single crystal silicon both sides by High temperature diffusion;
(2) respectively a N+ diffusion region and the 2nd N+ diffusion region are processed to form to N+ diffusion residual layer and N+
Resilient coating;
(3) on N+ diffusion residual layer, form P type base, N+ emitter region, emitter;
(4) on N+ resilient coating, form P-resilient coating, back of the body P+ collector area, back of the body N+ collector area by injecting ion, after the metallization of back of the body Yu BeiN+ collector area, P+ collector area, form collector electrode.
6. preparation method according to claim 5, is characterized in that: described N+ resilient coating uses reduction process to make to the 2nd N+ diffusion region.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105514148A (en) * | 2015-10-22 | 2016-04-20 | 温州墨熵微电子有限公司 | Insulated gate bipolar transistor |
| CN108630749A (en) * | 2018-05-09 | 2018-10-09 | 西安理工大学 | A kind of super-pressure silicon carbide thyristor and preparation method thereof |
| CN113451399A (en) * | 2021-06-02 | 2021-09-28 | 广东美的白色家电技术创新中心有限公司 | Insulated gate bipolar transistor and preparation method thereof |
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| US6239466B1 (en) * | 1998-12-04 | 2001-05-29 | General Electric Company | Insulated gate bipolar transistor for zero-voltage switching |
| CN102439725A (en) * | 2010-09-25 | 2012-05-02 | 浙江大学 | Insulated gate bipolar transistor(igbt) and method for manufacturing same |
| CN103872113A (en) * | 2012-12-13 | 2014-06-18 | 中国科学院微电子研究所 | Tunneling reverse-conducting IGBT and manufacturing method thereof |
| CN103872053A (en) * | 2013-12-17 | 2014-06-18 | 上海联星电子有限公司 | TI-IGBT device |
-
2014
- 2014-07-25 CN CN201410356503.2A patent/CN104167356B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6239466B1 (en) * | 1998-12-04 | 2001-05-29 | General Electric Company | Insulated gate bipolar transistor for zero-voltage switching |
| CN102439725A (en) * | 2010-09-25 | 2012-05-02 | 浙江大学 | Insulated gate bipolar transistor(igbt) and method for manufacturing same |
| CN103872113A (en) * | 2012-12-13 | 2014-06-18 | 中国科学院微电子研究所 | Tunneling reverse-conducting IGBT and manufacturing method thereof |
| CN103872053A (en) * | 2013-12-17 | 2014-06-18 | 上海联星电子有限公司 | TI-IGBT device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105514148A (en) * | 2015-10-22 | 2016-04-20 | 温州墨熵微电子有限公司 | Insulated gate bipolar transistor |
| CN108630749A (en) * | 2018-05-09 | 2018-10-09 | 西安理工大学 | A kind of super-pressure silicon carbide thyristor and preparation method thereof |
| CN113451399A (en) * | 2021-06-02 | 2021-09-28 | 广东美的白色家电技术创新中心有限公司 | Insulated gate bipolar transistor and preparation method thereof |
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| CN104167356B (en) | 2017-04-19 |
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