CN105552873B - Surge protection device - Google Patents
Surge protection device Download PDFInfo
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- CN105552873B CN105552873B CN201610009821.0A CN201610009821A CN105552873B CN 105552873 B CN105552873 B CN 105552873B CN 201610009821 A CN201610009821 A CN 201610009821A CN 105552873 B CN105552873 B CN 105552873B
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- well layer
- surge
- protection device
- type substrate
- surge protection
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- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000002347 injection Methods 0.000 claims abstract description 22
- 239000007924 injection Substances 0.000 claims abstract description 22
- 239000007943 implant Substances 0.000 claims 2
- 230000010354 integration Effects 0.000 abstract description 7
- 230000002441 reversible effect Effects 0.000 description 15
- 230000015556 catabolic process Effects 0.000 description 10
- 238000007599 discharging Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Emergency Protection Circuit Devices (AREA)
Abstract
The present invention provides a surge protection device comprising: the N-type substrate is characterized in that a back P-well layer is arranged on the whole back surface of the N-type substrate, a front P-well layer is arranged on the front surface of the N-type substrate, and an N+ injection region is arranged on one side of the front P-well layer. The surge protection device of the invention, because of integrating TVS, TSS together, it presents TVS characteristic when suffering the forward surge; the surge protection device has the advantages that the surge protection device is characterized by TSS when subjected to negative surge, the problem that one TVS and one TSS are required to be used in series in application is completely solved, the integration level of the surge protection device is high, the product cost is low, the connection of external circuits is convenient, and the application is simple.
Description
Technical Field
The invention relates to the field of overvoltage protection products, in particular to a surge protection device.
Background
Currently, there are mainly two types of semiconductor devices commonly used as surge protection devices: firstly, a transient suppression diode (TVS for short, english translation is TRANSIENT VOLTAGE SUPPRESSOR), wherein the TVS is a voltage clamping type protection device, when the voltage at two ends of the TVS exceeds reverse breakdown voltage, the TVS is rapidly changed from a high resistance state to a low resistance state, and the voltage is stabilized at the clamping voltage, so that other electronic devices connected in parallel with the TVS are protected; and secondly, a semiconductor discharge tube (THYRISTOR SURGE SUPPRESSOR is called TSS for short), wherein the TSS is a voltage switch type protection device, when the voltage at two ends of the TSS exceeds the reverse breakdown voltage, the TSS rapidly changes from a high resistance state to a low resistance state, and the voltage is reduced to be almost zero, so that other electronic devices connected in parallel with the TSS are protected.
In a specific application scenario, an appropriate surge protection device needs to be selected according to the working performance of the protected electronic device. For example, in the case where the surge voltage may be either forward or reverse, it is desirable to use a unidirectional TVS in series with the TSS that clamps the surge voltage to within the normal operating voltage range of the protected electronic device when subjected to a forward surge; when subjected to a reverse surge, the TSS releases the surge voltage close to a short circuit so that the protected electronic device is not damaged by being subjected to excessive reverse voltages. Meanwhile, in order to simplify and integrate the circuit, it is currently common practice to: the unidirectional TVS and TSS wafers which are needed to be connected in series are manually stacked for packaging, and the packaging piece has a complex structure and high cost.
Disclosure of Invention
The invention aims to provide a surge protection device which can provide forward surge protection and reverse surge protection for a circuit, and has the advantages of higher integration level, simple structure and low cost.
In view of this, an embodiment of the present invention provides a surge protection device, including:
the N-type substrate is characterized in that a back P-well layer is arranged on the whole back surface of the N-type substrate, a front P-well layer is arranged on the front surface of the N-type substrate, and an N+ injection region is arranged on one side of the front P-well layer.
Further, the front-side P well layer is a front-side deep P well layer and a front-side shallow P well layer which are respectively positioned at two sides, and the front-side shallow P well layer is arranged at the side provided with the N+ injection region.
Further, a front deep N well is arranged below the front shallow P well layer.
Further, the back P-well layer is a back deep P-well layer and a back shallow P-well layer which are respectively positioned at two sides, and the back deep P-well layer is arranged at the side provided with the n+ injection region.
Further, a back deep N well is arranged on the back shallow P well layer.
Further, the back deep P-well layer is provided with a plurality of separated deep P-wells.
Further, a plurality of N+ injection regions are arranged.
Furthermore, short-circuit holes are formed among the N+ injection regions, and the impedance of the short-circuit holes is large.
The surge protection device of the invention, because of integrating TVS, TSS together, it presents TVS characteristic when suffering the forward surge; the TSS characteristic is shown when the TVS surge is subjected to negative surge, and the problem that one TVS and one TSS are required to be used in series in application is completely solved. The surge protection device is high in integration level, low in product cost, convenient to connect with external circuits and simple and convenient to apply.
Drawings
In order that the invention may be more readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof that are illustrated in the appended drawings, in which
FIG. 1 is a schematic cross-sectional view of a surge protection device according to a first embodiment of the present invention;
fig. 2 is an equivalent circuit diagram of a surge protection device provided by an embodiment of the present invention;
fig. 3 is a schematic cross-sectional view of a surge protection device according to a second embodiment of the present invention;
fig. 4 is a schematic cross-sectional view of a surge protection device according to a third embodiment of the present invention;
fig. 5 is a schematic cross-sectional view of a surge protection device according to a fourth embodiment of the present invention;
fig. 6 is a schematic cross-sectional view of a surge protection device according to a fifth embodiment of the present invention.
Detailed Description
The invention will be further elucidated with the following examples in connection with the accompanying drawings.
Referring to fig. 1, fig. 1 is a schematic cross-sectional view of a surge protection device according to an embodiment of the invention. As shown in fig. 1, the surge protection device 1 of the present embodiment includes: the semiconductor device comprises a metal layer 11 externally connected with a lead, and an N-type substrate, wherein a back P-well layer is arranged on the whole back of the N-type substrate, a front P-well layer is arranged on the front of the N-type substrate, and an N+ injection region is arranged on one side of the front P-well layer.
Preferably, the n+ implantation region is provided with a plurality of n+ implantation regions for adjusting the sustain current and the sustain voltage of the device. In another preferred embodiment, a short-circuit hole 12 is arranged between the n+ injection regions, and the short-circuit hole 12 has high impedance. The shorting holes are used to improve the tamper resistance of the device. Because the device area is too large, if there is no short hole, the device will have current concentrated in one part, and another part will have no current passing through, which will have adverse effect on the performance of the device.
Referring to fig. 2 in combination, fig. 2 is an equivalent circuit diagram of a surge protection device according to an embodiment of the present invention, and the following description will describe the working process of the surge protection device according to the present invention with reference to fig. 1 and 2:
1. when the device is impacted by forward surge, avalanche breakdown occurs at a reverse PN junction formed by the N-type substrate and the back P well, so that surge current is discharged. Meanwhile, the structure on the right of the device is N+ injection-front P well-N type substrate-back P well, and the device will not be opened due to high withstand voltage. So when a forward surge comes out, the surge is drained through the front P-well-N type substrate-back P-well region on the left side of the device. At this time, the device exhibits TVS performance. When the surge is over, the device is turned off immediately, and the problem of follow current does not occur.
2. When the device is impacted by negative surge, the reverse diode formed by the N+ injection-positive P well has high withstand voltage, and the reverse diode formed by the N-type substrate-positive P well has low withstand voltage, so that avalanche breakdown occurs in the N-type substrate-positive P well, and leakage current forms voltage drop through a short circuit hole after breakdown occurs. When the voltage drop is larger than the forward voltage drop of the front P-well-N+ injection, positive feedback occurs to the PNPN structure formed by the back P-well-N type substrate-front P-well-N+ injection. After the surge passes, the device is turned off immediately because the back P well is connected to low potential, and the problem of follow current does not occur.
From the above description, it can be seen that the operating circuit of the device is equivalent to the circuit of fig. 2 in which the TVS is connected in parallel with the TSS.
This embodiment has the following advantages:
the surge protection device of the invention, because of integrating TVS, TSS together, it presents TVS characteristic when suffering the forward surge; the TSS characteristic is shown when the TVS surge is subjected to negative surge, and the problem that one TVS and one TSS are required to be used in series in application is completely solved. The surge protection device is high in integration level, low in product cost, convenient to connect with external circuits and simple and convenient to apply.
Referring to fig. 3, fig. 3 is a schematic cross-sectional view of a surge protection device according to a second embodiment of the present invention. As shown in fig. 3, the surge protection device of the present embodiment includes: the N-type substrate, the whole back of N-type substrate is equipped with back P well layer, the front of N-type substrate is equipped with front P well layer, front P well layer is the front deep P well layer and the front shallow P well layer that are located both sides respectively, front shallow P well layer sets up in the one side that is equipped with N+ injection region.
This embodiment differs from the corresponding embodiment of fig. 1 in that: the front-side P well layer is a front-side deep P well layer and a front-side shallow P well layer which are respectively positioned at two sides, and the front-side shallow P well layer is arranged at the side provided with the N+ injection region. The other components are the same as those of the first embodiment, and will not be described here again. The advantages are that:
1. when the device is impacted by forward surge, avalanche breakdown occurs at a reverse PN junction formed by the N-type substrate and the back P well, so that surge current is discharged. The triode structure formed by the front deep P well, the N type substrate and the back P well has smaller negative resistance, and can effectively reduce residual voltage and improve surge discharge capacity. Meanwhile, the right structure of the device is N+ injection-front shallow P well-N type substrate-back P well, and the device will not be opened due to high withstand voltage. So when a forward surge comes out, the surge is drained through the front deep P-well-N-type substrate-back P-well region on the left side of the device. At this time, the device exhibits TVS performance. When the surge is over, the device is turned off immediately, and the problem of follow current does not occur.
2. When the device is impacted by negative surge, the reverse diode formed by the N+ injection-positive deep P well has high withstand voltage, and the reverse diode formed by the N-type substrate-positive shallow P well has low withstand voltage, so that avalanche breakdown occurs in the N-type substrate-positive shallow P well, and leakage current forms voltage drop through a short circuit hole after breakdown occurs. When the voltage drop is larger than the forward voltage drop of the front shallow P well-N+ injection, positive feedback occurs to the PNPN structure formed by the back P well-N type substrate-front shallow P well-N+ injection. After the surge passes, the device is turned off immediately because the back P well is connected to low potential, and the problem of follow current does not occur.
This embodiment has the following advantages:
the surge protection device of the invention, because of integrating TVS, TSS together, it presents TVS characteristic when suffering the forward surge; the TSS characteristic is shown when the TVS surge is subjected to negative surge, and the problem that one TVS and one TSS are required to be used in series in application is completely solved. The surge protection device is high in integration level, low in product cost, convenient to connect with external circuits and simple and convenient to apply.
Referring to fig. 4, fig. 4 is a schematic cross-sectional view of a surge protection device according to a third embodiment of the present invention. As shown in fig. 4, the surge protection device of the present embodiment includes: the N-type substrate, the whole back of N-type substrate is equipped with back P well layer, the front of N-type substrate is equipped with front P well layer, the right side of front P well layer is equipped with N+ injection zone, back P well layer is the back deep P well layer and the back shallow P well layer that are located both sides respectively, back deep P well layer sets up the one side that is equipped with N+ injection zone.
This embodiment differs from the corresponding embodiment of fig. 1 in that: the back P well layer is a back deep P well layer and a back shallow P well layer which are respectively positioned at two sides, and the back deep P well layer is arranged at the side provided with the N+ injection region. The other components are the same as those of the first embodiment, and will not be described here again. The device has the advantages that when the device is impacted by reverse surge, the arrangement of the back deep P well layer can improve the surge discharging capability of the device and reduce residual voltage.
In another preferred embodiment, please refer to fig. 5 in combination, the back deep P-well layer is provided with a plurality of separated deep P-wells. The advantages are that: the junction area of the back deep P well-N type substrate is increased, and the reverse surge discharging capability of the device is further improved.
The operation is the same as in the embodiment of fig. 1, and will not be described again here.
This embodiment has the following advantages:
the surge protection device of the invention, because of integrating TVS, TSS together, it presents TVS characteristic when suffering the forward surge; the TSS characteristic is shown when the TVS surge is subjected to negative surge, and the problem that one TVS and one TSS are required to be used in series in application is completely solved. The surge protection device is high in integration level, low in product cost, convenient to connect with external circuits and simple and convenient to apply.
Referring to fig. 6, fig. 6 is a schematic cross-sectional view of a surge protection device according to a fifth embodiment of the present invention. As shown in fig. 5, the surge protection device of the present embodiment includes: the N-type substrate, the whole back of N-type substrate is equipped with back dark P well layer and the shallow P well layer in back that is located both sides respectively, back dark P well layer sets up in the one side that is equipped with N+ injection zone, the N-type substrate openly is equipped with front dark P well layer and the front shallow P well layer that is located both sides respectively, be equipped with N+ injection zone on the front shallow P well layer, front dark N well is equipped with in front shallow P well layer below, be equipped with back dark N well on the back shallow P well layer.
This embodiment differs from the third embodiment corresponding to fig. 4 in that: and a front deep N well is arranged below the front shallow P well layer, and a back deep N well is arranged on the back shallow P well layer. The other parts are the same as those of the embodiment, and are not described herein. The device has the advantages that the breakdown voltage of the device when subjected to reverse surge can be adjusted by adjusting the front deep N well; the breakdown voltage of the device when subjected to forward surge can be regulated by regulating the back deep N well, and meanwhile, the forward surge discharging capability of the device is further improved, and the residual voltage is reduced.
The operation is the same as in the embodiment of fig. 1, and will not be described again here.
This embodiment has the following advantages:
the surge protection device of the invention, because of integrating TVS, TSS together, it presents TVS characteristic when suffering the forward surge; the TSS characteristic is shown when the TVS surge is subjected to negative surge, and the problem that one TVS and one TSS are required to be used in series in application is completely solved. The surge protection device is high in integration level, low in product cost, convenient to connect with external circuits and simple and convenient to apply.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the invention.
Claims (3)
1. A surge protection device, comprising:
the N-type substrate is provided with a back P-well layer on the whole back surface, a front P-well layer is arranged on the whole front surface of the N-type substrate, the front P-well layer comprises a front deep P-well layer and a front shallow P-well layer which are adjacently arranged in the direction parallel to the surface of the N-type substrate, and an N+ injection region is arranged in the front shallow P-well layer and is close to one side of the positive electrode of the N-type substrate;
the back P well layer comprises a back deep P well layer and a back shallow P well layer which are adjacently arranged in the direction parallel to the surface of the N-type substrate, and the front shallow P well layer corresponds to the back deep P well layer in the direction parallel to the surface of the N-type substrate;
the back deep P-well layer is provided with a plurality of separate deep P-wells.
2. The surge protection device of claim 1 wherein the n+ implant region is provided in plurality.
3. The surge protection device of claim 2 wherein a shorting hole is provided between the plurality of n+ implant regions, the shorting hole having a high impedance.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610009821.0A CN105552873B (en) | 2016-01-05 | 2016-01-05 | Surge protection device |
| PCT/CN2016/095630 WO2017118028A1 (en) | 2016-01-05 | 2016-08-17 | Surge protector device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610009821.0A CN105552873B (en) | 2016-01-05 | 2016-01-05 | Surge protection device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105552873A CN105552873A (en) | 2016-05-04 |
| CN105552873B true CN105552873B (en) | 2024-03-29 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610009821.0A Active CN105552873B (en) | 2016-01-05 | 2016-01-05 | Surge protection device |
Country Status (2)
| Country | Link |
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| CN (1) | CN105552873B (en) |
| WO (1) | WO2017118028A1 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105552873B (en) * | 2016-01-05 | 2024-03-29 | 深圳市槟城电子股份有限公司 | Surge protection device |
| CN106783949A (en) * | 2016-12-19 | 2017-05-31 | 东莞市阿甘半导体有限公司 | Unidirectional TVS structures and its manufacture method |
| CN108428697A (en) * | 2017-11-09 | 2018-08-21 | 上海长园维安微电子有限公司 | A kind of low-capacitance bidirectional band negative resistance TVS device |
| CN108922885A (en) * | 2018-08-06 | 2018-11-30 | 上海长园维安微电子有限公司 | A kind of high-power unidirectional TVS device |
| CN111223914A (en) * | 2019-07-01 | 2020-06-02 | 上海维安半导体有限公司 | Semiconductor discharge tube with negative resistance characteristic and manufacturing method thereof |
| CN110459593B (en) * | 2019-08-01 | 2024-05-28 | 富芯微电子有限公司 | Low-clamping-voltage unidirectional TVS device and manufacturing method thereof |
| CN112614782B (en) * | 2020-12-15 | 2024-06-18 | 扬州杰利半导体有限公司 | Manufacturing method of unidirectional negative resistance surge protection chip |
| CN117116936B (en) * | 2023-09-25 | 2024-04-26 | 深圳长晶微电子有限公司 | Unidirectional surge protection device and manufacturing method thereof |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN105552873A (en) | 2016-05-04 |
| WO2017118028A1 (en) | 2017-07-13 |
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