CN104505341A - Manufacturing method of semiconductor discharge tube - Google Patents
Manufacturing method of semiconductor discharge tube Download PDFInfo
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- CN104505341A CN104505341A CN201410797601.XA CN201410797601A CN104505341A CN 104505341 A CN104505341 A CN 104505341A CN 201410797601 A CN201410797601 A CN 201410797601A CN 104505341 A CN104505341 A CN 104505341A
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- boron
- diffusion
- carried out
- photoetching
- silicon chip
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 229910052796 boron Inorganic materials 0.000 claims abstract description 64
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 60
- 238000009792 diffusion process Methods 0.000 claims abstract description 54
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 50
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 49
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 49
- 239000010703 silicon Substances 0.000 claims abstract description 49
- 230000003647 oxidation Effects 0.000 claims abstract description 37
- 238000001259 photo etching Methods 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 20
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 12
- 230000007797 corrosion Effects 0.000 claims abstract description 12
- 238000005260 corrosion Methods 0.000 claims abstract description 12
- 238000005275 alloying Methods 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 6
- 238000001465 metallisation Methods 0.000 claims abstract description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 10
- 239000011574 phosphorus Substances 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 2
- 230000007547 defect Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001012 protector Effects 0.000 description 1
- APTZNLHMIGJTEW-UHFFFAOYSA-N pyraflufen-ethyl Chemical compound C1=C(Cl)C(OCC(=O)OCC)=CC(C=2C(=C(OC(F)F)N(C)N=2)Cl)=C1F APTZNLHMIGJTEW-UHFFFAOYSA-N 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Cold Cathode And The Manufacture (AREA)
- Thyristors (AREA)
Abstract
The invention discloses a manufacturing method of a semiconductor discharge tube. The manufacturing method comprises the following steps: (1), performing primary oxidation on a silicon wafer; (2), photoetching a deep-boron area of the silicon wafer; (3), etching the position which is to be formed into the deep-boron area by use of a silicon etch solution so as to form a groove, wherein the groove corresponds to the shape of the deep-boron area; (4) photoetching a base area; (5), performing diluted boron diffusion; (6), performing diluted boron oxidation; (7),photoetching an emitting area; (8), performing phosphor diffusion; (9), performing phosphor oxidation; (10), performing double-sided lead photoetching; (11), performing double-sided metallization on the silicon wafer; (12), photoething metal; and (13), alloying the silicon wafer under a vacuum state. According to the manufacturing method, deep-boron effect is realized by virtue of a corrosion structure combining diluted boron diffusion, and processes are reduced, the cost is greatly saved, detects such as dislocation and stacking fault of the silicon wafer due to a high temperature in the deep boron process are also avoided, and thus the problem that current leakage exceeds the standard can not be caused.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor discharge tube, belong to semiconductor discharge tube manufacturing process technology field.
Background technology
Semiconductor discharge tube is a kind of over-voltage protector; it relies on the breakdown current trigger device conducting electric discharge of PN junction; very large surge current or pulse current can be flow through; during use, semiconductor discharge tube directly can be connected across protected circuit two ends; in the scope of its puncture voltage, constitute the scope of overvoltage protection.
Semiconductor discharge tube when sheet thick constant, in order to obtain preferably thunderbolt and power frequency effect, general technological means carries out boron intensification in the local of silicon chip.Local boron deepens the width decreasing growing base area, thus reduces on-state voltage drop V
t, improve through-current capability, final acquisition is struck by lightning and power frequency effect preferably.
In order to deepen at local boron, ensure to maintain electric current, current technique first carries out dark boron diffusion, dark boron oxidation, then carry out light boron diffusion, the oxidation of light boron, thus form the Shen Peng district of local simultaneously.
Such as, but in prior art processes, dark boron diffusion is generally carried out at 1050 ~ 1150 DEG C, and at these elevated temperatures, silicon chip very easily produces defect, the defect such as dislocation, fault, and these defects will cause leakage current to exceed standard, and drastically influence the quality of discharge tube.In addition, dark boron oxidization time is longer, usually needs 30 ~ 120 hours, too increases production cost.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of manufacture method of semiconductor discharge tube, and this manufacture method cost is low, and through-current capability is strong.
In order to solve the problems of the technologies described above, technical scheme of the present invention is:
A manufacture method for semiconductor discharge tube, comprises the following steps:
(1) once oxidation is carried out to the two sides of silicon chip simultaneously, form once oxidation layer.
(2) photoetching is carried out to silicon chip once oxidation Ceng Shenpeng district.
(3) adopt silicon etch solution to corrode the silicon chip surface position for forming Shen Peng district, corrosion formation one groove, described groove is corresponding with the shape in Shen Peng district; Described groove can selected depth be 30-60 μm.
Traditional processing technology carries out the diffusion of dark boron and the oxidation of dark boron after the photoetching of Shen Peng district, and the temperature that dark boron spreads is within the scope of 1050-1150 DEG C, and dark boron diffusion time is at 50-100 minute; The temperature of dark boron oxidation is within the scope of 1220-1270 DEG C, and dark boron oxidization time is at 30-120 hour.Manufacture method of the present invention adopts step (3) to substitute above-mentioned dark boron diffusion and the oxidation of dark boron.
(4) photoetching is carried out to the base of silicon chip.
(5) at 950-1050 DEG C, light boron diffusion is carried out, diffusion time is 50-100 minute, under identical diffusion velocity, due to the existence of the groove that corrosion is formed, the junction depth of groove boron diffusion, by being greater than the region of other position boron diffusions, forms outstanding Shen Peng district; Namely the junction depth difference that the junction depth of groove boron diffusion and other position boron spread is the degree of depth of erosion grooves.
(6) at 1220-1270 DEG C, carry out light boron oxidation, oxidization time is 7-15 hour.
(7) photoetching is carried out to the emitter region of silicon chip.
(8) at 1130-1170 DEG C, carry out phosphorus diffusion, diffusion time is 40-60 minute.
(9) at 1150-1190 DEG C, carry out phosphorus oxidation, oxidization time is 40-100 minute.
(10) two-sided lead-in wire photoetching is carried out.
(11) two-sided metallization is carried out to silicon chip.
(12) metal lithographic.
(13) under vacuum conditions alloying is carried out to silicon chip.
Manufacture method of the present invention realizes dark effect of boron, its advantage by etching process in conjunction with light boron diffusion:
1) traditional dark boron diffusion, dark boron are oxidized two steps and omit, the substitute is the step of Shen Peng district corrosion, decrease the operation of technique;
2) in dark boron diffusion process, the temperature of dark boron diffusion is within the scope of 1050-1150 DEG C, and dark boron diffusion time is at 50-100 minute; And the temperature of dark boron oxidation is within the scope of 1220-1270 DEG C, dark boron oxidization time is at 30-120 hour; Omit the technical process of the diffusion of dark boron, dark boron oxidation, can be significantly cost-saving;
3) omit the technical process of the diffusion of dark boron, dark boron oxidation, avoid the hot environment in above-mentioned dark boron technical process, thus decrease the defect of silicon chip as dislocation, fault etc., avoid therefore and the leakage current caused exceeds standard.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Fig. 1 is the present invention's light boron diffusion schematic diagram.
Embodiment
Embodiment 1
(1) once oxidation is carried out to the two sides of silicon chip simultaneously, form once oxidation layer.
(2) photoetching is carried out to silicon chip once oxidation Ceng Shenpeng district.
(3) adopt silicon etch solution to corrode the silicon chip surface position for forming Shen Peng district, the groove 1 that corrosion formation one 60 μm is dark, described groove 1 is corresponding with the shape in Shen Peng district, as shown in Figure 1.
(4) photoetching is carried out to the base of silicon chip.
(5) at 1000 DEG C, carry out light boron diffusion, diffusion time is 100 minutes.Under identical diffusion velocity, dispersal direction as shown by the arrows in Figure 1, due to the existence of the groove 1 that corrosion is formed, the junction depth of groove 1 place boron diffusion will be greater than the region of other position boron diffusions, formed to give prominence to and (give prominence to distance corresponding with depth of groove, here be approximately 60 μm) Shen Peng district P1, other positions are Dan Peng district P2.
(6) at 1250 DEG C, carry out light boron oxidation, oxidization time is 12 hours.
(7) photoetching is carried out to the emitter region of silicon chip.
(8) at 1150 DEG C, carry out phosphorus diffusion, diffusion time is 55 minutes;
(9) at 1190 DEG C, carry out phosphorus oxidation, oxidization time is 90 minutes;
(10) two-sided lead-in wire photoetching is carried out.
(11) two-sided metallization is carried out to silicon chip.
(12) metal lithographic.
(13) under vacuum conditions alloying is carried out to silicon chip.
Embodiment 2
(1) once oxidation is carried out to the two sides of silicon chip simultaneously, form once oxidation layer.
(2) photoetching is carried out to silicon chip once oxidation Ceng Shenpeng district.
(3) adopt silicon etch solution to corrode the silicon chip surface position for forming Shen Peng district, the groove that corrosion formation one 55 μm is dark, described groove is corresponding with the shape in Shen Peng district, as shown in Figure 1.
(4) photoetching is carried out to the base of silicon chip.
(5) at 950 DEG C, carry out light boron diffusion, diffusion time is 60 minutes.Under identical diffusion velocity, dispersal direction as shown by the arrows in Figure 1, due to the existence of the groove that corrosion is formed, the junction depth of groove boron diffusion will be greater than the region of other position boron diffusions, formed to give prominence to and (give prominence to distance corresponding with depth of groove, here be approximately 55 μm) Shen Peng district P1, other positions are Dan Peng district P2.
(6) at 1250 DEG C, carry out light boron oxidation, oxidization time is 10 hours;
(7) photoetching is carried out to the emitter region of silicon chip;
(8) at 1170 DEG C, carry out phosphorus diffusion, diffusion time is 55 minutes;
(9) at 1190 DEG C, carry out phosphorus oxidation, oxidization time is 50 minutes;
(10) two-sided lead-in wire photoetching is carried out.
(11) two-sided metallization is carried out to silicon chip.
(12) metal lithographic.
(13) under vacuum conditions alloying is carried out to silicon chip.
Embodiment 3
(1) once oxidation is carried out to the two sides of silicon chip simultaneously, form once oxidation layer.
(2) photoetching is carried out to silicon chip once oxidation Ceng Shenpeng district.
(3) adopt silicon etch solution to corrode the silicon chip surface position for forming Shen Peng district, the groove that corrosion formation one 45 μm is dark, described groove is corresponding with the shape in Shen Peng district, as shown in Figure 1.
(4) photoetching is carried out to the base of silicon chip.
(5) at 1050 DEG C, carry out light boron diffusion, diffusion time is 90 minutes.Under identical diffusion velocity, dispersal direction as shown by the arrows in Figure 1, due to the existence of the groove that corrosion is formed, the junction depth of groove boron diffusion will be greater than the region of other position boron diffusions, formed to give prominence to and (give prominence to distance corresponding with depth of groove, here be approximately 45 μm) Shen Peng district P1, other positions are Dan Peng district P2.
(6) at 1200 DEG C, carry out light boron oxidation, oxidization time is 15 hours.
(7) photoetching is carried out to the emitter region of silicon chip.
(8) at 1150 DEG C, carry out phosphorus diffusion, diffusion time is 50 minutes.
(9) at 1190 DEG C, carry out phosphorus oxidation, oxidization time is 100 minutes.
(10) two-sided lead-in wire photoetching is carried out.
(11) two-sided metallization is carried out to silicon chip.
(12) metal lithographic.
(13) under vacuum conditions alloying is carried out to silicon chip.
Above-mentioned 3 embodiments decrease energy consumption required in the technical process of the diffusion of dark boron and the oxidation of dark boron, thus decrease production cost; After testing, the product that the inventive method obtains obtains product with conventional method and compares, and leakage current qualification rate improves 2-3%.
Above-described embodiment does not limit the present invention in any way, and the technical scheme that the mode that every employing is equal to replacement or equivalent transformation obtains all drops in protection scope of the present invention.
Claims (2)
1. a manufacture method for semiconductor discharge tube, is characterized in that comprising the following steps:
(1) once oxidation is carried out to the two sides of silicon chip simultaneously, form once oxidation layer;
(2) photoetching is carried out to silicon chip once oxidation Ceng Shenpeng district;
(3) adopt silicon etch solution to corrode the silicon chip surface position for forming Shen Peng district, corrosion formation one groove, described groove is corresponding with the shape in Shen Peng district;
(4) photoetching is carried out to the base of silicon chip;
(5) at 950-1050 DEG C, light boron diffusion is carried out, diffusion time is 50-100 minute, under identical diffusion velocity, due to the existence of the groove that corrosion is formed, the junction depth of groove boron diffusion, by being greater than the region of other position boron diffusions, forms outstanding Shen Peng district;
(6) at 1220-1270 DEG C, carry out light boron oxidation, oxidization time is 7-15 hour;
(7) photoetching is carried out to the emitter region of silicon chip;
(8) at 1130-1170 DEG C, carry out phosphorus diffusion, diffusion time is 40-60 minute;
(9) at 1150-1190 DEG C, carry out phosphorus oxidation, oxidization time is 40-100 minute;
(10) two-sided lead-in wire photoetching is carried out;
(11) two-sided metallization is carried out to silicon chip;
(12) metal lithographic;
(13) under vacuum conditions alloying is carried out to silicon chip.
2. the manufacture method of a kind of semiconductor discharge tube according to claim 1, is characterized in that: the degree of depth of described groove is 30-60 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410797601.XA CN104505341B (en) | 2014-12-18 | 2014-12-18 | A kind of manufacture method of semiconductor discharge tube |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410797601.XA CN104505341B (en) | 2014-12-18 | 2014-12-18 | A kind of manufacture method of semiconductor discharge tube |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104505341A true CN104505341A (en) | 2015-04-08 |
| CN104505341B CN104505341B (en) | 2017-06-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201410797601.XA Active CN104505341B (en) | 2014-12-18 | 2014-12-18 | A kind of manufacture method of semiconductor discharge tube |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105552873A (en) * | 2016-01-05 | 2016-05-04 | 深圳市槟城电子有限公司 | Surge protection device |
| CN113314409A (en) * | 2021-05-27 | 2021-08-27 | 江苏晟驰微电子有限公司 | Manufacturing process of VBAT end low-voltage protection chip of mobile phone |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3972113A (en) * | 1973-05-14 | 1976-08-03 | Mitsubishi Denki Kabushiki Kaisha | Process of producing semiconductor devices |
| CN202094126U (en) * | 2011-05-31 | 2011-12-28 | 无锡固电半导体股份有限公司 | High-power transistor for high-voltage high-frequency quick switch |
| CN102800757A (en) * | 2012-08-28 | 2012-11-28 | 英利集团有限公司 | N-type solar cell and manufacturing process thereof |
| CN104078353A (en) * | 2013-03-28 | 2014-10-01 | 上海瞬雷电子科技有限公司 | Backward GPP (Glass Passivation Pellet) high voltage diode chip in automobile module, and production technology |
-
2014
- 2014-12-18 CN CN201410797601.XA patent/CN104505341B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3972113A (en) * | 1973-05-14 | 1976-08-03 | Mitsubishi Denki Kabushiki Kaisha | Process of producing semiconductor devices |
| CN202094126U (en) * | 2011-05-31 | 2011-12-28 | 无锡固电半导体股份有限公司 | High-power transistor for high-voltage high-frequency quick switch |
| CN102800757A (en) * | 2012-08-28 | 2012-11-28 | 英利集团有限公司 | N-type solar cell and manufacturing process thereof |
| CN104078353A (en) * | 2013-03-28 | 2014-10-01 | 上海瞬雷电子科技有限公司 | Backward GPP (Glass Passivation Pellet) high voltage diode chip in automobile module, and production technology |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105552873A (en) * | 2016-01-05 | 2016-05-04 | 深圳市槟城电子有限公司 | Surge protection device |
| WO2017118028A1 (en) * | 2016-01-05 | 2017-07-13 | 深圳市槟城电子有限公司 | Surge protector device |
| CN105552873B (en) * | 2016-01-05 | 2024-03-29 | 深圳市槟城电子股份有限公司 | Surge protection device |
| CN113314409A (en) * | 2021-05-27 | 2021-08-27 | 江苏晟驰微电子有限公司 | Manufacturing process of VBAT end low-voltage protection chip of mobile phone |
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| Publication number | Publication date |
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| CN104505341B (en) | 2017-06-06 |
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Effective date of registration: 20180601 Address after: 518116 Shenzhen, Longgang, Guangdong province Longgang Street Baolong community Baolong four road 3 Lan Pu Yuan Industrial Zone 1 Factory A501 Patentee after: Shenzhen Bencent Electronics Co., Ltd. Address before: 201900 No. 64 lane, Tangjia lane, Luo Dian Town, Baoshan District, Shanghai 2 Patentee before: Jin Baoxing |
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Address after: 518116 Shenzhen, Longgang, Guangdong province Longgang Street Baolong community Baolong four road 3 Lan Pu Yuan Industrial Zone 1 Factory A501 Patentee after: Shenzhen Penang Electronics Co.,Ltd. Address before: 518116 Shenzhen, Longgang, Guangdong province Longgang Street Baolong community Baolong four road 3 Lan Pu Yuan Industrial Zone 1 Factory A501 Patentee before: Shenzhen Bencent Electronics Co.,Ltd. |
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