CN104485282A - Manufacturing method of discharge tube chip - Google Patents
Manufacturing method of discharge tube chip Download PDFInfo
- Publication number
- CN104485282A CN104485282A CN201410797320.4A CN201410797320A CN104485282A CN 104485282 A CN104485282 A CN 104485282A CN 201410797320 A CN201410797320 A CN 201410797320A CN 104485282 A CN104485282 A CN 104485282A
- Authority
- CN
- China
- Prior art keywords
- photoetching
- chip
- silicon chip
- oxidation
- carried out
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 38
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 38
- 239000010703 silicon Substances 0.000 claims abstract description 38
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 36
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052796 boron Inorganic materials 0.000 claims abstract description 29
- 230000003647 oxidation Effects 0.000 claims abstract description 28
- 238000001259 photo etching Methods 0.000 claims abstract description 25
- 238000009792 diffusion process Methods 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 18
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 8
- 230000007797 corrosion Effects 0.000 claims abstract description 8
- 238000005260 corrosion Methods 0.000 claims abstract description 8
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 8
- 239000011574 phosphorus Substances 0.000 claims abstract description 8
- 238000005275 alloying Methods 0.000 claims abstract description 4
- 239000007788 liquid Substances 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims abstract description 4
- 238000001465 metallisation Methods 0.000 claims abstract description 4
- 238000005245 sintering Methods 0.000 abstract description 5
- 230000007547 defect Effects 0.000 abstract description 4
- 238000005520 cutting process Methods 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000010257 thawing Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000001012 protector Effects 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Dicing (AREA)
Abstract
The invention discloses a manufacturing method of a discharge tube chip. The manufacturing method comprises steps as follows: (1), a silicon chip is subjected to one-time oxidation; (2), a deep boron zone is subjected to photoetching; (3), deep boron diffusion is performed; (4), deep boron oxidation is performed; (5), a base region of the silicon chip is subjected to photoetching; (6), light boron diffusion is performed; (7), light boron oxidation is performed; (8), an emitter region of the silicon chip is subjected to photoetching; (9), phosphorus diffusion is performed; (10), mesa recess photoetching is performed between two chips on the silicon chip; (11), mesa recess corrosion is performed on a mesa recess photoetching part by a corrosive liquid; (12), oxidation is performed for 40-100 minutes at the temperature of 1,150 DEG C-1,190 DEG C; (13), two-sided lead photoetching is performed on the silicon chip; (14), two-sided metallization is performed on the silicon chip; (15), metal photoetching is performed; and (16), vacuum alloying is performed. According to the manufacturing method, the problem of cut surface short circuit caused in the sintering process of the chip can be effectively avoided, the chip quality is ensured, the production cost is reduced, chip defects caused in the high-temperature environment are avoided, and scribing is further facilitated.
Description
Technical field
The present invention relates to a kind of manufacture method of discharge tube chip, belong to semiconductor discharge tube manufacturing process technology field.
Background technology
Semiconductor discharge tube is a kind of over-voltage protector; it relies on the breakdown current trigger device conducting electric discharge of PN junction; very large surge current or pulse current can be flow through; during use, semiconductor discharge tube directly can be connected across protected circuit two ends; in the scope of its puncture voltage, constitute the scope of overvoltage protection.
In the making later stage of semiconductor discharge tube, need to cut (i.e. scribing) silicon chip, to obtain single discharge tube chip, the cut surface formed in this cutting process then loses insulation protection.Discharge tube chip after cutting needs to sinter, and chip places weld tabs, weld tabs presses copper electrode.In sintering process, chip is connected with copper electrode by weld tabs thawing.In the process, when solder is too much or when electrode is more inclined, the solder of fusing will flow on the cut surface of chip, will cause chip short circuit after solder solidification.The integrated chip packing forms particularly grown up at present, because base plate does not have boss, easilier causes chip short circuit because solder is excessive.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of manufacture method of discharge tube chip, the cut surface short circuit problem that the method can effectively avoid chip to cause in sintering process.
In order to solve the problems of the technologies described above, technical scheme of the present invention is: a kind of manufacture method of discharge tube chip, and it comprises the following steps:
(1) once oxidation is carried out to the two sides of silicon chip simultaneously, form once oxidation layer.
(2) photoetching is carried out to silicon chip once oxidation Ceng Shenpeng district.
(3) dark boron diffusion, the temperature of dark boron diffusion is within the scope of 1050-1150 DEG C, and dark boron diffusion time is at 50-100 minute.
(4) dark boron oxidation, the temperature of dark boron oxidation is within the scope of 1220-1270 DEG C, and dark boron oxidization time is at 30-120 hour.
(5) photoetching is carried out to the base of silicon chip.
(6) at 950-1050 DEG C, carry out light boron diffusion, diffusion time is 50-100 minute.
(7) at 1220-1270 DEG C, carry out light boron oxidation, oxidization time is 7-15 hour.
(8) photoetching is carried out to the emitter region of silicon chip.
(9) at 1130-1170 DEG C, carry out phosphorus diffusion, diffusion time is 40-60 minute.
(10) mesa recess photoetching is carried out on silicon chip between two chips.
(11) corrosive liquid is utilized to carry out mesa recess corrosion to mesa recess photoetching position.Described corrosive liquid is silicon etch solution.When the later stage carries out chip cutting, line of cut is in the middle part of the mesa recess of corrosion, and the chip edge after cutting is arc, and when the later stage sinters, the solder of fusing can not flow on the cut surface of chip, thus avoids chip short circuit problem.
(12) be oxidized at 1150-1190 DEG C, oxidization time is 40-100 minute.
The oxidizing process of this step comprises two levels: first level is oxidized mesa recess position, makes the mesa recess position of corrosion produce oxide layer, forms insulation.Relative in the enterprising oozy glass passivation of mesa recess, not only cost is few, and is beneficial to scribing in the later stage.Second level carries out phosphorus oxidation to after phosphorus diffusion.The oxidation of two levels is merged in a procedure, also greatly reduces production cost, avoids silicon chip is repeatedly in hot environment, avoid the defect causing chip in hot environment.
(13) two-sided lead-in wire photoetching is carried out to silicon chip.
(14) two-sided metallization is carried out to silicon chip.
(15) metal lithographic.
(16) under vacuum conditions alloying is carried out to silicon chip.
The cut surface short circuit problem that the inventive method can effectively avoid chip to cause in sintering process, ensure that the rate of finished products of chip package, reduces production cost, avoids multiple high temp to process the chip defect caused simultaneously, but also is conducive to scribing.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Fig. 1 is mesa recess schematic diagram between two chips.
Embodiment
(1) once oxidation is carried out to the two sides of silicon chip simultaneously, form once oxidation layer.
(2) photoetching is carried out to silicon chip once oxidation Ceng Shenpeng district.
(3) dark boron diffusion, the temperature of dark boron diffusion is within the scope of 1100 DEG C, and dark boron spreads 100 minutes.
(4) dark boron oxidation, the temperature of dark boron oxidation is within the scope of 1250 DEG C, and dark boron is oxidized 100 hours.
(5) photoetching is carried out to the base of silicon chip.
(6) at 1050 DEG C, carry out light boron diffusion, spread 100 minutes.
(7) at 1250 DEG C, carry out light boron oxidation, oxidization time is 10 hours.
(8) photoetching is carried out to the emitter region of silicon chip.
(9) at 1150 DEG C, carry out phosphorus diffusion, spread 50 minutes.
(10) mesa recess photoetching is carried out on silicon chip between two chips.
(11) utilize silicon etch solution to carry out mesa recess corrosion to mesa recess photoetching position, form mesa recess 1, as shown in Figure 1.When the later stage carries out chip cutting, line of cut is in the middle part of the mesa recess 1 of corrosion, and the chip edge after cutting is arc, and when the later stage sinters, the solder of fusing can not flow on the cut surface of chip, thus avoids chip short circuit problem.
(12) at 1150 DEG C, dry O is filled with
2be oxidized, oxidization time is 60 minutes.
First the oxidation of this step is be oxidized mesa recess position, makes the mesa recess position of corrosion produce oxidation, forms insulation.Abandon traditional being formed in the enterprising oozy glass passivation of mesa recess 1 to insulate, not only cost is few, and is beneficial to scribing in the later stage.Moreover be carry out phosphorus oxidation to after phosphorus diffusion.Whole oxidizing process merges, and greatly reduces production cost, avoids silicon chip is repeatedly in hot environment, avoids the defect causing chip in hot environment.
(13) two-sided lead-in wire photoetching is carried out to silicon chip.
(14) two-sided metallization is carried out to silicon chip.
(15) metal lithographic.
(16) under vacuum conditions alloying is carried out to silicon chip.
Cutting scribing is carried out to silicon chip and obtains single discharge tube chip, the discharge tube chip after cutting places weld tabs, weld tabs presses copper electrode.In sintering process, chip is connected with copper electrode by weld tabs thawing.Because surface is through the existence of the mesa recess 1 of oxidation formation insulating barrier, even if when solder is too much or electrode is more inclined, the solder melted also can be avoided to flow on the cut surface of chip, chip short circuit can not be caused.
Above-described embodiment does not limit the present invention in any way, and the technical scheme that the mode that every employing is equal to replacement or equivalent transformation obtains all drops in protection scope of the present invention.
Claims (2)
1. a manufacture method for discharge tube chip, is characterized in that comprising the following steps:
(1) once oxidation is carried out to the two sides of silicon chip simultaneously, form once oxidation layer;
(2) photoetching is carried out to silicon chip once oxidation Ceng Shenpeng district;
(3) dark boron diffusion, the temperature of dark boron diffusion is within the scope of 1050-1150 DEG C, and dark boron diffusion time is at 50-100 minute;
(4) dark boron oxidation, the temperature of dark boron oxidation is within the scope of 1220-1270 DEG C, and dark boron oxidization time is at 30-120 hour;
(5) photoetching is carried out to the base of silicon chip;
(6) at 950-1050 DEG C, carry out light boron diffusion, diffusion time is 50-100 minute;
(7) at 1220-1270 DEG C, carry out light boron oxidation, oxidization time is 7-15 hour;
(8) photoetching is carried out to the emitter region of silicon chip;
(9) at 1130-1170 DEG C, carry out phosphorus diffusion, diffusion time is 40-60 minute;
(10) mesa recess photoetching is carried out on silicon chip between two chips;
(11) silicon etch solution is utilized to carry out mesa recess corrosion to mesa recess photoetching position;
(12) be oxidized at 1150-1190 DEG C, oxidization time is 40-100 minute;
(13) two-sided lead-in wire photoetching is carried out to silicon chip;
(14) two-sided metallization is carried out to silicon chip;
(15) metal lithographic;
(16) under vacuum conditions alloying is carried out to silicon chip.
2. the manufacture method of a kind of discharge tube chip according to claim 1, is characterized in that: in described step (11), and described corrosive liquid is silicon etch solution.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410797320.4A CN104485282B (en) | 2014-12-18 | 2014-12-18 | Manufacturing method of discharge tube chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410797320.4A CN104485282B (en) | 2014-12-18 | 2014-12-18 | Manufacturing method of discharge tube chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104485282A true CN104485282A (en) | 2015-04-01 |
| CN104485282B CN104485282B (en) | 2017-05-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410797320.4A Active CN104485282B (en) | 2014-12-18 | 2014-12-18 | Manufacturing method of discharge tube chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104485282B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113314409A (en) * | 2021-05-27 | 2021-08-27 | 江苏晟驰微电子有限公司 | Manufacturing process of VBAT end low-voltage protection chip of mobile phone |
| CN117476641A (en) * | 2023-12-28 | 2024-01-30 | 深圳市槟城电子股份有限公司 | High-voltage discharge tube and method for producing the same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3972113A (en) * | 1973-05-14 | 1976-08-03 | Mitsubishi Denki Kabushiki Kaisha | Process of producing semiconductor devices |
| CN2757336Y (en) * | 2004-11-30 | 2006-02-08 | 安徽省祁门县黄山电器有限责任公司 | Commutation diode and chip special for producing commutation diode |
| CN101651102A (en) * | 2009-08-25 | 2010-02-17 | 南通明芯微电子有限公司 | Bidirectional trigger diode chip production method |
| CN201985101U (en) * | 2011-01-28 | 2011-09-21 | 上海芯导电子科技有限公司 | Single-side discharge-tube integrated chip |
| CN102244104A (en) * | 2011-07-07 | 2011-11-16 | 重庆平伟实业股份有限公司 | Flat and lug combined bidirectional diode chip and manufacturing process thereof |
-
2014
- 2014-12-18 CN CN201410797320.4A patent/CN104485282B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3972113A (en) * | 1973-05-14 | 1976-08-03 | Mitsubishi Denki Kabushiki Kaisha | Process of producing semiconductor devices |
| CN2757336Y (en) * | 2004-11-30 | 2006-02-08 | 安徽省祁门县黄山电器有限责任公司 | Commutation diode and chip special for producing commutation diode |
| CN101651102A (en) * | 2009-08-25 | 2010-02-17 | 南通明芯微电子有限公司 | Bidirectional trigger diode chip production method |
| CN201985101U (en) * | 2011-01-28 | 2011-09-21 | 上海芯导电子科技有限公司 | Single-side discharge-tube integrated chip |
| CN102244104A (en) * | 2011-07-07 | 2011-11-16 | 重庆平伟实业股份有限公司 | Flat and lug combined bidirectional diode chip and manufacturing process thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113314409A (en) * | 2021-05-27 | 2021-08-27 | 江苏晟驰微电子有限公司 | Manufacturing process of VBAT end low-voltage protection chip of mobile phone |
| CN117476641A (en) * | 2023-12-28 | 2024-01-30 | 深圳市槟城电子股份有限公司 | High-voltage discharge tube and method for producing the same |
| CN117476641B (en) * | 2023-12-28 | 2024-04-09 | 深圳市槟城电子股份有限公司 | High-voltage discharge tube and method for producing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104485282B (en) | 2017-05-24 |
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Effective date of registration: 20170714 Address after: Tang Luodian town Shanghai city Baoshan District 201900 Lane 64 Lane 2 Patentee after: Jin Baoxing Address before: 215500 Jiangsu city of Suzhou province Changshou City Yushan High-tech Industrial Park No. 21 Sanya Road Patentee before: CHANGSHU JUXIN SEMICONDUCTOR TECHNOLOGY CO., LTD. |
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Effective date of registration: 20180601 Address after: 518116 Shenzhen, Longgang, Guangdong province Longgang Street Baolong community Baolong four road 3 Lan Pu Yuan Industrial Zone 1 Factory A501 Patentee after: Shenzhen Bencent Electronics Co., Ltd. Address before: 201900 No. 64 lane, Tangjia lane, Luo Dian Town, Baoshan District, Shanghai 2 Patentee before: Jin Baoxing |
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Address after: 518116 Shenzhen, Longgang, Guangdong province Longgang Street Baolong community Baolong four road 3 Lan Pu Yuan Industrial Zone 1 Factory A501 Patentee after: Shenzhen Penang Electronics Co.,Ltd. Address before: 518116 Shenzhen, Longgang, Guangdong province Longgang Street Baolong community Baolong four road 3 Lan Pu Yuan Industrial Zone 1 Factory A501 Patentee before: Shenzhen Bencent Electronics Co.,Ltd. |
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