CN112614782B - Manufacturing method of unidirectional negative resistance surge protection chip - Google Patents
Manufacturing method of unidirectional negative resistance surge protection chip Download PDFInfo
- Publication number
- CN112614782B CN112614782B CN202011476918.5A CN202011476918A CN112614782B CN 112614782 B CN112614782 B CN 112614782B CN 202011476918 A CN202011476918 A CN 202011476918A CN 112614782 B CN112614782 B CN 112614782B
- Authority
- CN
- China
- Prior art keywords
- region
- oxide film
- type wafer
- negative resistance
- surge protection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 12
- 239000011574 phosphorus Substances 0.000 claims abstract description 12
- 238000009792 diffusion process Methods 0.000 claims abstract description 11
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052796 boron Inorganic materials 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 238000001259 photo etching Methods 0.000 claims description 9
- 239000007788 liquid Substances 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 6
- 150000001204 N-oxides Chemical class 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 3
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 3
- 238000012858 packaging process Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66121—Multilayer diodes, e.g. PNPN diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thyristors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
A method for manufacturing a unidirectional negative resistance surge protection chip. The invention relates to the field of chip processing, in particular to a manufacturing method of a unidirectional negative resistance surge protection chip. A method for manufacturing a unidirectional negative resistance surge protection chip is provided, which enables a product to have negative resistance characteristics and low forward contact voltage without the need of limiting thickness reduction of a wafer. In operation, the invention comprises a P-type substrate raw silicon wafer; forming N-diffusion regions by lightly phosphorus doping on two sides of the P-type silicon substrate; and (3) carrying out heavy boron doping on the upper N-region to form a P+ region, and doping heavy phosphorus on the lower N-region to form an N++ region, wherein the lower N-region is changed into the N+ region, so that the unidirectional negative resistance surge protection chip is manufactured. The invention avoids the stress caused by the over-thin wafer in the packaging process and improves the reliability of the product.
Description
Technical Field
The invention relates to the field of chip processing, in particular to a manufacturing method of a unidirectional negative resistance surge protection chip.
Background
The surge protection device itself is required to absorb a large surge current so as to protect the subsequent-stage circuit from damage. In the application range of the circuit, the device shows residual voltage after absorbing surge current, the smaller the residual voltage is, the smaller the influence of surge and residual voltage on the later-stage circuit is, and the smaller the influence of the device on the later-stage circuit is, the better the protection is.
The negative resistance characteristic of the device requires that the device has a narrower base width, and the traditional manufacturing process cannot achieve the narrow base region due to the limitations of diffusion process, great difficulty in sheet production operation and the like, so that the negative resistance characteristic is difficult to achieve.
Today, the market competition of semiconductors is more and more vigorous, a first-class testing technology is provided, the quality of products is guaranteed to be a necessary interest of each semiconductor discrete device manufacturer, and therefore, in order to guarantee the use reliability of the semiconductor discrete devices, the research of a high-reliability surge protection product is of great significance.
Disclosure of Invention
The invention aims at the problems and provides a manufacturing method of a unidirectional negative resistance surge protection chip which enables a product to have negative resistance characteristics and low forward contact voltage under the condition that the thickness limit of a wafer sheet is not required to be thinned.
The technical scheme of the invention is as follows: the method comprises the following steps:
s1, initial oxidation: growing a layer of compact oxide film on the surface of the wafer;
S2, selective photoetching: exposing the N-region above the P-type wafer and the N-ring region oxide films on two sides, and protecting other regions by using a photoresist;
s3, removing the N-oxide film: removing the oxide film exposed above and below the wafer;
S4, N-region phosphorus pre-deposition: pre-depositing low-concentration N < - > on the surface of the exposed silicon above and below the wafer;
s5, re-expanding N-region: re-advancing the N-region;
s6, selective photoetching: exposing a part of the oxide film in the N-region above the wafer, and protecting other regions by using a photoresist;
s7, removing the oxide film in the P+ region: removing the oxide film on the exposed N-region part above the wafer;
s8, P+ region diffusion: pre-depositing a layer of concentrated boron on the exposed silicon surface of the N-region by using a liquid boron source;
S9, re-expanding the P+ region: re-advancing the p+ region;
S10, selective photoetching: exposing the surface oxide film of the N-region below the P region above the wafer, and protecting other regions by using a photoresist;
S11, oxide film removal: removing the oxide film exposed from the N-region below the wafer;
s12, N-region phosphorus pre-deposition: pre-depositing a high concentration of n++ on the exposed silicon surface below the wafer;
s13, re-expanding the N++ region: the N++ region is re-pushed, and meanwhile, the N-region is changed into an N+ region under the influence of the concentration of the N++ region, so that the junction depth is further pushed;
S14, metallization: plating a layer of electrode metal on the surface of the wafer, and finishing the processing.
In step S1, the thickness of the oxide film is 20000-30000 angstroms.
In steps S3, S7, and S11, the oxide film is removed using the BOE etchant.
In steps S4 and S12, POCL3 liquid source diffusion is used, respectively.
In operation, the invention comprises a P-type substrate raw silicon wafer; forming N-diffusion regions by lightly phosphorus doping on two sides of the P-type silicon substrate; and (3) carrying out heavy boron doping on the upper N-region to form a P+ region, and doping heavy phosphorus on the lower N-region to form an N++ region, wherein the lower N-region is changed into the N+ region, so that the unidirectional negative resistance surge protection chip is manufactured.
Drawings
Figure 1 is a schematic representation of S1 in the present invention,
Figure 2 is a schematic representation of S2 in the present invention,
Figure 3 is a schematic representation of S3 in the present invention,
Figure 4 is a schematic representation of S4 in the present invention,
Figure 5 is a schematic representation of S5 in the present invention,
Figure 6 is a schematic representation of S6 in the present invention,
Figure 7 is a schematic representation of S7 in the present invention,
Figure 8 is a schematic representation of S8 in the present invention,
Figure 9 is a schematic diagram of S9 in the present invention,
Figure 10 is a schematic representation of S10 in the present invention,
Figure 11 is a schematic diagram of S11 in the present invention,
Figure 12 is a schematic diagram of S12 in the present invention,
Figure 13 is a schematic representation of S13 in the present invention,
Fig. 14 is a schematic diagram of S14 in the present invention.
Detailed Description
The invention, as shown in fig. 1-14, comprises the following steps:
s1, initial oxidation: growing a layer of compact oxide film on the surface of the wafer;
s2, selective photoetching: exposing the N-region above the P-type wafer and the N-ring region oxide films on both sides, and protecting other regions with photoresist (the lower part of the wafer is not coated with photoresist);
s3, removing the N-oxide film: removing the oxide film exposed above and below the wafer;
s4, N-region phosphorus pre-deposition: pre-depositing a low concentration of N-on the exposed silicon surface above and below the wafer using POCL3 liquid source diffusion;
S5, re-expanding N-region: the N-region is re-propelled, and the reverse voltage of the diode is raised;
s6, selective photoetching: exposing a part of the oxide film in the N-region above the wafer, and protecting other regions by using a photoresist;
s7, removing the oxide film in the P+ region: removing the oxide film on the exposed N-region part above the wafer;
s8, P+ region diffusion: pre-depositing a layer of concentrated boron on the exposed silicon surface of the N-region by using a liquid boron source;
s9, re-expanding the P+ region: pushing the P+ region to a certain depth;
S10, selective photoetching: exposing the surface oxide film of the N-region below the P region above the wafer, and protecting other regions by using a photoresist;
S11, oxide film removal: removing the oxide film exposed from the N-region below the wafer;
S12, N-region phosphorus pre-deposition: pre-depositing a high concentration of n++ on the exposed silicon surface below the wafer using POCL3 liquid source diffusion;
S13, re-expanding the N++ region: the N++ region is pushed to a certain depth, and meanwhile, the N-region is changed into an N+ region under the influence of the concentration of the N++ region, so that the junction depth is further pushed;
S14, metallization: plating a layer of electrode metal (TI/NI/AG or NI/Au) on the surface of the wafer, and finishing the processing.
In step S1, the thickness of the oxide film is 20000-30000 angstroms.
In steps S3, S7, and S11, the oxide film is removed using the BOE etchant.
In operation, the invention comprises a P-type substrate raw silicon wafer; forming N-diffusion regions by lightly phosphorus doping on two sides of the P-type silicon substrate; and (3) carrying out heavy boron doping on the upper N-region to form a P+ region, and doping heavy phosphorus on the lower N-region to form an N++ region, wherein the lower N-region is changed into the N+ region, so that the unidirectional negative resistance surge protection chip is manufactured.
Claims (3)
1. The manufacturing method of the unidirectional negative resistance surge protection chip is characterized by comprising the following steps of:
S1, initial oxidation: growing a layer of compact oxide film on the surface of the P-type wafer;
S2, selective photoetching: exposing the oxide film corresponding to the N-region to be formed and the N-ring regions on the two sides above the P-type wafer, and protecting other regions above the P-type wafer by using a photoresist;
S3, removing the N-oxide film: removing the exposed oxide films above and below the P-type wafer;
S4, N-region phosphorus pre-deposition: pre-depositing the exposed silicon surface above and below the P-type wafer to form a low-concentration N-region;
s5, re-expanding N-region: re-advancing the N-region to obtain the N-region and the N-ring region;
s6, selective photoetching: exposing part of the oxide film on the N-region above the P-type wafer, and protecting other regions by using a photoresist;
s7, removing the oxide film in the P+ region: removing the exposed oxide film of the N-region part above the P-type wafer;
s8, P+ region diffusion: pre-depositing a layer of concentrated boron on the exposed silicon surface of the N-region by using a liquid boron source;
S9, re-expanding the P+ region: re-advancing the p+ region;
S10, selective photoetching: exposing the surface oxide film of the N-region below the P-type wafer, and protecting other regions by using a photoresist;
s11, oxide film removal: removing the oxide film exposed from the N-region below the P-type wafer;
s12, N-region phosphorus pre-deposition: pre-depositing a high-concentration N++ region on the exposed silicon surface below the P-type wafer;
S13, re-expanding the N++ region: the N++ region is re-pushed, and meanwhile, the N-region below the P-type wafer is changed into an N+ region under the influence of the concentration of the N++ region, so that the junction depth is further pushed;
S14, metallization: plating a layer of electrode metal on the surface of the P-type wafer, and finishing the processing;
In steps S4 and S12, POCl 3 liquid source diffusion is used.
2. The method of manufacturing a unidirectional negative resistance surge protection chip as claimed in claim 1, wherein in step S1, the thickness of the oxide film is 20000-30000 angstroms.
3. The method of manufacturing a unidirectional negative resistance surge protection chip as claimed in claim 1, wherein in steps S3, S7, and S11, the oxide film is removed by using a BOE etchant.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011476918.5A CN112614782B (en) | 2020-12-15 | 2020-12-15 | Manufacturing method of unidirectional negative resistance surge protection chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011476918.5A CN112614782B (en) | 2020-12-15 | 2020-12-15 | Manufacturing method of unidirectional negative resistance surge protection chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112614782A CN112614782A (en) | 2021-04-06 |
| CN112614782B true CN112614782B (en) | 2024-06-18 |
Family
ID=75234257
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011476918.5A Active CN112614782B (en) | 2020-12-15 | 2020-12-15 | Manufacturing method of unidirectional negative resistance surge protection chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112614782B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109390385A (en) * | 2017-12-05 | 2019-02-26 | 上海长园维安微电子有限公司 | A kind of unidirectional TVS device and preparation method thereof with negative resistance charactertistic |
| CN111223914A (en) * | 2019-07-01 | 2020-06-02 | 上海维安半导体有限公司 | Semiconductor discharge tube with negative resistance characteristic and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105552873B (en) * | 2016-01-05 | 2024-03-29 | 深圳市槟城电子股份有限公司 | Surge protection device |
| CN211654822U (en) * | 2020-05-09 | 2020-10-09 | 捷捷半导体有限公司 | Unidirectional negative resistance electrostatic discharge protection device |
-
2020
- 2020-12-15 CN CN202011476918.5A patent/CN112614782B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109390385A (en) * | 2017-12-05 | 2019-02-26 | 上海长园维安微电子有限公司 | A kind of unidirectional TVS device and preparation method thereof with negative resistance charactertistic |
| CN111223914A (en) * | 2019-07-01 | 2020-06-02 | 上海维安半导体有限公司 | Semiconductor discharge tube with negative resistance characteristic and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112614782A (en) | 2021-04-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108682695B (en) | High-current low-forward voltage drop silicon carbide Schottky diode chip and preparation method thereof | |
| JPH0222869A (en) | Symmetrical blocking high breakdown voltage semiconductor device and its manufacture | |
| CN106601826B (en) | Fast recovery diode and manufacturing method thereof | |
| US20150221523A1 (en) | Arrangement and method for manufacturing the same | |
| US9209132B2 (en) | Semiconductor component and method of manufacture | |
| CN113644027A (en) | Groove power device integrated with inductor and manufacturing method thereof | |
| US8546918B2 (en) | Semiconductor device | |
| CN106169508B (en) | Bidirectional ultra-low capacitance transient voltage suppressor and manufacturing method thereof | |
| CN111223919A (en) | TVS (transient voltage suppressor) etched by deep groove and filled with high-concentration polycrystalline silicon and manufacturing method thereof | |
| CN112614782B (en) | Manufacturing method of unidirectional negative resistance surge protection chip | |
| CN210866178U (en) | TVS device of integrated unidirectional low-capacity GPP process | |
| CN116487385B (en) | TVS device and manufacturing method thereof | |
| CN212434624U (en) | High-power transient voltage suppressor | |
| CN111370497A (en) | Semiconductor mesa diode chip and manufacturing method thereof | |
| CN111430468B (en) | Dual-core isolation structure of dual-cell packaged Schottky diode chip and manufacturing method | |
| CN107527907B (en) | Transient voltage suppressor and method of manufacturing the same | |
| CN111430305B (en) | Method for manufacturing electrostatic discharge protection device and electrostatic discharge protection device | |
| KR101006768B1 (en) | Structure of a tvs diode array and its fabrication method | |
| CN211605156U (en) | Electrostatic discharge protection device | |
| CN111312709B (en) | High-power transient voltage suppressor and manufacturing method thereof | |
| CN212085008U (en) | Semiconductor discharge tube with negative resistance characteristic | |
| JP6594296B2 (en) | Zener diode with polysilicon layer with improved reverse surge capability and reduced leakage current | |
| CN107154448B (en) | The preparation method and photodiode of photodiode | |
| CN111223914A (en) | Semiconductor discharge tube with negative resistance characteristic and manufacturing method thereof | |
| CN212571004U (en) | TVS protection device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |