CN112614782B - Manufacturing method of unidirectional negative resistance surge protection chip - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 14
- 239000011574 phosphorus Substances 0.000 claims abstract description 14
- 238000009792 diffusion process Methods 0.000 claims abstract description 11
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052796 boron Inorganic materials 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 238000000206 photolithography Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 8
- 239000007788 liquid Substances 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 6
- 150000001204 N-oxides Chemical class 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 6
- 238000012858 packaging process Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 24
- 238000010586 diagram Methods 0.000 description 14
- 239000004065 semiconductor Substances 0.000 description 3
- 101001121408 Homo sapiens L-amino-acid oxidase Proteins 0.000 description 1
- 101000827703 Homo sapiens Polyphosphoinositide phosphatase Proteins 0.000 description 1
- 102100026388 L-amino-acid oxidase Human genes 0.000 description 1
- 102100023591 Polyphosphoinositide phosphatase Human genes 0.000 description 1
- 101100233916 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) KAR5 gene Proteins 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
- H10D8/01—Manufacture or treatment
- H10D8/041—Manufacture or treatment of multilayer diodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
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- Semiconductor Integrated Circuits (AREA)
Abstract
一种单向负阻浪涌防护芯片的制造方法。本发明涉及芯片加工领域，尤其涉及一种单向负阻浪涌防护芯片的制造方法。提供了一种在无需晶片片厚极限减薄的情况下，使产品具有负阻特性及低的正向接触电压的单向负阻浪涌防护芯片的制造方法。本发明在工作中，包含P型衬底原硅片；通过在P型硅衬底的两侧进行淡磷掺杂形成N‑扩散区；在上侧N‑区进行浓硼掺杂形成P+区，在下侧N‑区掺杂浓磷，形成N++区，同时下层N‑区改变为N+区，从而制得单向负阻浪涌防护芯片。本发明避免了封装过程中晶片过薄而造成的应力，提升产品可靠性。
A method for manufacturing a unidirectional negative resistance surge protection chip. The present invention relates to the field of chip processing, and in particular to a method for manufacturing a unidirectional negative resistance surge protection chip. A method for manufacturing a unidirectional negative resistance surge protection chip that enables the product to have negative resistance characteristics and low forward contact voltage without the need for extreme thinning of the wafer thickness is provided. During operation, the present invention comprises a P-type substrate original silicon wafer; an N-diffusion region is formed by light phosphorus doping on both sides of the P-type silicon substrate; a P+ region is formed by concentrated boron doping in the upper N-region, and a N++ region is formed by doping the lower N-region with concentrated phosphorus, while the lower N-region is changed to an N+ region, thereby obtaining a unidirectional negative resistance surge protection chip. The present invention avoids the stress caused by the wafer being too thin during the packaging process, and improves product reliability.
Description
技术领域Technical Field
本发明涉及芯片加工领域，尤其涉及一种单向负阻浪涌防护芯片的制造方法。The invention relates to the field of chip processing, and in particular to a method for manufacturing a unidirectional negative resistance surge protection chip.
背景技术Background technique
浪涌防护器件要求其本身可以吸收大的浪涌电流从而保护后级电路不受损坏的作用。在电路所处应用范围内，器件在吸收浪涌电流后展现出残压，残压越小，后级电路受到浪涌及残压影响越小，其对后级电路影响越小保护越好。Surge protection devices are required to absorb large surge currents to protect the subsequent circuits from damage. Within the application range of the circuit, the device will show residual voltage after absorbing the surge current. The smaller the residual voltage, the less impact the subsequent circuit will be affected by the surge and residual voltage. The smaller the impact on the subsequent circuit, the better the protection.
器件的负阻特性要求器件具有较窄的基区宽度，传统的制造工艺由于扩散工艺及薄片生产操作难度大等限制，无法将基区做到很窄，很难实现负阻特性。The negative resistance characteristic of the device requires that the device has a narrow base width. Due to limitations such as the diffusion process and the difficulty of thin film production operations, the traditional manufacturing process cannot make the base very narrow, making it difficult to achieve negative resistance characteristics.
在半导体市场竞争越演越烈的今天，拥有一流的测试技术，保证产品质量是每个半导体分立器件制造厂必备的利器，因此为了保证半导体分立器件使用的可靠性，研究一种高可靠性的浪涌防护产品具有很重要的意义。As competition in the semiconductor market becomes increasingly fierce, having first-class testing technology to ensure product quality is an essential tool for every semiconductor discrete device manufacturer. Therefore, in order to ensure the reliability of the use of semiconductor discrete devices, it is of great significance to study a high-reliability surge protection product.
发明内容Summary of the invention
本发明针对以上问题，提供了一种在无需晶片片厚极限减薄的情况下，使产品具有负阻特性及低的正向接触电压的单向负阻浪涌防护芯片的制造方法。In view of the above problems, the present invention provides a method for manufacturing a unidirectional negative resistance surge protection chip which has negative resistance characteristics and low forward contact voltage without reducing the thickness of the wafer to an extreme extent.
本发明的技术方案是：包括以下步骤：The technical solution of the present invention is: comprising the following steps:
S1、初始氧化：在晶片表面生长一层致密氧化膜；S1, initial oxidation: growing a dense oxide film on the surface of the wafer;
S2、选择性光刻：将 P型晶片上方的N-区及两侧的N-环区氧化膜暴露出来，其它区域用光阻剂保护；S2, Selective photolithography: Expose the N-region above the P-type wafer and the N-ring oxide film on both sides, and protect other areas with photoresist;
S3、N-氧化膜去除：将晶片上方及下方暴露出来的氧化膜去除；S3, N-oxide film removal: remove the oxide film exposed above and below the wafer;
S4、N-区磷预沉积：在晶片上方及下方暴露出来硅表面预沉积低浓度的N-；S4, N-area phosphorus pre-deposition: pre-deposit low concentration N- on the exposed silicon surface above and below the wafer;
S5、N-区再扩：将N-区域再推进；S5, N-area expansion: further advance the N-area;
S6、选择性光刻：将晶片上方N-区部分氧化膜暴露出来，其他区域用光阻剂保护；S6, Selective photolithography: expose part of the oxide film in the N-region above the wafer, and protect the other areas with photoresist;
S7、P+区氧化膜去除：将晶片上方N-区部分暴露出来上的氧化膜去除；S7, P+ region oxide film removal: remove the oxide film on the exposed N- region above the wafer;
S8、P+区扩散：使用液态硼源在N-区暴露的硅表面预沉积一层浓硼；S8, P+ region diffusion: Use a liquid boron source to pre-deposit a layer of concentrated boron on the silicon surface exposed in the N- region;
S9、P+区再扩：将P+区域再推进；S9, P+ area expansion: further advance the P+ area;
S10、选择性光刻：将晶片上方P区下方N-区表面氧化膜暴露出来，其他区域用光阻剂保护；S10, Selective photolithography: Expose the surface oxide film of the N-region below the P region above the wafer, and protect other areas with photoresist;
S11、氧化膜去除：将晶片下方N-区暴露出来的氧化膜去除；S11, oxide film removal: remove the oxide film exposed in the N-region below the wafer;
S12、N-区磷预沉积：在晶片下方暴露出来硅表面预沉积高浓度的N++；S12, N-region phosphorus pre-deposition: pre-deposit high concentration of N++ on the silicon surface exposed below the wafer;
S13、N++区再扩：将N++区域再推进，同时N-区受到N++区的浓度影响变成N+区，结深进一步推进；S13, N++ area expansion: the N++ area is further advanced, and at the same time, the N- area is affected by the concentration of the N++ area and becomes the N+ area, and the junction depth is further advanced;
S14、金属化：在晶片表面镀一层电极金属，加工完毕。S14, Metallization: A layer of electrode metal is plated on the surface of the chip and the processing is completed.
步骤S1中，氧化膜的厚度在20000-30000埃。In step S1, the thickness of the oxide film is 20,000-30,000 angstroms.
步骤S3、S7、S11中，分别使用BOE腐蚀液去除氧化膜。In steps S3, S7 and S11, BOE etching solution is used to remove the oxide film.
步骤S4、S12中，分别使用POCL3液态源扩散。In steps S4 and S12, POCL3 liquid source is used for diffusion respectively.
本发明在工作中，包含P型衬底原硅片；通过在P型硅衬底的两侧进行淡磷掺杂形成N-扩散区；在上侧N-区进行浓硼掺杂形成P+区，在下侧N-区掺杂浓磷，形成N++区，同时下层N-区改变为N+区，从而制得单向负阻浪涌防护芯片。The present invention comprises a P-type substrate original silicon wafer during operation; N-diffusion regions are formed by light phosphorus doping on both sides of the P-type silicon substrate; concentrated boron doping is performed on the upper N-region to form a P+ region, and concentrated phosphorus is doped on the lower N-region to form an N++ region, while the lower N-region is changed into an N+ region, thereby obtaining a unidirectional negative resistance surge protection chip.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
图1是本发明中S1的示意图，FIG1 is a schematic diagram of S1 in the present invention,
图2是本发明中S2的示意图，FIG. 2 is a schematic diagram of S2 in the present invention,
图3是本发明中S3的示意图，FIG3 is a schematic diagram of S3 in the present invention,
图4是本发明中S4的示意图，FIG4 is a schematic diagram of S4 in the present invention,
图5是本发明中S5的示意图，FIG5 is a schematic diagram of S5 in the present invention,
图6是本发明中S6的示意图，FIG6 is a schematic diagram of S6 in the present invention,
图7是本发明中S7的示意图，FIG. 7 is a schematic diagram of S7 in the present invention,
图8是本发明中S8的示意图，FIG8 is a schematic diagram of S8 in the present invention,
图9是本发明中S9的示意图，FIG9 is a schematic diagram of S9 in the present invention,
图10是本发明中S10的示意图，FIG10 is a schematic diagram of S10 in the present invention,
图11是本发明中S11的示意图，FIG11 is a schematic diagram of S11 in the present invention,
图12是本发明中S12的示意图，FIG12 is a schematic diagram of S12 in the present invention,
图13是本发明中S13的示意图，FIG13 is a schematic diagram of S13 in the present invention,
图14是本发明中S14的示意图。FIG. 14 is a schematic diagram of S14 in the present invention.
具体实施方式Detailed ways
本发明如图1-14所示，包括以下步骤：The present invention, as shown in Figures 1-14, comprises the following steps:
S1、初始氧化：在晶片表面生长一层致密氧化膜；S1, initial oxidation: growing a dense oxide film on the surface of the wafer;
S2、选择性光刻：将 P型晶片上方的N-区及两侧的N-环区氧化膜暴露出来，其它区域用光阻剂保护（晶片下方不涂光阻剂）；S2, Selective photolithography: Expose the N-region above the P-type wafer and the N-ring oxide film on both sides, and protect other areas with photoresist (no photoresist is applied under the wafer);
S3、N-氧化膜去除：将晶片上方及下方暴露出来的氧化膜去除；S3, N-oxide film removal: remove the oxide film exposed above and below the wafer;
S4、N-区磷预沉积：使用POCL3液态源扩散，在晶片上方及下方暴露出来硅表面预沉积低浓度的N-；S4, N-area phosphorus pre-deposition: Use POCL3 liquid source diffusion to pre-deposit low concentration N- on the exposed silicon surface above and below the wafer;
S5、N-区再扩：将N-区域再推进，提升二极管反向电压；S5, N-region expansion: further push the N-region to increase the reverse voltage of the diode;
S6、选择性光刻：将晶片上方N-区部分氧化膜暴露出来，其他区域用光阻剂保护；S6, Selective photolithography: expose part of the oxide film in the N-region above the wafer, and protect the other areas with photoresist;
S7、P+区氧化膜去除：将晶片上方N-区部分暴露出来上的氧化膜去除；S7, P+ region oxide film removal: remove the oxide film on the exposed N- region above the wafer;
S8、P+区扩散：使用液态硼源在N-区暴露的硅表面预沉积一层浓硼；S8, P+ region diffusion: Use a liquid boron source to pre-deposit a layer of concentrated boron on the silicon surface exposed in the N- region;
S9、P+区再扩：将P+区域再推进一定深度；S9, P+ area expansion: push the P+ area further to a certain depth;
S10、选择性光刻：将晶片上方P区下方N-区表面氧化膜暴露出来，其他区域用光阻剂保护；S10, Selective photolithography: Expose the surface oxide film of the N-region below the P region above the wafer, and protect other areas with photoresist;
S11、氧化膜去除：将晶片下方N-区暴露出来的氧化膜去除；S11, oxide film removal: remove the oxide film exposed in the N-region below the wafer;
S12、N-区磷预沉积：使用POCL3液态源扩散，在晶片下方暴露出来硅表面预沉积高浓度的N++；S12, N-area phosphorus pre-deposition: Use POCL3 liquid source diffusion to pre-deposit high concentration N++ on the silicon surface exposed below the wafer;
S13、N++区再扩：将N++区域再推进一定深度，同时N-区受到N++区的浓度影响变成N+区，结深进一步推进；S13, N++ area further expansion: the N++ area is pushed forward to a certain depth, and at the same time, the N- area is affected by the concentration of the N++ area and becomes the N+ area, and the junction depth is further advanced;
S14、金属化：在晶片表面镀一层电极金属（TI/NI/AG或者NI/Au），加工完毕。S14, Metallization: A layer of electrode metal (TI/NI/AG or NI/Au) is plated on the surface of the chip, and the processing is completed.
步骤S1中，氧化膜的厚度在20000-30000埃。In step S1, the thickness of the oxide film is 20,000-30,000 angstroms.
步骤S3、S7、S11中，分别使用BOE腐蚀液去除氧化膜。In steps S3, S7 and S11, BOE etching solution is used to remove the oxide film.
本发明在工作中，包含P型衬底原硅片；通过在P型硅衬底的两侧进行淡磷掺杂形成N-扩散区；在上侧N-区进行浓硼掺杂形成P+区，在下侧N-区掺杂浓磷，形成N++区，同时下层N-区改变为N+区，从而制得单向负阻浪涌防护芯片。The present invention comprises a P-type substrate original silicon wafer during operation; N-diffusion regions are formed by light phosphorus doping on both sides of the P-type silicon substrate; concentrated boron doping is performed on the upper N-region to form a P+ region, and concentrated phosphorus is doped on the lower N-region to form an N++ region, while the lower N-region is changed into an N+ region, thereby obtaining a unidirectional negative resistance surge protection chip.
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| CN111223914A (en) * | 2019-07-01 | 2020-06-02 | 上海维安半导体有限公司 | Semiconductor discharge tube with negative resistance characteristic and manufacturing method thereof |
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| CN111223914A (en) * | 2019-07-01 | 2020-06-02 | 上海维安半导体有限公司 | Semiconductor discharge tube with negative resistance characteristic and manufacturing method thereof |
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