CN117877981B - Semiconductor device and preparation method thereof - Google Patents
Semiconductor device and preparation method thereof Download PDFInfo
- Publication number
- CN117877981B CN117877981B CN202410275643.0A CN202410275643A CN117877981B CN 117877981 B CN117877981 B CN 117877981B CN 202410275643 A CN202410275643 A CN 202410275643A CN 117877981 B CN117877981 B CN 117877981B
- Authority
- CN
- China
- Prior art keywords
- layer
- conductive
- hole
- photoresist
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 238000002360 preparation method Methods 0.000 title abstract description 18
- 239000010410 layer Substances 0.000 claims abstract description 472
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 136
- 238000005530 etching Methods 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 238000005468 ion implantation Methods 0.000 claims abstract description 30
- 239000002346 layers by function Substances 0.000 claims abstract description 14
- 150000002500 ions Chemical class 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 41
- 238000004519 manufacturing process Methods 0.000 claims description 20
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 229910021480 group 4 element Inorganic materials 0.000 claims description 5
- 229910021478 group 5 element Inorganic materials 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 230000000694 effects Effects 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 238000004026 adhesive bonding Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a semiconductor device and a preparation method thereof. The preparation method of the semiconductor device comprises the following steps: preparing a semiconductor functional layer, wherein the semiconductor functional layer at least comprises a substrate and an epitaxial layer, and a first insulating layer and a first conducting layer are formed on the surface of the epitaxial layer far away from the substrate; forming a photoresist layer on one side of the first conductive layer away from the epitaxial layer; ion implantation is carried out on the photoresist layer and the bottom of the groove so as to form doped ions for hardening the photoresist layer in the photoresist layer; etching the first conductive layer and the first insulating layer by taking the photoresist layer as a mask plate to form a first through hole, wherein the first through hole exposes the epitaxial layer; and etching the epitaxial layer by taking the photoresist layer as a mask plate to form a second through hole. The technical scheme provided by the embodiment of the invention reduces the use quantity of the photoresist layers, reduces the preparation cost, improves the etching precision of the first through hole and the second through hole, and improves the yield of the semiconductor device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
In the existing high electron mobility transistor (High electron mobility transistor, HEMT), in the process of preparing the first through hole in the insulating layer, which is far away from the surface of the substrate, and the second through hole in the epitaxial layer, the number of photoresist layers is large, so that the preparation cost is very high, the etching precision of the first through hole and the second through hole is not high, and the yield of the semiconductor device is further affected.
Disclosure of Invention
The invention provides a semiconductor device and a preparation method thereof, which are used for reducing the use quantity of photoresist layers, lowering the preparation cost, improving the etching precision of a first through hole and a second through hole and improving the yield of the semiconductor device.
According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising:
Preparing a semiconductor functional layer, wherein the semiconductor functional layer at least comprises a substrate and an epitaxial layer, a first insulating layer and a first conducting layer are formed on the surface, far away from the substrate, of the epitaxial layer, a first conducting structure is arranged in the first insulating layer, the first conducting layer is located on the surface, far away from the epitaxial layer, of the first insulating layer, and the first conducting layer is connected with the first conducting structure;
Forming a photoresist layer on one side of the first conductive layer far away from the epitaxial layer, wherein the photoresist layer is provided with a groove, the groove penetrates through the photoresist layer, and the orthographic projection of the groove on the substrate and the orthographic projection of the first conductive structure on the substrate are not overlapped;
ion implantation is carried out on the photoresist layer and the bottoms of the grooves so as to form doped ions used for hardening the photoresist layer in the photoresist layer;
Etching the first conductive layer and the first insulating layer by taking the photoresist layer as a mask plate to form a first through hole, wherein the first through hole exposes the epitaxial layer;
and etching the epitaxial layer by taking the photoresist layer as a mask plate to form a second through hole, wherein the second through hole penetrates through the epitaxial layer, and the second through hole is communicated with the first through hole.
Optionally, etching the epitaxial layer by using the photoresist layer as a mask, so as to form a second via hole, further including:
and carrying out ion implantation on the photoresist layer and the epitaxial layer for hardening the photoresist layer.
Optionally, etching the epitaxial layer by using the photoresist layer as a mask, so as to form a second via, and then further including:
Removing the photoresist layer;
Forming a second conductive structure on the surface of the first conductive layer far away from the first insulating layer, wherein the second conductive structure is connected with the first conductive structure through the first conductive layer, and the orthographic projection of the second conductive structure on the substrate is not overlapped with the orthographic projection of the first through hole and the second through hole on the substrate;
and forming a second conductive layer, wherein the second conductive layer covers the second conductive structure, the side wall of the first through hole, the side wall of the second through hole and the bottom surface of the second through hole.
Optionally, preparing the semiconductor functional layer includes:
Providing a substrate;
forming an epitaxial layer on one side of the substrate;
Forming an ohmic contact layer on the surface of the epitaxial layer far away from the substrate;
Forming a first sub-insulating layer on the surface of the ohmic contact layer far away from the epitaxial layer;
Forming at least one first conductive via in the first sub-insulating layer, wherein the first conductive via is connected with the ohmic contact layer;
Forming a third conductive layer on the surface of the first conductive through hole far away from the ohmic contact layer;
forming a second sub-insulating layer on the surface of the third conductive layer far away from the first conductive through hole;
forming at least one second conductive via within the second sub-insulating layer, wherein the second conductive via is connected to the third conductive layer;
And forming the first conductive layer on the surface of the second conductive through hole far away from the third conductive layer.
Optionally, forming a second conductive structure on a surface of the first conductive layer remote from the first insulating layer includes:
forming a fourth conductive layer on the surface of the first conductive layer far away from the first insulating layer, wherein the fourth conductive layer is connected with the first conductive layer;
Forming a second insulating layer on the surface of the fourth conductive layer far away from the first conductive layer;
Forming at least one third conductive via in the second insulating layer, wherein the third conductive via is connected to the fourth conductive layer;
And forming a second conductive layer on the surface, far away from the fourth conductive layer, of the second insulating layer, wherein the second conductive layer is in contact with the third conductive through hole, and the fourth conductive layer and the third conductive through hole form the second conductive structure.
Optionally, the elements for performing ion implantation on the photoresist layer and the bottom of the groove include at least one of a group iv element, a group v element, and a group iii element.
Optionally, the elements for ion implantation of the photoresist layer and the bottom of the groove comprise silicon elements and/or germanium elements in the IV main group elements.
Optionally, the elements for ion implantation of the photoresist layer and the bottom of the groove include nitrogen element and/or phosphorus element in the V main group element.
Optionally, the elements for ion implantation of the photoresist layer and the bottom of the groove include boron element in the group III element.
According to another aspect of the present invention, there is provided a semiconductor device manufactured by the manufacturing method of the semiconductor device as described in any of the above embodiments.
According to the technical scheme provided by the embodiment of the invention, the same photoresist layer is used in the process of preparing the first through hole in the first insulating layer and the second through hole in the epitaxial layer, which are far away from the surface of the substrate, and correspondingly, the processes of gluing and removing the photoresist are needed once, so that the preparation process is simplified, and the preparation cost is reduced. And the photoresist layer is used as a mask plate to etch the first conductive layer and the first insulating layer, so that before the first through hole is formed, ion implantation is carried out on the bottoms of the photoresist layer and the grooves to form doping ions for hardening the photoresist layer in the photoresist layer, the hardness of the photoresist layer is increased, the transverse dimension of the photoresist layer is reduced in the etching process, the metal layer (such as the third conductive layer) is prevented from being damaged in the etching process, the etching precision of the first through hole and the second through hole is improved, and the subsequent short circuit between the conductive layer prepared by the first through hole and the second through hole and the third conductive layer is prevented, so that the yield of the semiconductor device is improved; in the second aspect, the photoresist layer is used as a mask plate, the first conductive layer and the first insulating layer are etched, before the first through hole is formed, ion implantation is carried out on the bottoms of the photoresist layer and the grooves, and the surface of the first insulating layer breaks the original combination among atoms under the effect of implanted ions, so that the combination becomes loose, the etching speed is increased, and the use amount of the photoresist is reduced; in the third aspect, during the etching process, the lateral dimension of the photoresist layer is reduced to be negligible, the design dimension of the dicing streets can be reduced, and the total number of chips in the wafer is increased, wherein a wafer is diced at the dicing streets, so that the semiconductor device in the embodiment of the invention can be obtained.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flow chart of a method for manufacturing a semiconductor device provided in the prior art;
FIGS. 2-7 are flowcharts corresponding to the steps of FIG. 1;
Fig. 8 is a method for manufacturing a semiconductor device according to an embodiment of the present invention;
FIGS. 9-13 are flowcharts corresponding to the steps of FIG. 8;
fig. 14 is a flowchart included before S240, S240 and after S240 in fig. 8;
fig. 15 is a schematic structural diagram corresponding to S240a in fig. 14;
Fig. 16 is a schematic structural diagram corresponding to S240c and S240d in fig. 14;
FIG. 17 is a schematic diagram of the process involved in S200 in FIG. 8;
Fig. 18 is a schematic flow chart included in S240c in fig. 14.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or means is not necessarily limited to those steps or means that are expressly listed or inherent to such process, method, article, or apparatus.
As described in the foregoing background art, in the existing semiconductor device, the number of photoresist layers used is large in the process of preparing the first through hole in the insulating layer and the second through hole in the epitaxial layer away from the surface of the substrate, so that the preparation cost is high, and the etching precision of the first through hole and the second through hole is not high, thereby affecting the yield of the semiconductor device. As shown in fig. 1 and fig. 2 to 7, the conventional method for manufacturing a semiconductor device includes the steps of: s100, preparing a semiconductor functional layer, wherein the semiconductor functional layer at least comprises a substrate and an epitaxial layer, a first insulating layer and a first conducting layer are formed on the surface, far away from the substrate, of the epitaxial layer, a first conducting structure is arranged in the first insulating layer, the first conducting layer is located on the surface, far away from the epitaxial layer, of the first insulating layer, and the first conducting layer is connected with the first conducting structure. S101, forming a first photoresist layer on one side, far away from the epitaxial layer, of the first conductive layer, wherein the first photoresist layer is provided with a groove, the groove penetrates through the photoresist layer, and orthographic projection of the groove on the substrate and orthographic projection of the first conductive structure on the substrate are not overlapped. S102, etching the first conductive layer and the first insulating layer by taking the first photoresist layer as a mask plate to form a first through hole, wherein the first through hole exposes the epitaxial layer. And S103, removing the first photoresist layer, forming a second photoresist layer on one side of the first conductive layer away from the epitaxial layer, and etching the epitaxial layer by taking the second photoresist layer as a mask plate to form a second through hole, wherein the second through hole penetrates through the epitaxial layer, and the second through hole is communicated with the first through hole. S104, forming a second conductive structure and a second conductive layer, wherein the second conductive structure is connected with the first conductive structure, and the second conductive layer is connected with the second conductive structure. Wherein reference numerals in fig. 2-7 are as follows: 100-substrate, 101-epitaxial layer, 102-first insulating layer, 103-first conductive structure, 104-first conductive layer, 105-first photoresist layer, T1-first via, 106-second photoresist layer, T2-second via, 107-second conductive structure, 108-second conductive layer, 1031-ohmic contact layer, 1032-first conductive via, 1033-third conductive layer, 1034-second conductive via, 1071-fourth conductive layer, 1072-third conductive via.
The first conductive structure 103 includes an ohmic contact layer 1031, a first conductive via 1032, a third conductive layer 1033, and a second conductive via 1034. The second conductive structure 107 includes a fourth conductive layer 1071 and a third conductive via 1072.
In the method for manufacturing a semiconductor device provided in the prior art, the first photoresist layer 105 is required to be used in the process of manufacturing the first through hole T1, the second photoresist layer 106 is required to be used in the process of manufacturing the second through hole T2, and correspondingly, the processes of photoresist coating, etching and photoresist removing are required to be performed twice, so that the process is complex and the cost is high. And because the photoresist layer is softer, the pattern of the photoresist layer is easy to incline during etching, and the metal layer (such as the third conductive layer 1033) is easy to be damaged, so that the etching precision for preparing the first through hole T1 and the second through hole T2 is not high, and the second conductive layer 108 is easy to be in short circuit with the third conductive layer 1033, thereby influencing the yield of the semiconductor device.
Aiming at the technical problems, the embodiment of the invention provides the following technical scheme:
As shown in fig. 8, fig. 8 is a method for manufacturing a semiconductor device according to an embodiment of the present invention, the method for manufacturing a semiconductor device includes the steps of:
S200, preparing a semiconductor functional layer.
As shown in fig. 9, a semiconductor functional layer was prepared. The semiconductor functional layer at least comprises a substrate 200 and an epitaxial layer 201, a first insulating layer 211 and a first conductive layer 208 are formed on the surface, far away from the substrate 200, of the epitaxial layer 201, a first conductive structure 210 is arranged in the first insulating layer 211, the first conductive layer 208 is located on the surface, far away from the epitaxial layer 201, of the first insulating layer 211, and the first conductive layer 208 is connected with the first conductive structure 210 and used for leading out an electric signal of the epitaxial layer 201.
Wherein the first insulating layer 211 includes a first sub-insulating layer 203 and a second sub-insulating layer 206. The first conductive structure 210 includes an ohmic contact layer 202, a first conductive via 204, a third conductive layer 205, and a second conductive via 207. The first conductive layer 208 is used to make a wiring layer so that the second conductive via 207 can be interconnected with conductive layers of other film layers.
And S210, forming a photoresist layer on one side of the first conductive layer away from the epitaxial layer.
As shown in fig. 10, a photoresist layer 209 is formed on a side of the first conductive layer 208 away from the epitaxial layer 201, where the photoresist layer 209 is provided with a groove, and the groove penetrates through the photoresist layer 209, and an orthographic projection of the groove on the substrate 200 and an orthographic projection of the first conductive structure 210 on the substrate 200 do not overlap.
S220, performing ion implantation on the photoresist layer and the bottoms of the grooves to form doped ions for hardening the photoresist layer in the photoresist layer.
As shown in fig. 11, ion implantation is performed on the photoresist layer 209 and the bottom of the recess to form dopant ions within the photoresist layer 209 for hardening the photoresist layer 209, increasing the hardness of the photoresist layer 209, and reducing the lateral dimension of the photoresist layer 209 during etching is negligible. And the photoresist layer 209 is used as a mask plate to etch the first conductive layer 208 and the first insulating layer 211, before the first through hole T01 is formed, ion implantation is performed on the bottoms of the photoresist layer 209 and the grooves, and the surface of the first insulating layer 211 breaks the combination between the original atoms under the effect of the implanted ions, so that the combination becomes loose, the etching speed becomes high, and the use amount of the photoresist is reduced.
And S230, etching the first conductive layer and the first insulating layer by taking the photoresist layer as a mask plate to form a first through hole.
As shown in fig. 12, the photoresist layer 209 is used as a mask to etch the first conductive layer 208 and the first insulating layer 211 to form a first via T01, where the first via T01 exposes the epitaxial layer 201.
And S240, etching the epitaxial layer by taking the photoresist layer as a mask plate to form a second through hole.
As shown in fig. 13, the photoresist layer 209 is used as a mask to etch the epitaxial layer 201 to form a second through hole T02, where the second through hole T02 penetrates through the epitaxial layer 201, and the second through hole T02 is communicated with the first through hole T01.
The epitaxial layer 201 includes a channel layer and a barrier layer, and a large concentration of two-dimensional electron gas is present near the interface of the channel layer and the barrier layer for improving device performance. A doped group iii-v semiconductor layer is formed on the side of epitaxial layer 201 remote from substrate 200. The doped III-V semiconductor layer is used for exhausting two-dimensional electron gas on the surface of the lower barrier layer under the control of the grid electrode, and the semiconductor device can be turned off under low voltage. The channel layer includes one or more of GaN, alGaN, and InGaN, preferably GaN. The doped III-V semiconductor layer comprises p-type doped AlN or GaN, preferably p-type doped GaN. The barrier layer includes AlGaN.
According to the technical scheme provided by the embodiment of the invention, the same photoresist layer 209 is used in the process of preparing the first through hole T01 in the first insulating layer 211 of the epitaxial layer 201 far away from the surface of the substrate 200 and the second through hole T02 in the epitaxial layer 201, and correspondingly, the processes of gluing and removing the photoresist are needed once, so that the preparation process is simplified, and the preparation cost is reduced. And the photoresist layer 209 is used as a mask to etch the first conductive layer 208 and the first insulating layer 211, before forming the first through hole T01, ion implantation is performed on the bottoms of the photoresist layer 209 and the grooves to form doped ions for hardening the photoresist layer 209 in the photoresist layer 209, so that the hardness of the photoresist layer 209 is increased, the lateral dimension of the photoresist layer 209 is reduced in a negligible manner in the etching process, the metal layer (such as the third conductive layer 205) is prevented from being damaged in the etching process in the first aspect, the etching precision of the first through hole T01 and the second through hole T02 is improved, and the subsequent short circuit between the conductive layers prepared in the first through hole T01 and the second through hole T02 and the third conductive layer 205 is prevented, so that the yield of the semiconductor device is improved; in the second aspect, before the photoresist layer 209 is used as a mask to etch the first conductive layer 208 and the first insulating layer 211 to form the first through hole T01, ion implantation is performed on the bottoms of the photoresist layer 209 and the grooves, and the surface of the first insulating layer 211 breaks the original combination between atoms under the effect of the implanted ions, so that the combination becomes loose, the etching speed becomes fast, and the use amount of the photoresist is reduced; in the third aspect, during etching, the lateral dimension of the photoresist layer 209 is reduced to a negligible extent, so that the design dimension of the scribe line can be reduced, and the total number of chips in the wafer can be increased, wherein a wafer is diced at the scribe line, so that the semiconductor device in the embodiment of the present invention can be obtained.
Optionally, on the basis of the above technical solution, as shown in fig. 14, fig. 14 is a flowchart including S240, S240 and S240 in fig. 8, and before S240 etching the epitaxial layer with the photoresist layer as a mask, the method further includes:
And S240a, performing ion implantation on the photoresist layer and the epitaxial layer for hardening the photoresist layer.
As shown in fig. 15, ion implantation is performed on the photoresist layer 209 and the epitaxial layer 201 for hardening the photoresist layer 209.
Specifically, before the photoresist layer 209 is used as a mask, the photoresist layer 209 is etched to form the second through hole T02, and before the photoresist layer 209 and the epitaxial layer 201 are subjected to ion implantation to harden the photoresist layer 209, the hardness of the photoresist layer 209 is further increased, in the etching process, the lateral dimension of the photoresist layer 209 is reduced to a small extent, the metal layer (such as the third conductive layer 205) is prevented from being damaged in the etching process in the first aspect, the etching precision of the first through hole T01 and the second through hole T02 is improved, and the subsequent short circuit between the conductive layers prepared in the first through hole T01 and the second through hole T02 and the third conductive layer 205 is prevented, so that the yield of the semiconductor device is improved; in the second aspect, before the photoresist layer 209 is used as a mask to etch the epitaxial layer 201 to form the second through hole T02, ion implantation is performed on the photoresist layer 209 and the epitaxial layer 201, and the surface of the epitaxial layer 201 breaks the original atomic bonding under the effect of the implanted ions, so that the etching speed is increased, and the use amount of the photoresist is reduced; in the third aspect, during etching, the lateral dimension L of the photoresist layer 209 may be reduced to a negligible extent, so that the design dimension of the scribe line may be reduced, and the total number of chips in the wafer may be increased, where a wafer is diced at the scribe line, thereby obtaining the semiconductor device in the embodiment of the present invention.
Optionally, on the basis of the above technical solution, as shown in fig. 14, S240 uses the photoresist layer as a mask to etch the epitaxial layer, so as to form the second via, and then further includes:
S240b, removing the photoresist layer.
As shown in fig. 13, the photoresist layer 209 is removed.
And S240c, forming a second conductive structure on the surface of the first conductive layer far away from the first insulating layer.
As shown in fig. 16, a second conductive structure 215 is formed on a surface of the first conductive layer 208 away from the first insulating layer 211, wherein the second conductive structure 215 is connected to the first conductive structure 210 through the first conductive layer 208, and an orthographic projection of the second conductive structure 215 on the substrate 200 and an orthographic projection of the first through hole T01 and the second through hole T02 on the substrate 200 do not overlap.
S240d, forming a second conductive layer.
As shown in fig. 16, a second conductive layer 216 is formed, wherein the second conductive layer 216 covers the second conductive structure 215, the sidewall of the first via T01, the sidewall of the second via T02, and the bottom surface of the second via T02.
Specifically, on the basis of the first conductive structure 210, the second conductive structure 215 is added, and the number of layers of the conductive layers in the electric signal deriving process of the epitaxial layer 201 is increased, so that the electrodes in different areas can quickly receive the electric signal, and the transmission speed of the electric signal received by the electrodes in different areas can be balanced, thereby improving the electrical performance of the semiconductor device. Wherein the electrode includes any one of a gate electrode, a source electrode, and a drain electrode. According to the technical scheme provided by the embodiment of the invention, the same photoresist layer 209 is used in the process of preparing the first through hole T01 in the first insulating layer 211 of the epitaxial layer 201 far away from the surface of the substrate 200 and the second through hole T02 in the epitaxial layer 201, and correspondingly, the processes of gluing and removing the photoresist are needed once, so that the preparation process is simplified, and the preparation cost is reduced. And the photoresist layer 209 is used as a mask to etch the first conductive layer 208 and the first insulating layer 211, before forming the first through hole T01, ion implantation is performed on the bottoms of the photoresist layer 209 and the grooves to form doping ions for hardening the photoresist layer 209 in the photoresist layer 209, so that the hardness of the photoresist layer 209 is increased, the lateral dimension of the photoresist layer 209 is reduced in a negligible manner in the etching process, the metal layer (such as the third conductive layer 205) is prevented from being damaged in the etching process in the first aspect, the etching precision of the first through hole T01 and the second through hole T02 is improved, the second conductive layer 216 is prevented from being easily shorted with the third conductive layer 205, and the yield of the semiconductor device is further improved; in the second aspect, before the photoresist layer 209 is used as a mask to etch the first conductive layer 208 and the first insulating layer 211 to form the first through hole T01, ion implantation is performed on the bottoms of the photoresist layer 209 and the grooves, and the surface of the first insulating layer 211 breaks the original combination between atoms under the effect of the implanted ions, so that the combination becomes loose, the etching speed becomes fast, and the use amount of the photoresist is reduced; in the third aspect, during etching, the lateral dimension L of the photoresist layer 209 may be reduced to a negligible extent, so that the design dimension of the scribe line may be reduced, and the total number of chips in the wafer may be increased, where a wafer is diced at the scribe line, thereby obtaining the semiconductor device in the embodiment of the present invention.
Optionally, on the basis of the above technical solution, as shown in fig. 17, fig. 17 is a schematic flow chart included in S200 in fig. 8, and S200 includes:
S200a, providing a substrate.
As shown in fig. 9, a substrate 200 is provided.
And S200b, forming an epitaxial layer on one side of the substrate.
As shown in fig. 9, an epitaxial layer 201 is formed on one side of a substrate 200.
And S200c, forming an ohmic contact layer on the surface of the epitaxial layer, which is far away from the substrate.
As shown in fig. 9, an ohmic contact layer 202 is formed on a surface of the epitaxial layer 201 remote from the substrate 200.
And S200d, forming a first sub-insulating layer on the surface of the ohmic contact layer, which is far away from the epitaxial layer.
As shown in fig. 9, a first sub-insulating layer 203 is formed on a surface of the ohmic contact layer 202 remote from the epitaxial layer 201.
And S200e, forming at least one first conductive through hole in the first sub-insulating layer, wherein the first conductive through hole is connected with the ohmic contact layer.
As shown in fig. 9, at least one first conductive via 204 is formed in the first sub-insulating layer 203, wherein the first conductive via 204 and the ohmic contact layer 202 are connected.
And S200f, forming a third conductive layer on the surface of the first conductive through hole, which is far away from the ohmic contact layer.
As shown in fig. 9, a third conductive layer 205 is formed on the surface of the first conductive via 204 remote from the ohmic contact layer 202.
And S200g, forming a second sub-insulating layer on the surface of the third conductive layer far away from the first conductive through hole.
As shown in fig. 9, a second sub-insulating layer 206 is formed on the surface of the third conductive layer 205 remote from the first conductive via 204.
S200h, forming at least one second conductive through hole in the second sub-insulating layer, wherein the second conductive through hole is connected with the third conductive layer.
As shown in fig. 9, at least one second conductive via 207 is formed in the second sub-insulating layer 206, wherein the second conductive via 207 and the third conductive layer 205 are connected.
S200i, forming a first conductive layer on the surface, far away from the third conductive layer, of the second conductive through hole.
As shown in fig. 9, a first conductive layer 208 is formed on a surface of the second conductive via 207 remote from the third conductive layer 205.
The above technical solution provides a preparation method for preparing a semiconductor functional layer, and the first conductive structure 210 is used for leading out an electrical signal of an epitaxial layer. The first conductive layer 208 is connected to the first conductive structure 210 for extracting an electrical signal from the epitaxial layer 201. Wherein the first insulating layer 211 includes a first sub-insulating layer 203 and a second sub-insulating layer 206. The first conductive structure 210 includes an ohmic contact layer 202, a first conductive via 204, a third conductive layer 205, and a second conductive via 207. The first conductive layer 208 is used to make a wiring layer so that the second conductive via 207 can be interconnected with conductive layers of other film layers.
Optionally, on the basis of the above technical solution, as shown in fig. 18, fig. 18 is a schematic flow chart included in S240c in fig. 8, and forming the second conductive structure 215 on the surface of the first conductive layer 208 away from the first insulating layer 211 includes:
And S240c1, forming a fourth conductive layer on the surface, far away from the first insulating layer, of the first conductive layer, wherein the fourth conductive layer is connected with the first conductive layer.
As shown in fig. 16, a fourth conductive layer 212 is formed on a surface of the first conductive layer 208 remote from the first insulating layer 211, wherein the fourth conductive layer 212 and the first conductive layer 208 are connected.
And S240c2, forming a second insulating layer on the surface of the fourth conductive layer far away from the first conductive layer.
As shown in fig. 16, a second insulating layer 213 is formed on a surface of the fourth conductive layer 212 remote from the first conductive layer 208.
S240c3, forming at least one third conductive through hole in the second insulating layer, wherein the third conductive through hole is connected with the fourth conductive layer.
As shown in fig. 16, at least one third conductive via 214 is formed in the second insulating layer 213, wherein the third conductive via 214 and the fourth conductive layer 212 are connected.
And S240c4, forming a second conductive layer on the surface, far away from the fourth conductive layer, of the second insulating layer, wherein the second conductive layer is contacted with the third conductive through hole, and the fourth conductive layer and the third conductive through hole form a second conductive structure.
As shown in fig. 16, a second conductive layer is formed on a surface of the second insulating layer away from the fourth conductive layer 212, wherein the second conductive layer is in contact with the third conductive via 214, and the fourth conductive layer 212 and the third conductive via 214 form a second conductive structure 215.
The above technical solution provides a method for preparing the second conductive structure 215, and the second conductive structure 215 can also be used for leading out the electrical signal of the epitaxial layer. On the basis of the first conductive structure 210, the second conductive structure 215 is added, and the number of layers of the conductive layers in the electric signal export process of the epitaxial layer 201 is increased, so that the electrodes in different areas can quickly receive electric signals, the transmission speed of the electric signals received by the electrodes in different areas can be balanced, and the electric performance of the semiconductor device is further improved. Wherein the electrode includes any one of a gate electrode, a source electrode, and a drain electrode.
Optionally, on the basis of the above technical solution, the elements that perform ion implantation on the photoresist layer 209 and the bottom of the groove include at least one of a group iv element, a group v element, and a group iii element.
Optionally, on the basis of the above technical solution, the elements that perform ion implantation on the photoresist layer 209 and the bottom of the groove include silicon element and/or germanium element in the group iv element.
Optionally, on the basis of the above technical solution, the elements that perform ion implantation on the photoresist layer 209 and the bottom of the groove include nitrogen element and/or phosphorus element in the v main group element.
Optionally, on the basis of the above technical solution, the elements that perform ion implantation on the photoresist layer 209 and the bottom of the groove include boron element in the group iii element.
The embodiment of the invention also provides a semiconductor device, which is prepared by the preparation method of the semiconductor device in any of the above embodiments. Therefore, the semiconductor device provided in the embodiment of the present invention includes the beneficial effects of the method for manufacturing a semiconductor device in the above embodiment, and is not described herein again.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (10)
1. A method of manufacturing a semiconductor device, comprising:
Preparing a semiconductor functional layer, wherein the semiconductor functional layer at least comprises a substrate and an epitaxial layer, a first insulating layer and a first conducting layer are formed on the surface, far away from the substrate, of the epitaxial layer, a first conducting structure is arranged in the first insulating layer, the first conducting layer is located on the surface, far away from the epitaxial layer, of the first insulating layer, and the first conducting layer is connected with the first conducting structure;
Forming a photoresist layer on one side of the first conductive layer far away from the epitaxial layer, wherein the photoresist layer is provided with a groove, the groove penetrates through the photoresist layer, and the orthographic projection of the groove on the substrate and the orthographic projection of the first conductive structure on the substrate are not overlapped;
ion implantation is carried out on the photoresist layer and the bottoms of the grooves so as to form doped ions used for hardening the photoresist layer in the photoresist layer;
Etching the first conductive layer and the first insulating layer by taking the photoresist layer as a mask plate to form a first through hole, wherein the first through hole exposes the epitaxial layer;
and etching the epitaxial layer by taking the photoresist layer as a mask plate to form a second through hole, wherein the second through hole penetrates through the epitaxial layer, and the second through hole is communicated with the first through hole.
2. The method of manufacturing a semiconductor device according to claim 1, wherein etching the epitaxial layer with the photoresist layer as a mask to form the second via further comprises:
and carrying out ion implantation on the photoresist layer and the epitaxial layer for hardening the photoresist layer.
3. The method for manufacturing a semiconductor device according to claim 1, wherein after etching the epitaxial layer by using the photoresist layer as a mask, the method further comprises:
Removing the photoresist layer;
Forming a second conductive structure on the surface of the first conductive layer far away from the first insulating layer, wherein the second conductive structure is connected with the first conductive structure through the first conductive layer, and the orthographic projection of the second conductive structure on the substrate is not overlapped with the orthographic projection of the first through hole and the second through hole on the substrate;
and forming a second conductive layer, wherein the second conductive layer covers the second conductive structure, the side wall of the first through hole, the side wall of the second through hole and the bottom surface of the second through hole.
4. The method for manufacturing a semiconductor device according to claim 1, wherein manufacturing the semiconductor functional layer comprises:
Providing a substrate;
forming an epitaxial layer on one side of the substrate;
Forming an ohmic contact layer on the surface of the epitaxial layer far away from the substrate;
Forming a first sub-insulating layer on the surface of the ohmic contact layer far away from the epitaxial layer;
Forming at least one first conductive via in the first sub-insulating layer, wherein the first conductive via is connected with the ohmic contact layer;
Forming a third conductive layer on the surface of the first conductive through hole far away from the ohmic contact layer;
forming a second sub-insulating layer on the surface of the third conductive layer far away from the first conductive through hole;
forming at least one second conductive via within the second sub-insulating layer, wherein the second conductive via is connected to the third conductive layer;
And forming the first conductive layer on the surface of the second conductive through hole far away from the third conductive layer.
5. The method of manufacturing a semiconductor device according to claim 3, wherein forming a second conductive structure on a surface of the first conductive layer remote from the first insulating layer comprises:
forming a fourth conductive layer on the surface of the first conductive layer far away from the first insulating layer, wherein the fourth conductive layer is connected with the first conductive layer;
Forming a second insulating layer on the surface of the fourth conductive layer far away from the first conductive layer;
Forming at least one third conductive via in the second insulating layer, wherein the third conductive via is connected to the fourth conductive layer;
And forming a second conductive layer on the surface, far away from the fourth conductive layer, of the second insulating layer, wherein the second conductive layer is in contact with the third conductive through hole, and the fourth conductive layer and the third conductive through hole form the second conductive structure.
6. The method of manufacturing a semiconductor device according to claim 1, wherein the element that performs ion implantation on the photoresist layer and the bottom of the recess includes at least one of a group iv element, a group v element, and a group iii element.
7. The method according to claim 6, wherein the elements for ion implantation of the photoresist layer and the bottom of the recess include silicon and/or germanium elements of main group iv elements.
8. The method according to claim 6, wherein the element for ion implantation of the photoresist layer and the bottom of the recess comprises nitrogen and/or phosphorus in the group v element.
9. The method of manufacturing a semiconductor device according to claim 6, wherein the element that performs ion implantation on the photoresist layer and the bottom of the recess includes boron element in the group iii element.
10. A semiconductor device manufactured by the manufacturing method of the semiconductor device according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410275643.0A CN117877981B (en) | 2024-03-12 | 2024-03-12 | Semiconductor device and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410275643.0A CN117877981B (en) | 2024-03-12 | 2024-03-12 | Semiconductor device and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117877981A CN117877981A (en) | 2024-04-12 |
| CN117877981B true CN117877981B (en) | 2024-05-17 |
Family
ID=90579600
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410275643.0A Active CN117877981B (en) | 2024-03-12 | 2024-03-12 | Semiconductor device and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117877981B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1521803A (en) * | 2002-11-25 | 2004-08-18 | 株式会社瑞萨科技 | Method for manufacturing semiconductor device |
| CN102136415A (en) * | 2010-01-27 | 2011-07-27 | 中芯国际集成电路制造(上海)有限公司 | Method for improving roughness of line edge of photoetching pattern in semiconductor process |
| CN112635397A (en) * | 2020-12-18 | 2021-04-09 | 华虹半导体(无锡)有限公司 | Method for manufacturing through hole |
| CN113130747A (en) * | 2019-12-30 | 2021-07-16 | 中芯国际集成电路制造(北京)有限公司 | Method for forming semiconductor structure |
-
2024
- 2024-03-12 CN CN202410275643.0A patent/CN117877981B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1521803A (en) * | 2002-11-25 | 2004-08-18 | 株式会社瑞萨科技 | Method for manufacturing semiconductor device |
| CN102136415A (en) * | 2010-01-27 | 2011-07-27 | 中芯国际集成电路制造(上海)有限公司 | Method for improving roughness of line edge of photoetching pattern in semiconductor process |
| CN113130747A (en) * | 2019-12-30 | 2021-07-16 | 中芯国际集成电路制造(北京)有限公司 | Method for forming semiconductor structure |
| CN112635397A (en) * | 2020-12-18 | 2021-04-09 | 华虹半导体(无锡)有限公司 | Method for manufacturing through hole |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117877981A (en) | 2024-04-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9171927B2 (en) | Spacer replacement for replacement metal gate semiconductor devices | |
| US20180082997A1 (en) | Vdmos transistors, bcd devices including vdmos transistors, and methods for fabricating integrated circuits with such devices | |
| CN104067384A (en) | Method and system for a gallium nitride vertical JFET with self-aligned source and gate | |
| CN103094121B (en) | A kind of method be used for producing the semiconductor devices | |
| CN113257921B (en) | Semiconductor structure | |
| CN116364644A (en) | Method for forming a thin semiconductor-on-insulator SOI substrate | |
| CN109427678A (en) | Semiconductor structure and forming method thereof | |
| CN208548342U (en) | Semiconductor devices | |
| CN104854705A (en) | Method for manufacturing semiconductor device | |
| CN102201366B (en) | Trench type power semiconductor structure with Schottky diode and manufacturing method thereof | |
| US20110095365A1 (en) | Power transistor with improved high-side operating characteristics and reduced resistance and related apparatus and method | |
| CN117877981B (en) | Semiconductor device and preparation method thereof | |
| US7923330B2 (en) | Method for manufacturing a semiconductor device | |
| CN115547830A (en) | Method for manufacturing gallium nitride power device, device and integrated circuit | |
| CN213459743U (en) | High electron mobility transistor device and electronic device | |
| US11257946B2 (en) | Method of forming a power semiconductor device | |
| KR102062050B1 (en) | Combined gate trench and contact etch process and related structure | |
| CN104008975A (en) | Manufacturing method of groove-type power MOS transistor | |
| CN111244026A (en) | Group III nitride devices and methods of making ohmic contacts for group III nitride-based devices | |
| CN117936569B (en) | Semiconductor device and preparation method thereof | |
| US20080233702A1 (en) | Method of forming a recess in a semiconductor structure | |
| CN110676173B (en) | Semiconductor device structure and forming method thereof | |
| US11515416B2 (en) | Laterally-diffused metal-oxide semiconductor transistor and method therefor | |
| US20240014306A1 (en) | Semiconductor Structure with Features of D-mode and E-mode GaN Devices and Semiconductor Process Thereof | |
| US7648898B2 (en) | Method to fabricate gate electrodes |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |