CN106783949A - Unidirectional TVS structures and its manufacture method - Google Patents
Unidirectional TVS structures and its manufacture method Download PDFInfo
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- CN106783949A CN106783949A CN201611177402.4A CN201611177402A CN106783949A CN 106783949 A CN106783949 A CN 106783949A CN 201611177402 A CN201611177402 A CN 201611177402A CN 106783949 A CN106783949 A CN 106783949A
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 132
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 238000001459 lithography Methods 0.000 claims description 12
- 238000009792 diffusion process Methods 0.000 claims description 5
- 239000002019 doping agent Substances 0.000 claims 2
- 230000001052 transient effect Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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Abstract
There is provided a kind of unidirectional TVS structures, including：Substrate, doped with first kind impurity；First doped region, is arranged on the top surface of the substrate and doped with Second Type impurity；Second doped region, is arranged on the subjacent of the substrate and doped with first kind impurity；At least one the 3rd doped regions, are arranged on the subjacent of the substrate and doped with Second Type impurity；And conductive layer, it is arranged on the 3rd doped region lower section and is electrically connected with second doped region and the 3rd doped region.Additionally provide a kind of method for manufacturing above-mentioned TVS structures.
Description
Technical field
The present invention relates to TVS fields, and in particular to a kind of unidirectional TVS structures and its manufacture method.
Background technology
The two poles of the earth of TVS (Transient Voltage Suppressor, transient voltage suppresses) diode are subject to reverse wink
During state high energy impact events, the high impedance of its two interpolar can be changed into Low ESR by it at a terrific speed, absorb power supply and holding wire
On surge power, make the voltage clamp of two interpolars in a predetermined value.
Traditional unidirectional TVS only one of which PN junction, device has individual event electric conductivity, controls the resistivity of substrate and doping dense
Degree carrys out the breakdown voltage of control device.Used as protection device, Surge handling capability is its key index, it is generally the case that device
Chip area is bigger, and Surge handling capability is stronger.It is contemplated that cost, chip package and the physics chi for needing circuit to be protected
Very little, increase chip area is severely restricted.
As shown in figure 1,102 is the doped layer doped with p type impurity or N-type impurity, 104 is doping for traditional unidirectional TVS
There is the doped layer of another impurity of p type impurity and N-type impurity.When the two poles of the earth of TVS diode are rushed by reverse transient state high-energy
When hitting, the high impedance of its two interpolar can be changed into Low ESR by it at a terrific speed, absorb the surge work(on power supply and holding wire
Rate, makes the voltage clamp of two interpolars in a predetermined value.
However, TVS structures above have the disadvantages that：Surge handling capability is restricted by the serious of die size；Change
Varying doping concentration and substrate concentration are limited to Surge handling capability lifting, and are limited by device operating voltages；Reduce silicon chip
Thickness can increase Surge handling capability, but limited by producing line treatment thin slice ability.
The content of the invention
Object of the present invention is to provide a kind of TVS structures, to improve the Surge handling capability of TVS.
To realize object above, the invention provides a kind of unidirectional TVS structures, including：
Substrate, doped with first kind impurity；
First doped region, is arranged on the top surface of the substrate and doped with Second Type impurity；
Second doped region, is arranged on the subjacent of the substrate and doped with first kind impurity；
At least one the 3rd doped regions, are arranged on the subjacent of the substrate and doped with Second Type impurity；And
Conductive layer, is arranged on the 3rd doped region lower section and is electrically connected with second doped region and the 3rd doped region.
Preferably, the first kind impurity is N-type impurity and the Second Type impurity is p type impurity；Or the first kind
Type impurity is p type impurity and the Second Type impurity is N-type impurity.
Preferably, the maximum inscribed circle in the lateral cross section of the 3rd doped region with diameter greater than equal to 100 μm.
Preferably, doping concentration of the doping concentration of second doped region more than the substrate.
Preferably, the concentration in the first kind impurity on the second doped region surface is 1 × 1019atom/cm3-1×
1021atom/cm3。
Preferably, the concentration of the first kind impurity in the substrate is 5 × 1013atom/cm3-1×1018atom/cm3；
The concentration of the Second Type impurity on the first doped region surface is 1 × 1019atom/cm3-1×1021atom/cm3；And/or the 3rd
The concentration of the Second Type impurity on doped region surface is 1 × 1019atom/cm3-1×1021atom/cm3。
Preferably, the thickness of the substrate is 150 μm~350 μm；The junction depth of first doped region is 10-60 μm；This second
The junction depth of doped region is 10-100 μm；And/or the 3rd doped region junction depth be 10-100 μm.
Preferably, this also includes the 4th doped region to TVS structures, and the 4th doped region is arranged on the first doped region and substrate
Between and doped with first kind impurity.
Preferably, the concentration of the first kind impurity in the 4th doped region is 5 × 1013atom/cm3-1×1019atom/
cm3。
It is highly preferred that the concentration of the first kind impurity in the 4th doped region is 5 × 1014atom/cm3。
Preferably, the diffusion depth of the 4th doped region is 20-60 μm.
Present invention also offers a kind of method for manufacturing TVS structures recited above, including：
One at least one the 3rd doped regions are made by lithography doped with the bottom surface of the substrate of first kind impurity；
Second Type impurity is doped in the 3rd doped region；
The second doped region is made by lithography in the bottom surface of substrate；
First kind impurity is doped in second doped region；
Second Type impurity is doped to the top surface of substrate to form the first doped region；And
Conductive layer is grown below the 3rd doped region to be electrically connected with by second doped region and the 3rd doped region.
Preferably, the first kind impurity is N-type impurity and the Second Type impurity is p type impurity；Or the first kind
Type impurity is p type impurity and the Second Type impurity is N-type impurity.
Preferably, after be doped to Second Type impurity in the 3rd doped region by step, also pushed away including carrying out high temperature
Enter, propulsion temperature is 1200-1300 DEG C so that the junction depth of the 3rd doped region is 10-100 μm.
Preferably, doping concentration of the doping concentration of second doped region more than the substrate.
Preferably, the concentration in the first kind impurity on the second doped region surface is 1 × 1019atom/cm3-1×
1021atom/cm3。
Preferably, the concentration of the Second Type impurity on the first doped region surface is 1 × 1019atom/cm3-1×1021atom/
cm3；And/or the 3rd the concentration of Second Type impurity on doped region surface be 1 × 1019atom/cm3-1×1021atom/cm3。
Preferably, after the step of Second Type impurity is doped into the top surface of substrate to form the first doped region, also
Including carrying out high temperature propulsion, propulsion temperature is 1200-1300 DEG C so that the junction depth of the 3rd doped region is 10-100 μm.
Preferably, the concentration of the Second Type impurity on the first doped region surface is 1 × 1019atom/cm3-1×1021atom/
cm3。
Present invention also offers a kind of method of manufacture TVS structures, including：
One at least one the 3rd doped regions are made by lithography doped with the bottom surface of the substrate of first kind impurity；
Second Type impurity is doped in the 3rd doped region；
First kind impurity is doped to the top surface of substrate to form the 4th doped region；
The second doped region is made by lithography in the bottom surface of substrate；
First kind impurity is doped in second doped region；
Second Type impurity is doped to the 4th doped region top to form the first doped region；And
Conductive layer is grown below the 3rd doped region to be electrically connected with by second doped region and the 3rd doped region.
The TVS structures that the present invention is provided, substrate lower section is provided with the second doped region and the 3rd doped region, and is passed through
Be electrically connected with for second doped region and the 3rd doped region by conductive layer, is capable of achieving the forward current injection of PN junction, modulates substrate conductance,
So as to strengthen the Surge handling capability of device, in normal range of operation, positive through-current capability can meet protection demand.
Brief description of the drawings
Fig. 1 is the schematic diagram of existing TVS structures；
Fig. 2 is the upward view for not drawing conductive layer of TVS structures of the invention；
Fig. 3 is profile of the TVS structures of the invention along the line A-A in Fig. 2；
Fig. 4 is the profile of another embodiment of TVS structures of the invention；
Fig. 5 is the profile of another embodiment of TVS structures of the invention；And
Fig. 6 is the profile of another embodiment of TVS structures of the invention.
Fig. 7 is the profile of another embodiment of TVS structures of the invention.
Specific embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
It should be noted that in accompanying drawing or specification description, similar or identical feature all uses identical label.
The noun of locality " top surface " mentioned in this article, " bottom surface ", " on ", D score etc., be described only with reference to the direction of accompanying drawing,
It is the position relationship of each feature being best understood from for technical staff in the present invention, as just illustration purpose, and can not
It is interpreted as limitation of the present invention.
In addition, though the scope of the parameter there is shown herein feature, it should be appreciated that the value at scope two ends is without being definitely equal to
Corresponding value, but corresponding value can be similar in acceptable error margin or design constraint.
Referring to Fig. 2 and Fig. 3, some embodiments of the invention, TVS structures include：Substrate 202, the first doped region
204, the second doped region 206, the 3rd doped region 208 and conductive layer 210.Substrate 202 is doped with first kind impurity.First doping
Area 204 is arranged on the top surface of the substrate and doped with Second Type impurity.Second doped region 206 is arranged on substrate lower section simultaneously
Doped with first kind impurity；3rd doped region 208 is arranged on substrate lower section and doped with Second Type impurity.Conductive layer
210 are arranged on the lower section of the 3rd doped region 208 and are electrically connected with the doped region 208 of the second doped region 206 and the 3rd.In Fig. 2
Embodiment in, the quantity of the 3rd doped region 208 is 4, but in other embodiments, the quantity of the 3rd doped region is not limited to
Four, one or more.
The TVS structures that the present invention is provided, substrate lower section is provided with the second doped region and the 3rd doped region, and is passed through
Be electrically connected with for second doped region and the 3rd doped region by conductive layer, is capable of achieving the forward current injection of PN junction, modulates substrate conductance,
So as to strengthen the Surge handling capability of device, in normal range of operation, positive through-current capability can meet protection demand.
In the embodiment of fig. 2, the 3rd doped region is shaped as cylinder, the lateral cross section of the cylinder with diameter greater than
Equal to 100 μm.In other embodiments, the shape of the 3rd doped region 208 can for square, cuboid or other rule or
Irregular shape.To the 3rd doped region 208 of different shapes, the maximum inscribed circle in the lateral cross section of the 3rd doped region 208
With diameter greater than equal to 100 μm.For example, with reference to Fig. 4, when the lateral cross section of the 3rd doped region 208 is pentalpha, five-pointed star
The diameter D of interior maximum inscribed circle is more than or equal to 100 μm.
In certain embodiments, the first kind impurity is N-type impurity and the Second Type impurity is p type impurity.
In some embodiments, the first kind impurity is p type impurity and the Second Type impurity is N-type impurity.In some embodiments
In, the conductive layer 210 is metal level or other conductive films.
In certain embodiments, doping concentration of the doping concentration of second doped region more than the substrate.In some implementations
It is 1 × 10 in the concentration of the first kind impurity on the second doped region surface in example19atom/cm3-1×1021atom/cm3.One
In a little embodiments, the concentration of the first kind impurity in the substrate is 5 × 1013 atom/cm3-1×1018atom/cm3.One
It is 1 × 10 in the concentration of the Second Type impurity on the first doped region surface in a little embodiments19atom/cm3-1×1021atom/
cm3.In certain embodiments, the concentration in the Second Type impurity on the 3rd doped region surface is 1 × 1019atom/cm3-1×
1021atom/cm3。
In certain embodiments, the thickness of the substrate is 150 μm~350 μm.In certain embodiments, first doped region
Junction depth be 10-60 μm.In certain embodiments, the junction depth of second doped region is 10-100 μm.In certain embodiments, should
The junction depth of the 3rd doped region is 10-100 μm.
In the fig. 3 embodiment, the TVS structures are boss type.However, in certain embodiments, the TVS structures can be with
For plate, as shown in Figure 5.
Referring to Fig. 6 and Fig. 7, in order to realize different operating voltages, this also includes the 4th doped region 212 to TVS structures, should
4th doped region 212 is arranged between the first doped region and substrate and doped with first kind impurity.In certain embodiments, exist
The concentration of the first kind impurity in the 4th doped region 212 is 5 × 1013atom/cm3-1×1019atom/cm3.In certain implementation
In example, the concentration of the first kind impurity in the 4th doped region 212 is 5 × 1014atom/cm3.In certain embodiments, should
The diffusion depth of the 4th doped region 212 is 20-60 μm.The operating voltage of the TVS structures may depend on the 4th doped region 212
Diffusion depth, can select the diffusion depth of the 4th doped region 212 according to the operating voltage of TVS.
Present invention also offers a kind of method for manufacturing TVS structures recited above, including：One doped with the first kind
The bottom surface of the substrate of impurity makes at least one the 3rd doped regions by lithography；Second Type impurity is doped in the 3rd doped region；
The second doped region is made by lithography in the bottom surface of substrate；First kind impurity is doped in second doped region；Second Type is miscellaneous
Matter is doped to the top surface of substrate to form the first doped region；And conductive layer is grown below the 3rd doped region second mixed with by this
Miscellaneous area and the 3rd doped region are electrically connected with.In certain embodiments, the conductive layer 210 is preferably metal level.In some realities
Apply in example, the conductive layer 210 can also be conductive film, and the material of the conductive layer does not limit specific material, as long as can
Second doped region and the 3rd doped region are electrically connected with.
In certain embodiments, the first kind impurity is N-type impurity and the Second Type impurity is p type impurity.
In some embodiments, the first kind impurity is p type impurity and the Second Type impurity is N-type impurity.
In certain embodiments, after be doped to Second Type impurity in the 3rd doped region by step, also include into
Row high temperature is advanced, and propulsion temperature is 1200-1300 DEG C so that the junction depth of the 3rd doped region is 10-100 μm.
In certain embodiments, doping concentration of the doping concentration of second doped region more than the substrate.In some implementations
It is 1 × 10 in the concentration of the first kind impurity on the second doped region surface after the second doped region is doped in example19atom/
cm3-1×1021atom/cm3.In certain embodiments, after being doped to substrate surface, the Equations of The Second Kind on the first doped region surface
The concentration of type impurity is 1 × 1019atom/cm3-1×1021atom/cm3.In certain embodiments, the 3rd doped region is mixed
After miscellaneous, the concentration of the Second Type impurity on the 3rd doped region surface is 1 × 1019atom/cm3-1×1021atom/cm3。
In certain embodiments, the step of Second Type impurity is doped into the top surface of substrate to form the first doped region
Afterwards, also including carrying out high temperature propulsion, propulsion temperature is 1200-1300 DEG C so that the junction depth of the 3rd doped region is 10-100 μm.
Preferably, the concentration of the Second Type impurity on the first doped region surface is 1 × 1019atom/cm3-1×1021atom/cm3。
Present invention also offers the method for another kind manufacture TVS structures, including：One doped with first kind impurity lining
The bottom surface at bottom makes at least one the 3rd doped regions by lithography；Second Type impurity is doped in the 3rd doped region；By the first kind
Type impurity is doped to the top surface of substrate to form the 4th doped region；The second doped region is made by lithography in the bottom surface of substrate；By the first kind
Type impurity is doped in second doped region；And by Second Type impurity be doped to the 4th doped region top mixed with forming first
Miscellaneous area；And growth conductive layer is electrically connected with by second doped region and the 3rd doped region below the 3rd doped region.
It is the step of manufacture method can also include other, same or like the step of these steps are with approach mentioned above, herein
Repeat no more.
Above-mentioned manufacture method, except specializing sequencing, the order of the step in method can be adjusted, certain
A little steps can be carried out and/or with other steps by different order while carry out, and the priority of step should not be by described in specification
It is construed to limitation of the invention.Each step is mentioned above can be comprising several sub-steps.
Presently preferred embodiments of the present invention is the foregoing is only, is not intended to limit the invention, it is all in essence of the invention
Any modification, equivalent and improvement made within god and principle etc., should be included within the scope of the present invention.
Claims (20)
1. a kind of unidirectional TVS structures, including：
Substrate, doped with first kind impurity；
First doped region, is arranged on the top surface of the substrate and doped with Second Type impurity；
Second doped region, is arranged on the subjacent of the substrate and doped with first kind impurity；
At least one the 3rd doped regions, are arranged on the subjacent of the substrate and doped with Second Type impurity；And
Conductive layer, is arranged on the 3rd doped region lower section and is electrically connected with second doped region and the 3rd doped region.
2. TVS structures as claimed in claim 1 unidirectional, it is characterised in that the first kind impurity be N-type impurity and this
Two type dopants are p type impurity；Or the first kind impurity is that p type impurity and the Second Type impurity are N-type impurity.
3. TVS structures as claimed in claim 1 unidirectional, it is characterised in that the maximum in the lateral cross section of the 3rd doped region
Inscribed circle with diameter greater than equal to 100 μm.
4. TVS structures as claimed in claim 1 unidirectional, it is characterised in that the doping concentration of second doped region is more than the lining
The doping concentration at bottom.
5. TVS structures as claimed in claim 1 unidirectional, it is characterised in that in the first kind impurity on the second doped region surface
Concentration be 1 × 1019atom/cm3-1×1021atom/cm3。
6. TVS structures as claimed in claim 1 unidirectional, it is characterised in that：
The concentration of the first kind impurity in the substrate is 5 × 1013atom/cm3-1×1018atom/cm3；
It is 1 × 10 in the concentration of the Second Type impurity on the first doped region surface19atom/cm3-1×1021atom/cm3；And/or
It is 1 × 10 in the concentration of the Second Type impurity on the 3rd doped region surface19atom/cm3-1×1021atom/cm3。
7. TVS structures as claimed in claim 1 unidirectional, it is characterised in that：
The thickness of the substrate is 150 μm~350 μm；
The junction depth of first doped region is 10-60 μm；
The junction depth of second doped region is 10-100 μm；And/or
The junction depth of the 3rd doped region is 10-100 μm.
8. TVS structures as claimed in claim 1 unidirectional, it is characterised in that this also includes the 4th doped region to TVS structures, should
4th doped region is arranged between the first doped region and substrate and doped with first kind impurity.
9. TVS structures as claimed in claim 8 unidirectional, it is characterised in that first kind impurity in the 4th doped region
Concentration is 5 × 1013atom/cm3-1×1019atom/cm3。
10. TVS structures as claimed in claim 8 unidirectional, it is characterised in that first kind impurity in the 4th doped region
Concentration is 5 × 1014atom/cm3。
11. unidirectional TVS structures as claimed in claim 8, it is characterised in that the diffusion depth of the 4th doped region is 20-60 μ
m。
A kind of 12. methods for manufacturing TVS structures as claimed in claim 1, including：
One at least one the 3rd doped regions are made by lithography doped with the bottom surface of the substrate of first kind impurity；
Second Type impurity is doped in the 3rd doped region；
The second doped region is made by lithography in the bottom surface of substrate；
First kind impurity is doped in second doped region；
Second Type impurity is doped to the top surface of substrate to form the first doped region；And
Conductive layer is grown below the 3rd doped region to be electrically connected with by second doped region and the 3rd doped region.
13. manufacture methods as claimed in claim 12, it is characterised in that the first kind impurity be N-type impurity and this
Two type dopants are p type impurity；Or the first kind impurity is that p type impurity and the Second Type impurity are N-type impurity.
14. manufacture methods as claimed in claim 12, it is characterised in that Second Type impurity is doped to the 3rd in step
After in doped region, also including carrying out high temperature propulsion, propulsion temperature is 1200-1300 DEG C so that the junction depth of the 3rd doped region is
10-100μm。
15. manufacture methods as claimed in claim 12, it is characterised in that the doping concentration of second doped region is more than the substrate
Doping concentration.
16. manufacture methods as claimed in claim 12, it is characterised in that in the first kind impurity on the second doped region surface
Concentration is 1 × 1019atom/cm3-1×1021atom/cm3。
17. manufacture methods as claimed in claim 12, it is characterised in that：
The concentration of the Second Type impurity on the first doped region surface is 1 × 1019atom/cm3-1×1021atom/cm3；And/or
The concentration of the Second Type impurity on the 3rd doped region surface is 1 × 1019atom/cm3-1×1021atom/cm3。
18. manufacture methods as claimed in claim 12, it is characterised in that Second Type impurity is being doped to the top surface of substrate
After the step of to form the first doped region, also including carrying out high temperature propulsion, propulsion temperature is 1200-1300 DEG C so that the 3rd
The junction depth of doped region is 10-100 μm.
19. unidirectional TVS structures as claimed in claim 12, it is characterised in that the Second Type impurity on the first doped region surface
Concentration be 1 × 1019atom/cm3-1×1021atom/cm3。
A kind of 20. methods for manufacturing TVS structures as claimed in claim 8, including：
One at least one the 3rd doped regions are made by lithography doped with the bottom surface of the substrate of first kind impurity；
Second Type impurity is doped in the 3rd doped region；
First kind impurity is doped to the top surface of substrate to form the 4th doped region；
The second doped region is made by lithography in the bottom surface of substrate；
First kind impurity is doped in second doped region；
Second Type impurity is doped to the 4th doped region top to form the first doped region；And
Conductive layer is grown below the 3rd doped region to be electrically connected with by second doped region and the 3rd doped region.
Priority Applications (2)
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|---|---|---|---|
| CN201611177402.4A CN106783949A (en) | 2016-12-19 | 2016-12-19 | Unidirectional TVS structures and its manufacture method |
| PCT/CN2017/116174 WO2018113583A1 (en) | 2016-12-19 | 2017-12-14 | Unidirectional tvs structure and manufacturing method therefor |
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| CN201611177402.4A CN106783949A (en) | 2016-12-19 | 2016-12-19 | Unidirectional TVS structures and its manufacture method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018113583A1 (en) * | 2016-12-19 | 2018-06-28 | 东莞市阿甘半导体有限公司 | Unidirectional tvs structure and manufacturing method therefor |
| CN110504324A (en) * | 2019-08-12 | 2019-11-26 | 电子科技大学 | A kind of high-voltage transient voltage suppressor diode |
| WO2023050387A1 (en) * | 2021-09-29 | 2023-04-06 | 上海韦尔半导体股份有限公司 | Unidirectional transient-voltage-suppression diode and process for preparing same |
| EP4340044A1 (en) * | 2022-09-16 | 2024-03-20 | Littelfuse Semiconductor (Wuxi) Co., Ltd. | Unidirectional tvs device with improved surge current performance |
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| WO2018113583A1 (en) * | 2016-12-19 | 2018-06-28 | 东莞市阿甘半导体有限公司 | Unidirectional tvs structure and manufacturing method therefor |
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