CN105826366A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
CN105826366A
CN105826366A CN201610052223.1A CN201610052223A CN105826366A CN 105826366 A CN105826366 A CN 105826366A CN 201610052223 A CN201610052223 A CN 201610052223A CN 105826366 A CN105826366 A CN 105826366A
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China
Prior art keywords
contact
substrate
semiconductor device
metal level
aforementioned
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Granted
Application number
CN201610052223.1A
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Chinese (zh)
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CN105826366B (en
Inventor
潘之昊
弗里德里希·哈恩
斯特芬·霍兰
奥拉夫·普芬尼希斯多夫
约亨·韦南茨
汉斯-马丁·里特
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Naizhiya Co Ltd
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NXP BV
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Publication of CN105826366B publication Critical patent/CN105826366B/en
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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a semiconductor device and a method of making the same. The device includes a semiconductor substrate provided in a chip-scale package (CSP). The device also includes a plurality of contacts provided on a major surface of the substrate. The device further includes an electrically floating metal layer forming an ohmic contact on a backside of the semiconductor substrate. The device is operable to conduct a current that passes through the substrate from a first of said plurality of contacts to a second of said plurality of contacts via the metal layer on the backside.

Description

Semiconductor device
Technical field
The present invention relates to semiconductor device.In particular it relates to the semiconductor device that can provide as wafer-level package (CSP).
Background technology
The existing discrete semiconductor device (such as, transient voltage surge device, Schottky diode, bipolar transistor and vertical MOS device) processing big electric current generally comprises the electrical contact being positioned at Semiconductor substrate top and back.In these devices, flow between the contact in substrate top of the main electric current and the contact on substrate back.Therefore, it is distributed in whole substrate bulk electric current overall average.
When introducing surface mount device (SMD), by using closing line or folder to solve the problem that top contact is connected to the plane identical with back contact.
Along with the further trend of miniaturization, need less encapsulation.In the device processing big electric current, silicon or the limited electrical conductivity of other semi-conducting materials, therefore it is not generally possible to reduce the size of substrate.Therefore, it is necessary to make the ratio of substrate volume and encapsulation volume maximize.
Wafer-level package (CSP), especially Flip-Chip Using, it is possible to provide relatively large substrate volume and relatively small package dimension.In some CSP, the encapsulation volume close to 100% is silicon.
In CSP, device contacts is positioned in the common surface of substrate.Fig. 1 shows the example of this device 100.Device 100 includes the Semiconductor substrate 112 with first type surface 102.First contact 104 contacts 106 with second and is arranged on first type surface 102.In use, substrate 112 can be mounted to make first type surface 102 face down, and contact 104 and 106 is welded on carrier (such as, printed circuit board (PCB) (PCB)).
The shortcoming of the program is, the electric current in substrate 112 is horizontal (as direction of the arrows shown in fig), and it may result in current crowding and local pyrexia, and this will be substantially reduced the vigorousness of device.Specifically, as shown in Fig. 1 shown in the arrow of electric current, the CURRENT DISTRIBUTION in substrate 112 is usually uneven, and there is more high current density in contact 104 and 106 mutual immediate edges.Uneven CURRENT DISTRIBUTION, current crowding and the local pyrexia being associated may have a strong impact on the current handling capability of this device, especially wish current processing performance when this device should process bigger electric current.Therefore, this device shown in Fig. 1 may not be suitable for the application of some big electric current.
Summary of the invention
The aspect of the present invention embodies in appended independence and dependent claims.Feature from dependent claims can be combined as with the feature of independent claims, is not limited solely to be expressly recited in claim.
According to an aspect of the invention, it is provided a kind of semiconductor device.Described device includes the Semiconductor substrate being arranged in wafer-level package (CSP).Described device also includes the multiple contacts being arranged in substrate main surface.Described device is additionally included on the back of Semiconductor substrate the electrically floating metal level forming Ohmic contact.Described device is operable as conducting electric current, and the first contact from the plurality of contact of the described electric current arrives second in the plurality of contact via the metal level on back by described substrate and contacts.
The electric current that the arranging of electrically floating metal level on substrate back can realize having generally uniform CURRENT DISTRIBUTION is to flow in substrate bulk.The electric current flowing to the second contact from the first contact can tend to there is not high current density in the mutual immediate edge of described contact.This is because electric current need not flow to the second contact directly through substrate bulk from the first contact.Alternatively, electric current first can contact, from first, the metal level (metal has the resistivity less than Semiconductor substrate) flowing to back, then flow to the second contact (or vice versa) from metal level.
In the context of the present invention, term " electrically floating " may refer to be free of attachment to the metal level of applied external potential (such as ground connection or some other electromotive forces).Therefore, metal level need not be connected to the output pin of the device for realizing the connection to any this applied external potential.
According to embodiments of the invention, semiconductor device can be the discrete device relative with integrated circuit.
First contact or the second contact contact can be connected to electrically floating metal level by the conductive part (such as, one or more grooves (trench) being filled with metal or through hole) extending to electrically floating metal level from the first or second contact through substrate.So can reduce the resistance in total current path between contact.
In one embodiment, substrate can be thinner than outside device active region at least one vicinity contacted.So can reduce the resistance in the path contacted between the metal level on back.The thinner part of substrate can be formed by the one or more grooves (groove) being positioned on substrate back.Groove can etch during manufacture in back.
In one embodiment, conductive part can extend through substrate towards one or more contacts metal layer part from back.Equally, this can reduce the resistance in the path between the metal level on contact and back.The conductive part that metal level from back extends can be one or more through holes and/or the groove such as comprising metal.
Metal level can only contact the part that on substrate back, position is relative with the contact essence on first type surface.This can allow the factor for such as low on-resistance, high electric current transporting power etc and general uniform current distribution and low current crowded and optimize ultimate current distribution.Can use 3D emulation technology that contact area is optimized.
In one embodiment, during barrier (barrier) may be located at the substrate between the first contact and the second contact, in order to stop the Direct Current flowing between the first contact and the second contact at least in part.Its effect is to be route towards the metal level on substrate back by electric current, thus improves the CURRENT DISTRIBUTION in substrate bulk further.Barrier can be such as to comprise dielectric groove, and it extends down into substrate and at least partially through substrate from first type surface.
In one embodiment, on first type surface, at least one contact can at least partly surround another contact in multiple contact.Known this structure can improve the current processing performance of device further.
Described device can have two contacts.Semiconductor device can e.g. PN junction diode (such as, transient voltage suppressor diode) or the first contact be negative electrode and the second contact is the Schottky diode of anode.Other examples of the device with two contacts according to embodiment include Xiao Keli (Shockley) diode, silicon controlled rectifier (SCR) and grounded-grid type nmos pass transistor.
In another example, described device can include the 3rd contact.In this example, described device can be bipolar transistor, and wherein the first contact is emitter stage contact, and the second contact is collector contact, and the 3rd contact is base stage contact.Alternatively, described device can be MOS transistor (such as, vertical MOS transistor), and wherein the first contact is source contact, and the second contact is drain contact, and the 3rd contact is gate contact.
Semiconductor device may be mounted on carrier, such as printed circuit board (PCB).According to embodiments of the invention, electrically floating metal level is not connected to any external pin of device.
Another aspect according to the present invention, it is provided that a kind of method, described method includes: provide semiconductor wafer；Multiple contacts on the major faces of the wafers are provided；The electrically floating metal level forming Ohmic contact on the back of wafer is provided, and by wafer stripping and slicing, to manufacture above-mentioned multiple semiconductor device.
Accompanying drawing explanation
Describing embodiments of the invention the most in exemplary fashion, reference marks similar in the accompanying drawings relates to the element being similar to, wherein:
Fig. 1 shows the semiconductor device of a kind of known type；
Fig. 2 shows semiconductor device according to an embodiment of the invention；
Fig. 3 shows semiconductor device according to another embodiment of the invention；
Fig. 4 shows semiconductor device according to still another embodiment of the invention；
Fig. 5 shows semiconductor device according to another embodiment of the invention；
Fig. 6 shows semiconductor device according to still another embodiment of the invention；
Fig. 7 shows semiconductor device according to another embodiment of the invention；
Fig. 8 shows semiconductor device according to still another embodiment of the invention；And
Fig. 9 shows semiconductor device according to another embodiment of the invention.
Detailed description of the invention
Below with reference to accompanying drawing, embodiments of the invention are described.
Embodiments of the invention provide and include arranging the semiconductor device of the Semiconductor substrate in wafer-level package (CSP).This device can include the multiple contacts being arranged in substrate main surface and form the electrically floating metal level of Ohmic contact on substrate back.Arranging the current path in electrically floating metal level can provide substrate on back, this current path produces substantially uniform CURRENT DISTRIBUTION in block, so can avoid the problem relevant to current crowding, as with reference to the problem described in Fig. 1.Therefore, device can be operable as according to an embodiment of the invention, based on wafer-level package scheme, processes bigger electric current than existing device.
Current path in device can the first contact from substrate main surface downwards, with generally vertical direction (being perpendicular to arrange the first type surface of contact) flowing through substrate block, arrive the metal level on back.Then, electric current can flow through the metal level on back, again returns up through substrate bulk with generally vertical direction, arrives the second contact on first type surface.Electric current flowing in metal level on back can be about horizontal.Typically have far below the semi-conducting material for substrate (such as due to metal level, can be silicon) resistivity, so direct with generally lateral direction flowing through substrate suitably compared between the on first type surface first contact and the second contact, the electric current flowing in this device will more they tend to take above-mentioned route.It is understood that in some implementations, at least sub-fraction of total current can still horizontal mobility in device.
Fig. 2 shows the semiconductor device 10 according to the first embodiment of the present invention.Semiconductor device 10 includes Semiconductor substrate 12.Substrate 12 can such as include silicon or any other suitable semi-conducting material.As it will be explained in more detail hereinafter, substrate 12 can be manufacture time from bigger wafer the tube core of stripping and slicing.
According to embodiments of the invention, substrate 12 is arranged in wafer-level package (CSP).Therefore, substrate 12 includes the multiple contacts being arranged on its first type surface 2.In this example, multiple contacts include that the first contact 4 contacts 6 with second.Such as, this embodiment can include PN junction diode or Schottky diode, and wherein the first contact 4 is the negative electrode of diode, and the second contact 6 is the anode of diode.As it has been described above, substrate 12 may be installed on the carrier of such as printed circuit board (PCB) (PCB), and the first contact 4 contacts 6 with second and is welded on the installation surface of carrier.
In this embodiment, semiconductor device 10 includes the metal level 20 being arranged on the back 18 of substrate 12.The surface relative with being provided with multiple first type surface 2 contacted of the back 18 of substrate 12 usually substrate 12.
During backend process (BEOL) processes, metal level 20 can be deposited on the back 18 of substrate 12.Such as, metal level 20 can include such as gold, silver, copper, aluminum or the metal of more composite multi-layer.The thickness of metal level generally can be in the range of several microns.
In Fig. 2, a series of arrow is used to show through device from the electric current flowing of the first contact 4 to the second contact 6.Solid arrow in Fig. 2 shows that the electric current through substrate 12 pieces flows, and the dotted arrow in Fig. 2 shows that the electric current through metal level 20 flows.As seen from Figure 2, the electric current flowing in substrate substantially arrives metal level 20 from the first contact 4 through substrate 12, then flows along metal level, then returns up, and arrives the second contact 6 through substrate 12 pieces.Therefore, from the first contact 4 during electric current flowing through substrate 12, via the metal level 20 on back 18, then the second contact 6 is arrived.As mentioned above, it is contemplated that be not that this route is all taked in all electric currents flowing in device, and there will still likely be and contact 4 some nubbin electric currents flowing directly into the second contact 6 with generally lateral direction from first, (that is, not via metal level 20) as shown in a solid arrow in Fig. 2.But it would be recognized that major part electric current will take the route via metal level 20.
Be will be consequently realised that by the solid arrow shown in Fig. 2, the CURRENT DISTRIBUTION in substrate 12 is generally uniform so that contact 6 mutual immediate edges in the first contact 4 with second and current crowding does not occur.Describing that device compared to above with reference to Fig. 1, owing to improve the uniformity of the electric current in device 10, the device in this embodiment can process relatively large electric current, thus realizes the application using previous device to realize.
Metal level 20 keeps electrically floating (such as, being free of attachment to external voltage, such as ground connection), the electric current that otherwise will affect between the first contact 4 and the second contact 6.And it is contemplated that metal level 20 should form Ohmic contact on the surface at the back 18 of substrate 12, to allow electric current to flow freely between substrate 12 and metal level 20.Metal level 20 can have low square resistance, such as in the range of every square of several milliohms.
Reentering before substrate 12 pieces flows up and arrive the second contact 6, electric current in metal level 20 substantially can flow to region closest to the second contact 6 (same, it is usually the region of underface of the second contact 6) from the region (typically in the underface of the first contact 4) closest to the first contact 4.
In certain embodiments, available insulating barrier (not shown in accompanying drawing) covers the metal level 20 on the back side 18, with isolating metal layer 20 risk of the undesirable electrical contact being reduced to metal level 20.Before the stripping and slicing that can describe in more detail below, during wafer processes, increase insulating barrier.
As it has been described above, in this example, this device can be Schottky diode.Such as, the first contact 4 can be the negative electrode of device and can be Schottky contacts, and the second contact 6 can be the anode of Schottky diode and can be Ohmic contact.
Fig. 3 shows semiconductor device 10 according to the second embodiment of the present invention.In this embodiment, device 10 includes the substrate 12 with first type surface 2, is provided with and includes that the first contact 4, second contacts 6 and contacts multiple contacts of 8 with the 3rd on first type surface 2.In this embodiment, device 10 can be MOS transistor (such as, vertical MOS transistor), in this device, first contact 4 is the source contact of transistor, and the second contact 6 is the drain contact of transistor, and the 3rd contact 8 is the gate contact of transistor.In another embodiment, device 10 can include bipolar transistor, and in this device, the first contact 4 is the emitter stage contact of transistor, and the second contact 6 is the collector contact of transistor, and the 3rd contact 8 is the base stage contact of transistor.
By the solid arrow of Fig. 3 it can be seen that in the device of Fig. 3, the distribution of 12 pieces of interior electric current flowings of substrate is generally uniform, and avoids the current crowding at engagement edge.Equally, in the example of fig. 3, although major part electric current will be taked to flow through substrate 12, from the first contact 4 via the back 18 being arranged on substrate 12 metal level 20 to the second contact 6 route, but as shown in a solid arrow in Fig. 3, it is contemplated that the relative small portion of total current still can directly flow through substrate 12 with generally lateral direction from the first contact 4 to second contact 6 in the case of not via metal level 20.
Fig. 4 shows semiconductor device 10 according to another embodiment of the invention.The example of the present invention shown in Fig. 4 can such as be used for realizing Transient Voltage Suppressor device.In the embodiment of Fig. 1 and Fig. 2, such as metal level 20 substantially covers the whole back 18 of substrate 12.But, in the example of fig. 4, metal level 20 does not contacts with the whole back 18 of substrate 12.Alternatively, the metal level 20 in Fig. 4 only with position in the back 18 of substrate 12 with contact that (in this example, including contacting 4 and 6) essence is relative or position part contact thereunder on first type surface 2.
For realizing this, known metallization technology can be used to produce metal level 20 pattern.Such as, metal level 20 may be included in the part 22 contacted at the part that on back 18, position is relative with the contact essence on first type surface 2 with back 18.Part 22 can be linked together by connecting portion 24, to allow electric current horizontal mobility in metal level 20.Dielectric filler can be used in any gap between connecting portion 24 and back 18.
Can select the layout of metal level 20 so that in given application, the corresponding CURRENT DISTRIBUTION in substrate 12 pieces transports the parameter of performance and the distribution of general uniform current for such as low on-resistance, high electric current and low current is crowded and optimized.For designing this device, it is possible to use 3D emulation optimizes the contact area between metal level 20 and back 18.
Although Fig. 4 showing, being provided with the first contact 4 on first type surface 2 contacts 6 with second, it will be appreciated that the 3rd contact described above with reference to Fig. 3 can also be arranged, such as contact 8.It will be appreciated that due to the electric current in MOS transistor or bipolar transistor flows will be between the first contact 4 and the second contact 6, so need not to realize the contact at the 3rd location directly below contacted of metal level 20 and back 18.
Fig. 5 shows semiconductor device 10 according to still another embodiment of the invention.In this example, place obstacles in substrate 12 thing 30.Barrier 30 effect can be to stop the Direct Current flowing between the first contact 4 and the second contact 6 at least in part, thus increases total current between the first contact 4 and the second contact 6 via the ratio of metal level 20 flowing on back 18.Because, the route taked from any electric current that the first contact 4 flows directly to the second contact 6 through block passes needing from the lower section of barrier 30, which increase the path length of this route, thus compared to including the current path of metal level 20, this electric current is presented bigger resistance.
In some instances, the shape of barrier 30 can be selected as consistent with the shape of the contact on first type surface and layout.
In this example, barrier 30 includes that the first type surface 2 from substrate 12 extends, at least partially through the groove of substrate 12.Groove can be formed by etching.Groove can be filled with dielectric substance.Owing to more current is forced to flow via metal level 20, compared to the example such as described above with reference to Fig. 2 to 4,12 pieces of interior CURRENT DISTRIBUTION of substrate can be improved further.
It will be appreciated that the use of all barriers 30 as shown in Figure 5 can with other embodiments as described herein provide feature combined (such as, above with reference to Fig. 3 describe the 3rd contact and/or with reference to Fig. 4 describe patterned metal layer).
Fig. 6 shows semiconductor device 10 according to still another embodiment of the invention.Fig. 6 is the view seeing first type surface 2 down over from substrate 12.In Fig. 6 it can be seen that in this example, device 10 includes that the first contact 4 on first type surface 2 contacts 6 with second.In this example, contact configuration is selected as making the first contact 4 at least partly surround the second contact 6.Such as, in figure 6, the second contact 6 is contained in recess generally U-shaped in the first contact 4.Have been found that this structure further increases the current processing performance of device 10.It will be appreciated that this contact shape can with other features of the present invention (such as, above with reference to Fig. 2 to 5 and with reference to more examples provided below describe feature) combined.
Although embodiments of the invention can produce substantially uniform CURRENT DISTRIBUTION in device, owing to electric current needs through substrate bulk twice, so the all-in resistance of current path in device still can be improved.The example of the following description of the present invention can use some more features to solve this problem.
Fig. 7 shows semiconductor device 10 according to another embodiment of the invention.Fig. 7 illustrate only a part for device 10, i.e. includes the part (in the embodiment of Fig. 7, it is contact 4) that mentioned above on first type surface 2 one contacts.
In certain embodiments, substrate can include the pn-junction 44 being formed between substrate 12 pieces and a part of semi-conducting material 42, and described semi-conducting material is arranged on the lower section (in the example shown in Fig. 7, be contact 4 equally) of a contact.For clarity sake, this part 42 that may be present and PN junction 44 not shown in the previously described accompanying drawing.It should be noted that thinner part described below (such as groove) may be provided at not include in the example of this kind of part 42 or PN junction shown in Fig. 7.
In this embodiment, for reducing the resistance in the path of the metal level 20 from the first contact 4 to the back being arranged on substrate 12, substrate 12 ratio near contact 4 is the thinnest.Such as, the thickness t of the substrate 12 near contact 4 is less than the thickness T of the substrate 12 away from contact 4 (such as, outside the active area of device 10).Accordingly, because the substrate 12 near contact 4 is thinner, reduce resistor path between contact 4 and metal level 20.In this example, the thinner of substrate 12 is formed by the groove 50 in the back surfaces of substrate 12.The shape of groove 50 can with on apparent surface contact 4 shape similar (in terms of the top of first type surface 2), and can wafer process during be formed with etch process.
It is contemplated that in certain embodiments, substrate 12 can be thinner near more than one contact.Such as, include that the region of more than one contact can be thinning including substrate 12.For example, it is possible to arrange around the region including multiple contact, relatively wide groove.Alternatively, in multiple corresponding contact near each contact, substrate 12 can local thinning (such as, can arrange corresponding groove for each contact).
It is further envisioned that as can be combined with the feature of any other embodiment described herein above with reference to arranging of the thinner of the substrate 12 described in Fig. 7.
Fig. 8 shows semiconductor device 10 according to still another embodiment of the invention.Identical with Fig. 7, Fig. 8 illustrate only a part for device, i.e. device and includes the part of the first contact 4.In this example, device 10 includes the conductive part that the metal level 20 from back 18 extends to contact 4 partially across substrate 12.It is contemplated that this conductive part of other contacts of device (the such as second contact 6) can be provided in other examples.In one example, contact 4 is both provided with this conductive part with contacting 6.In another example, it is possible not only to any given contact position, it is also possible to other regions of substrate are arranged conductive part.For example, it is contemplated that, groove described below and/or through hole can be set in most of region of substrate on the most whole substrate.The all-in resistance that the path that can reduce between the first contact 4 and metal level 20 is set of conductive part.
In this embodiment, conductive part includes the one or more through holes being filled with conductive material (such as metal).In another example, conductive part can include one or more groove, and groove also includes metal.It is contemplated that use through hole and the combination of groove.The metal used in through hole or groove could be for forming metal level 20 and/or the same metal of top contact 4,6,8.Etch process can be used during wafer processes to manufacture through hole or groove.
Fig. 9 shows semiconductor device according to another embodiment of the invention.In this example, (the second contact 6 shown in Fig. 9, however, it is contemplated that it can be in other contacts of device in one contact, such as contact 4) by extending to the conductive part 70 of metal level 20, the metal level 20 being electrically connected on the back 18 of substrate 12 through substrate from contact 6.The arranging of conductive part can reduce the all-in resistance of the current path between the first contact 4 and the second contact 6 via metal level 20.In this example, conductive part includes the one or more through holes 70 that can comprise metal.It is contemplated that use groove substitute or form conductive part together with through hole.Metal level 20 that groove and/or through hole 70 can be filled with on the back 18 for forming substrate 12 and/or the same metal of top contact.
It is contemplated that the conductive part with reference to Fig. 8 and 9 description can be combined with any feature of the present invention described above with reference to Fig. 2 to 7.
For manufacturing device according to an embodiment of the invention, can first provide semiconductor wafer, the first type surface of described semiconductor wafer has multiple contact.In next step, electrically floating metal level can be deposited on wafer back, to form the Ohmic contact of wafer.Then by wafer stripping and slicing.Each section of wafer can form this semiconductor device as herein described.Before each cutting tube core from wafer, inventive feature (such as groove, the conductive part with reference to Fig. 8 and 9 discussion, the contact configuration with reference to Fig. 6 discussion and reference Figure 4 and 5 with reference to Fig. 7 discussion describe patterned metal layer 20 or barrier) can manufacture in wafer scale respectively and repeat in each target tube core.
Therefore, it has been described that a kind of conductor device and manufacture method thereof.Described device includes the Semiconductor substrate being arranged in wafer-level package (CSP).Described device also includes the multiple contacts being arranged in substrate main surface.Described device is additionally included on the back of Semiconductor substrate the electrically floating metal level forming Ohmic contact.This device is operable as turning on through the substrate the first contact from the plurality of contact, via the metal level on back, arrives the electric current of the second contact in the plurality of contact.
Specific embodiment notwithstanding the present invention, it should be recognized that multiple amendment/add and/or replace can be made within the scope of claimed invention.

Claims (15)

1. a semiconductor device, including:
The Semiconductor substrate being arranged in wafer-level package CSP；
The multiple contacts being arranged on the first type surface of substrate, and
The back of Semiconductor substrate is formed the electrically floating metal level of Ohmic contact,
Wherein said device is operable as conducting electric current, and the first contact from the plurality of contact of the described electric current arrives second in the plurality of contact via the metal level on back by described substrate and contacts.
Semiconductor device the most according to claim 1, wherein said first contact or described second contact are electrically connected to electrically floating metal level by the conductive part extending to electrically floating metal level from the first or second contact through substrate.
Semiconductor device the most according to claim 2, wherein said conductive part is include the one or more through holes comprised including metal and/or groove.
4. according to the semiconductor device described in aforementioned any one claim, wherein substrate is thinner than outside the active area of described device at least one vicinity contacted, to reduce the resistance in the path between the metal level on described contact and back.
Semiconductor device the most according to claim 4, the thinner part of wherein said substrate includes the one or more grooves being positioned on substrate back.
6. according to the semiconductor device described in aforementioned any one claim, including the metal layer part on back through substrate towards the plurality of contact in the conductive part of one or more extensions.
Semiconductor device the most according to claim 6, the conductive part that wherein metal level from the back side extends is include the one or more through holes comprised including metal and/or groove.
8., according to the semiconductor device described in aforementioned any one claim, wherein said metal level only contacts the part that position on described substrate back contacts and the second contact essence is relative with first on described first type surface.
9. according to the semiconductor device described in aforementioned any one claim, also include the barrier in the substrate between the first contact and the second contact, in order to stop the Direct Current flowing between the first contact and the second contact at least in part.
Semiconductor device the most according to claim 9, wherein said barrier extends at least partially through substrate from the first type surface of described substrate include the groove comprised including electrolyte, wherein said groove.
11. according to the semiconductor device described in aforementioned any one claim, and the most on said principal surface, at least one contact in the plurality of contact at least partly surrounds another contact in the plurality of contact.
12. according to the semiconductor device described in aforementioned any one claim, and wherein said device is that transient voltage suppresses TVS diode.
13. according to the semiconductor device described in any one of claim 1 to 11, wherein:
The plurality of contact includes the 3rd contact；And
Described device includes bipolar transistor, and wherein the first contact is emitter stage contact, and the second contact is collector contact, and the 3rd contact is base stage contact；Or
Described device includes MOS transistor, and wherein the first contact is source contact, and the second contact is drain contact, and the 3rd contact is gate contact.
14., according to the semiconductor device described in aforementioned any one claim, are arranged on carrier surface, and wherein said electrically floating metal level is free of attachment to any external pin of described device.
15. 1 kinds of methods, including:
Semiconductor wafer is provided；
Multiple contact is provided on the major faces of the wafers；
The back of wafer provides the electrically floating metal level forming Ohmic contact, and
By wafer stripping and slicing, to manufacture according to the multiple semiconductor device described in aforementioned any one claim.
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