JP2007142272A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To allow resistance to be smaller by constituting a drain electrode composed of a through-hole electrode penetrating a semiconductor substrate, so as to shorten an electric current route passing through a semiconductor substrate compared with a conventional structure. <P>SOLUTION: A semiconductor device includes an epitaxial layer 2 formed on an n-type semiconductor substrate 1, a p-type impurity diffused layer 3 formed on the epitaxial layer 2, a trench groove 4 formed to have a prescribed depth in the epitaxial layer 2 from the surface layer of the impurity diffused layer 3, a gate electrode 6 formed by embedding a conductive layer in the trench groove 4 via an insulating layer 5, source layers 7 formed on the surface layer of the impurity diffused layer 3 and also in both the sidewalls of the trench groove 4 so as to be adjacent to the insulating layer 5, a drain layer 9 formed to have a through-hole electrode structure in a through-hole 1A which is formed to penetrate the semiconductor substrate 1 from the surface layer of the epitaxial layer 2, and a metallic layer 14 which is formed on the rear surface of the semiconductor substrate 1 and electrically connected to the bottom part of the drain layer 9. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a technology for forming an up drain type MOS transistor having a trench structure.

  A conventional up-drain type MOS transistor having a trench structure has a structure in which a current passes through a semiconductor substrate.

  That is, as shown in FIG. 3, an epitaxial layer 52 is formed on a semiconductor substrate 51 made of, for example, N-type silicon, and a P-type impurity diffusion layer 53 (channel region) is formed on the surface layer of the epitaxial layer 52. A trench groove 54 is formed from the surface layer of the P-type impurity diffusion layer 53 to a predetermined depth position of the epitaxial layer 52. The trench groove 54 is made of a polysilicon film surrounded by an insulating layer 55. A conductive layer is buried and a gate electrode (G) 56 is formed.

  Further, an N + type source layer 57 adjacent to the insulating layer 55 is formed on the surface layer of the epitaxial layer 52 and on both side walls of the trench groove 54, and P + so as to straddle between the adjacent source layers 57. A mold body layer 58 is formed.

  Further, an N-type impurity diffusion layer is formed so as to reach from the surface layer of the epitaxial layer 52 to a predetermined depth position of the semiconductor substrate 51, and an N + type drain layer 59 is configured.

  Further, a metal layer made of, for example, an Al alloy or the like is formed on the epitaxial layer 52 so as to cover the source layer 57 and the drain layer 59, and the source electrode (S) 60 and the drain electrode (D) 61, respectively. Is formed.

A semiconductor device 63 having a metal layer 62 formed on the back surface of the semiconductor substrate 51 is formed.
JP 2004-363302 A

  Here, the up-drain type MOS transistor having the trench structure passes through the source electrode (S) 60, the P-type impurity diffusion layer 53, the epitaxial layer 52, and the semiconductor substrate 51 along the direction of the arrow shown in FIG. Then, the current I <b> 2 flows through the semiconductor substrate 51 again through the metal layer 62 formed on the back surface of the semiconductor substrate 51 and flows through the drain electrode 61.

  At this time, since the high-resistance semiconductor substrate 51 passes twice, the resistance value as a product becomes high.

  Accordingly, the semiconductor device of the present invention includes an epitaxial layer formed on a first conductivity type semiconductor substrate, a second conductivity type impurity diffusion layer formed on the epitaxial layer, and a surface layer of the impurity diffusion layer. A trench groove formed to a predetermined depth position of the layer, a gate electrode in which a conductive layer is embedded in the trench groove via an insulating layer, a surface layer of the impurity diffusion layer, and both side walls of the trench groove A through hole is formed in the portion so as to penetrate the semiconductor substrate from a source layer formed adjacent to the insulating layer and a surface layer of the epitaxial layer, and a through electrode structure is formed in the through hole. And a metal layer formed on the back surface of the semiconductor substrate and electrically connected to the bottom of the drain layer.

  Further, the semiconductor device constitutes a flip chip.

  Further, the through electrode is composed of one or a plurality of through electrodes.

  According to the semiconductor device of the present invention, compared to the conventional drain electrode composed of the impurity diffusion layer, the drain electrode composed of the through electrode penetrating the semiconductor substrate is configured. Since the current path passing through the semiconductor substrate is shortened, the resistance can be reduced.

  Hereinafter, an embodiment according to a semiconductor device of the present invention will be described with reference to the drawings.

  The semiconductor device of the present invention has an up drain type MOS transistor structure to which the through electrode technology is applied.

  First, as shown in FIG. 1, an epitaxial layer 2 is formed on a semiconductor substrate 1 made of one conductivity type, for example, N-type silicon, and a P-type impurity diffusion layer 3 (channel region) is formed on the surface of the epitaxial layer 2. ing.

  In this embodiment, for example, the thickness of the epitaxial layer 2 is 10 μm, the thickness of the semiconductor substrate 1 is 200 μm including the thickness of the epitaxial layer 2, and the thickness of the P-type impurity diffusion layer 3 is 1 to 1.5 μm.

  Further, a trench groove 4 is formed which extends from the surface layer of the P-type impurity diffusion layer 3 to a predetermined depth position of the epitaxial layer 2, and is made of a polysilicon film surrounded by the insulating layer 5 in the trench groove 4. A conductive layer is buried and a gate electrode (G) 6 is formed.

  Here, in the present embodiment, for example, the depth of the trench groove 4 is 2 μm, and the opening diameter of the central portion of the trench groove 4 is 0.4 μm.

  Further, an N-type source layer 7 adjacent to the insulating layer 5 is formed in the epitaxial layer 2 on the surface layer and on both side walls of the trench groove 4, and between the adjacent source layers 7. A P-type body layer 8 is formed so as to straddle.

  A through hole 1A is formed from the surface layer of the epitaxial layer 2 so as to penetrate the semiconductor substrate 1, and a drain layer 9 forming a through electrode structure is formed in the through hole 1A.

  Here, the opening diameter of the central portion of the through hole 1A is, for example, 25 μm to 30 μm, and a barrier metal layer 10 made of, for example, a TiN film or a TiW film is formed in the through hole 1A. A Cu layer 11 is formed on the substrate 10 as a through electrode material via a seed layer (for example, a Cu seed layer) (not shown).

  Further, a metal layer made of, for example, an Al alloy (Al—Si, Al—Si—Cu, Al—Cu) or the like is formed on the epitaxial layer 2 so as to cover the source layer 7 and the drain layer 9, respectively. A source electrode (S) 12 and a drain electrode (D) 13 are formed accordingly.

  A semiconductor device 15 is configured in which a metal layer 14 is formed on the back surface of the semiconductor substrate 1. Accordingly, the bottom of the drain electrode (D) 13 having the through electrode structure is electrically connected to the metal layer 14.

  In this embodiment, for example, a Ti—Ni—Au alloy layer (50 nm-500 nm-50 nm) is used as the metal layer 14, but any other conductive material having a low resistance may be used.

  The up-drain type MOS transistor to which the through electrode technology is applied, which is the semiconductor device 15 of the present invention configured as described above, has the source electrode (S) 12, P-type along the arrow direction shown in FIG. Through the impurity diffusion layer 3, the epitaxial layer 2 and the semiconductor substrate 1, the current I 1 is supplied to the drain electrode (D) 13 forming the through electrode structure via the metal layer 14 formed on the back surface of the semiconductor substrate 1. Flows.

  Therefore, as in the conventional semiconductor device 63, the current that flows through the metal layer 62 through the source electrode (S) 60, the P-type impurity diffusion layer 53, the epitaxial layer 52, and the semiconductor substrate 51 again becomes the semiconductor substrate 51. Compared to a structure in which a current flows through the drain electrode (D) 61, the region of the high-resistance semiconductor substrate through which current flows can be halved, and the resistance value of the product can be reduced (the present invention). The resistance value R1 of the semiconductor device <the resistance value R2 of the conventional semiconductor device).

  As described above, in the semiconductor device of the present invention, the current passes through the semiconductor substrate 51 having a thickness of 200 μm. Therefore, by using one of the current paths as a metal layer made of a through electrode, high-speed current propagation is achieved. Can be achieved.

  Here, in place of the conventional Sb-doped substrate crystal of about 10 to 20 mΩcm, an As-doped substrate crystal realizing a low resistance of about several mΩcm has been used recently. It was an obstacle to resistance reduction.

  Further, in the present invention, since the drain electrode (D) 13 is made of a through electrode in which a metal is buried, compared to the drain layer 59 made of the impurity diffusion layer, the resistance can be reduced. Here, the resistance can be further reduced by increasing the volume of the through electrode. Moreover, the thing of the structure which increases the volume as a whole by forming a some penetration electrode may be used.

  With the semiconductor device having such a structure, a low-resistance flip chip can be realized.

  That is, FIG. 2 is a plan view of a flip chip adopting the present invention. In FIG. 2, the upper left bump electrode 16 is for the gate electrode, the lower left bump electrode 17 is for the source electrode (S), and the right side. The upper and lower bump electrodes 18 are for the drain electrode. It should be noted that a plurality of bump electrodes may be formed as long as the flatness of the plip chip is not hindered.

It is sectional drawing which shows the semiconductor device which concerns on embodiment of this invention. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention. It is sectional drawing which shows the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1A Through-hole 2 Epitaxial layer 3 P-type impurity diffusion layer (channel region)
4 Trench groove 5 Insulating layer 6 Gate electrode (G)
7 Source layer 8 Body layer 9 Drain layer 10 Barrier metal layer 11 Cu layer 12 Source electrode (S)
13 Drain electrode (D)
14 Metal layer 15 Semiconductor device

Claims (4)

In the up-drain type semiconductor device, a semiconductor device comprising a through electrode that is electrically connected to a metal layer formed on a back surface of a semiconductor substrate and forms a drain electrode. An epitaxial layer formed on the first conductivity type semiconductor substrate, a second conductivity type impurity diffusion layer formed on the epitaxial layer, and a surface layer of the impurity diffusion layer to a predetermined depth position of the epitaxial layer. A trench electrode, a gate electrode in which a conductive layer is embedded in the trench groove via an insulating layer, a surface layer of the impurity diffusion layer, and adjacent to the insulating layer on both side walls of the trench groove A source layer formed, a drain hole formed so as to penetrate the semiconductor substrate from a surface layer of the epitaxial layer, and a drain layer formed so as to form a through electrode structure in the through hole; and the semiconductor substrate A semiconductor device comprising a metal layer formed on the back surface of the drain layer and electrically connected to the bottom of the drain layer. The semiconductor device according to claim 1, wherein the semiconductor device forms a flip chip. The semiconductor device according to claim 1, wherein the through electrode includes one or a plurality of through electrodes.