JP2010087096A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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JP2010087096A
JP2010087096A JP2008252541A JP2008252541A JP2010087096A JP 2010087096 A JP2010087096 A JP 2010087096A JP 2008252541 A JP2008252541 A JP 2008252541A JP 2008252541 A JP2008252541 A JP 2008252541A JP 2010087096 A JP2010087096 A JP 2010087096A
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electrode
semiconductor device
drain
semiconductor substrate
layer
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Tetsuya Yoshida
哲哉 吉田
Takuji Miyata
拓司 宮田
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Sanyo Electric Co Ltd
System Solutions Co Ltd
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Sanyo Electric Co Ltd
Sanyo Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To realize a highly efficient and high performance semiconductor device by reducing electric resistance across a current path in longitudinal direction and lateral direction in the semiconductor device where current continuously flows in longitudinal direction, lateral direction, and longitudinal direction. <P>SOLUTION: In the semiconductor device, two MOS structures which share a drain are formed in the front surface side of the semiconductor substrate, and a plurality of ditch-like opening parts 4 are formed to extend from the drain region of one MOS structure to the drain region of the other MOS structure in the interior of an N+ type drain layer 7 in the back surface side of the semiconductor substrate. The ditch-like opening parts 4 are formed deeply up to the proximity of the boundary between the N+ type drain layer 7 and an N- type epitaxial layer 8, in the interior of the N+ type drain layer 7. A metal electrode 6, which is electrically connected to a back electrode 5 and has resistance lower than that of the N+ type drain layer 7, is formed in the ditch-like opening 4. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体装置及びその製造方法に関し、特に、半導体基板の縦方向及び横方向に電流を流すＭＯＳ型半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a MOS type semiconductor device that allows current to flow in a vertical direction and a horizontal direction of a semiconductor substrate and a manufacturing method thereof.

半導体基板内を縦方向、横方向、そして縦方向と連続的に電流が流れるＭＯＳ型半導体装置が存在する。その第１の例として、携帯電話等に使用されるリチューム電池の充放電時の保護回路として、図１５に示すような、ドレインを共有する２つのＭＯＳ型ＦＥＴで構成される半導体装置１０２が挙げられる。図１５における、当該半導体装置１０２の動作を簡単に説明する。図１５の左向きの矢印は、リチューム電池１０１が充電する場合の電流の流れる方向である。また、右向きの矢印は、リチューム電池１０１が放電する、即ち、携帯電話を使用しているときの電流の流れを示している。充電時は放電用ＦＥＴ（Ｄ・ＦＥＴ）１０３側の寄生ダイオード１０３ａが順方向に、充電用ＦＥＴ（Ｃ・ＦＥＴ）１０４の寄生ダイオード１０４ａが逆方向にバイアスされるので、充電用ＦＥＴ（Ｃ・ＦＥＴ）１０４がオンしない限り、このままでは電流は流れない。   There is a MOS type semiconductor device in which a current flows continuously in a vertical direction, a horizontal direction, and a vertical direction in a semiconductor substrate. As a first example, as a protection circuit at the time of charging / discharging a rechargeable battery used in a mobile phone or the like, a semiconductor device 102 composed of two MOS FETs sharing a drain as shown in FIG. It is done. The operation of the semiconductor device 102 in FIG. 15 will be briefly described. The left-pointing arrow in FIG. 15 indicates the direction of current flow when the lithium battery 101 is charged. The right-pointing arrow indicates the current flow when the lithium battery 101 is discharged, that is, when the mobile phone is used. During charging, the parasitic diode 103a on the discharging FET (D • FET) 103 side is biased in the forward direction, and the parasitic diode 104a of the charging FET (C • FET) 104 is biased in the reverse direction. As long as the (FET) 104 is not turned on, no current flows as it is.

この場合、コントロール用デバイス１０５がリチューム電池１０１の電圧を感知しＣ・ＦＥＴ１０４のゲートに電圧を印加し、Ｃ・ＦＥＴ１０４をオンすることにより、図１５の左向き矢印の方向へ充電電流が流れ、リチューム電池１０１は充電される。リチューム電池１０１が、所定の電圧まで充電されたのを感知し、コントロール用デバイス１０５はＣ・ＦＥＴ１０４のゲート信号をオフにして、Ｄ・ＦＥＴ１０３側のゲートに電圧を印加し、Ｄ・ＦＥＴ１０３をオンにする。この場合Ｃ・ＦＥＴ１０４はオフだが寄生ダイオード１０４ａは順方向になるため、図１５の右向きの放電回路が確保される。   In this case, the control device 105 senses the voltage of the rechargeable battery 101, applies a voltage to the gate of the C • FET 104, and turns on the C • FET 104, whereby a charging current flows in the direction of the left arrow in FIG. The battery 101 is charged. The control device 105 detects that the rechargeable battery 101 has been charged to a predetermined voltage, turns off the gate signal of the C • FET 104, applies a voltage to the gate on the D • FET 103 side, and turns on the D • FET 103. To. In this case, since the C • FET 104 is off but the parasitic diode 104a is in the forward direction, a discharge circuit directed to the right in FIG. 15 is secured.

それでは係る保護回路に使用される、ドレインを共有するＭＯＳ型ＦＥＴを２個含む半導体装置１０２にかかる半導体チップについて、図１６にその表面から見た平面図を、図１７にその裏面図を、また図１８に図１７のＡ−Ａ間による断面図を示す。図１６には、半導体基板の表面側に、Ｓ１で表示されるソースバンプ電極１０６とＧ１で表示されるゲートバンプ電極１０７を含むＭＯＳ構造と、Ｓ２で表示されるソースバンプ電極１０６とＧ２で表示されるゲートバンプ電極１０７とを含むＭＯＳ構造とからなる、２つのＭＯＳ構造が形成されているのが示される。また、図１７、図１８から、それぞれのＭＯＳ構造に対して８つのビアホール１０８が、半導体基板の裏面からＮ＋型ドレイン層１０９の中に、Ｎ＋型ドレイン層１０９とＮ−型エピ層１１０の境界近くまで、形成されているのが示される。Ｓ１、Ｓ２、Ｇ１、Ｇ２はハンダバンプであり、当該チップは、Ｆｌｉｐ Ｃｈｉｐを構成している。なお、図１７における点線で示すＳ１等は、裏面から透視してみたハンダバンプを点線で表している。   FIG. 16 is a plan view seen from the front surface of the semiconductor chip used in the protection circuit and the semiconductor device 102 of the semiconductor device 102 including two MOS FETs sharing the drain, and FIG. 18 is a cross-sectional view taken along the line AA in FIG. FIG. 16 shows a MOS structure including a source bump electrode 106 indicated by S1 and a gate bump electrode 107 indicated by G1, and a source bump electrode 106 indicated by S2 and G2 on the surface side of the semiconductor substrate. It is shown that two MOS structures composed of a MOS structure including a gate bump electrode 107 to be formed are formed. 17 and 18, eight via holes 108 for each MOS structure are formed in the N + type drain layer 109 from the back surface of the semiconductor substrate, and the boundary between the N + type drain layer 109 and the N − type epi layer 110. It is shown that it has been formed. S1, S2, G1, and G2 are solder bumps, and the chip constitutes a flip chip. In addition, S1 etc. shown with the dotted line in FIG. 17 represent the solder bump seen through from the back surface with the dotted line.

図１８に示されるように、２つのＦＥＴは、ドレインを共通にした縦型ＭＯＳＦＥＴを構成している。また、基板の縦方向に、Ｐ＋型ボディ層１１２、Ｐ型チャネル層１１１からなるＰ型半導体層とＮ−型エピ層１１０、Ｎ＋型ドレイン層１０９からなるＮ型半導体層により、図１５に示す、寄生ダイオード１０３ａ、１０４ａが形成されている。かかる半導体チップ内の、電流の流れについて以下に記す。例えば、前述の保護回路で、充電動作が行われている場合を考えてみる。この場合、図１５の右側のＣ・ＦＥＴ１０４がオンするようにゲートに電圧が印加され、左側のＤ・ＦＥＴ１０３はその寄生ダイオード１０３ａが順方向であり充電電流が流れる。これを図１８で、ソースバンプ電極Ｓ１がリチューム電池１０１の負電極側に接続されているとして考えると、矢印で示すように、ソースバンプ電極Ｓ２側のＦＥＴ（Ｃ・ＦＥＴ１０４に相当）がオンし、Ｎ＋型ドレイン層１０９からＮ−型エピ層１１０、Ｐ型チャネル層１１１を経由し、Ｎ＋型ソース層１１３に向かって、下から上に縦方向の電流が流れる。ソースバンプ電極Ｓ１側のＦＥＴ（Ｄ・ＦＥＴ１０３に相当）はオフ状態であるが、Ｐ＋型ボディ層１１２、Ｐ型チャネル層１１１とＮ−型エピ層１１０、Ｎ＋型ドレイン層１０９からなる寄生ダイオードが順方向となるため、矢印で示すように、其のルートを辿って上から下へ縦方向の電流が流れる。   As shown in FIG. 18, the two FETs constitute a vertical MOSFET having a common drain. Further, in the vertical direction of the substrate, a P-type semiconductor layer composed of a P + type body layer 112 and a P-type channel layer 111 and an N-type semiconductor layer composed of an N− type epi layer 110 and an N + type drain layer 109 are shown in FIG. Parasitic diodes 103a and 104a are formed. The current flow in the semiconductor chip will be described below. For example, consider a case where a charging operation is performed in the above-described protection circuit. In this case, a voltage is applied to the gate so that the right C • FET 104 in FIG. 15 is turned on, and the parasitic diode 103a is forward in the left D • FET 103, and a charging current flows. Assuming that the source bump electrode S1 is connected to the negative electrode side of the lithium battery 101 in FIG. 18, the FET on the source bump electrode S2 side (corresponding to C • FET104) is turned on as shown by the arrow. A vertical current flows from the N + type drain layer 109 through the N− type epi layer 110 and the P type channel layer 111 toward the N + type source layer 113 from the bottom to the top. Although the FET on the source bump electrode S1 side (corresponding to D · FET 103) is in an OFF state, a parasitic diode comprising a P + type body layer 112, a P type channel layer 111, an N− type epi layer 110, and an N + type drain layer 109 is present. Since it is in the forward direction, as indicated by the arrow, a vertical current flows from the top to the bottom following the route.

即ち、図１８の矢印で示すように、ソースバンプ電極Ｓ１側の寄生ダイオードを経由して縦方向にドレインに流れ込む電流が、共通ドレインを横方向に流れ、ソースバンプ電極Ｓ２側の、オンしているＦＥＴのチャネル層を縦方向に流れ、Ｓ１からＳ２に通じる電流経路を形成する。この場合、バンプＳ１側の寄生ダイオード１０３ａを経由して、縦方向にドレインに流れ込む電流は、Ｎ＋型ドレイン層１０９より抵抗の小さな、ビアホール１０８内に形成された金属電極１１４を経由して、裏面電極１１５に流れ、次に裏面電極１１５内を横方向に流れてから、隣のＦＥＴのビアホール１０８に形成された、金属電極１１４を縦方向に流れ、チャネル層を経由して、当該ＦＥＴのＮ＋型ソース層１１３に流れ込む。従来のように、ビアホール１０８が形成されず、電流がＮ＋型ドレイン層１０９を経由して流れざるを得なかった場合に比し、ビアホール１０８を形成し、ビアホール１０８内と裏面電極１１５を、電気的に接続する金属電極１１４を形成することにより、かかる電流経路の抵抗は大きく減少した。   That is, as indicated by an arrow in FIG. 18, the current flowing into the drain in the vertical direction via the parasitic diode on the source bump electrode S1 flows in the horizontal direction on the common drain and is turned on on the source bump electrode S2 side. A current path that flows from S1 to S2 is formed by flowing in the channel layer of the FET in the vertical direction. In this case, the current flowing into the drain in the vertical direction via the parasitic diode 103a on the bump S1 side passes through the metal electrode 114 formed in the via hole 108, which has a smaller resistance than the N + type drain layer 109, and the back surface. After flowing through the electrode 115 and then through the back electrode 115 in the horizontal direction, the metal electrode 114 formed in the via hole 108 of the adjacent FET flows in the vertical direction and passes through the channel layer, and the N + It flows into the mold source layer 113. Compared to the case where the via hole 108 is not formed and the current has to flow through the N + type drain layer 109 as in the conventional case, the via hole 108 is formed, and the inside of the via hole 108 and the back electrode 115 are electrically connected. By forming the electrically connected metal electrode 114, the resistance of the current path is greatly reduced.

半導体基板内を縦方向、横方向、次に縦方向と連続的に電流が流れる、第２の例として、パワー系の縦型ＭＯＳＦＥＴであって、Ｆｌｉｐ Ｃｈｉｐ用として、ドレイン電極を半導体基板の表面から取り出す半導体装置がある。図１９により、第１の例と同一の構成については、同一の符号を使用して説明する。この場合も、ドレイン層の抵抗を低減するためビアホール１０８が、半導体基板の裏面から、Ｎ＋型ドレイン層１０９とＮ−型エピ層１１０の境界近くまでの、Ｎ＋型ドレイン層１０９内に形成される。したがって、矢印で示すように、電流はＮ＋型ソース層１１３から、Ｐ型チャネル層１１１に形成されたＮ型チャネル層を通り、ビアホール１０８内の金属電極１１４を、縦方向に裏面電極１１５まで流れる。次に裏面電極１１５内を横方向に、半導体基板の表面にドレイン導出電極１１６が形成された、直下のビアホール１０８部分まで流れる。最後に当該ビアホール１０８を経由して、ドレイン導出電極１１６に向かう、縦方向の電流が流れる。なお、ドレイン導出電極１１６の直下のビアホール１０８は、通常Ｎ―型エピ層１１０内部まで形成される。   As a second example in which a current flows continuously in a vertical direction, a horizontal direction, and then a vertical direction in a semiconductor substrate, a power-type vertical MOSFET is used for a flip chip, and a drain electrode is provided on the surface of the semiconductor substrate. There is a semiconductor device to be taken out from. 19, the same components as those in the first example will be described using the same symbols. Also in this case, a via hole 108 is formed in the N + type drain layer 109 from the back surface of the semiconductor substrate to near the boundary between the N + type drain layer 109 and the N − type epi layer 110 in order to reduce the resistance of the drain layer. . Therefore, as indicated by an arrow, current flows from the N + type source layer 113 through the N type channel layer formed in the P type channel layer 111, and flows in the vertical direction to the back electrode 115 through the metal electrode 114 in the via hole 108. . Next, it flows in the back surface electrode 115 in the horizontal direction to the portion of the via hole 108 immediately below where the drain lead electrode 116 is formed on the surface of the semiconductor substrate. Finally, a vertical current flows toward the drain lead electrode 116 through the via hole 108. The via hole 108 immediately below the drain lead-out electrode 116 is usually formed up to the inside of the N − type epi layer 110.

このように、半導体基板の裏面側にビアホール１０８を形成し、裏面電極１１５と電気的に接続することにより、縦型ＭＯＳＦＥＴのドレイン抵抗を低下させることについては、以下の特許文献に記載されている。
特開２００８−６６６９４号公報 Thus, the following patent document describes that the drain resistance of the vertical MOSFET is reduced by forming the via hole 108 on the back surface side of the semiconductor substrate and electrically connecting it to the back surface electrode 115. .
JP 2008-66694 A

前述の電流が縦方向、横方向、次に縦方向と連続して流れる半導体装置において、縦方向に流れる電流に対する抵抗は、半導体基板の裏面にビアホールを形成し、ビアホール内壁に、裏面電極と電気的に接続された金属電極を形成することにより、ビアホールが形成されない場合に比して大きく低減した。しかし、なお、ビアホール内から裏面電極にいたる、金属電極の抵抗は存在する。また、裏面電極内を横方向に流れる電流に対する裏面電極の抵抗は、半導体チップを小型化、即ち、縦横一定比率でシュリンクした場合も、裏面電極の比抵抗や厚みで決まる値をそのまま維持する。したがって、縦方向、横方向、次に縦方向と連続して流れる電流経路の電気抵抗を、更に低下させる事が可能な、高効率、高性能な半導体装置の開発が課題となる。   In the semiconductor device in which the current flows continuously in the vertical direction, the horizontal direction, and then in the vertical direction, the resistance to the current flowing in the vertical direction is that a via hole is formed on the back surface of the semiconductor substrate, and the back electrode is electrically connected to the inner wall of the via hole. By forming the electrically connected metal electrode, it was greatly reduced as compared with the case where the via hole was not formed. However, there is still a resistance of the metal electrode from the via hole to the back electrode. Further, the resistance of the back surface electrode against the current flowing in the lateral direction in the back surface electrode maintains the value determined by the specific resistance and thickness of the back surface electrode even when the semiconductor chip is downsized, that is, when the semiconductor chip is shrunk at a constant vertical and horizontal ratio. Therefore, it is an object to develop a highly efficient and high performance semiconductor device capable of further reducing the electrical resistance of a current path that flows continuously in the vertical direction, the horizontal direction, and then in the vertical direction.

本発明の半導体装置は、半導体基板の表面側に形成されたドレインを共有する２つのＭＯＳ構造と、前記半導体基板の裏面側に前記ＭＯＳ構造の一方のドレイン領域から、前記ＭＯＳ構造の他方の前記ドレイン領域まで延在して形成された堀状の開口部と、前記堀状の開口部の中に形成された金属電極と、前記金属電極と電気的に接続された裏面電極と、を備えることを特徴とする。   The semiconductor device of the present invention includes two MOS structures sharing a drain formed on the front surface side of a semiconductor substrate, and one drain region of the MOS structure on the back surface side of the semiconductor substrate, and the other of the MOS structure. A trench-shaped opening formed extending to the drain region, a metal electrode formed in the trench-shaped opening, and a back electrode electrically connected to the metal electrode. It is characterized by.

また、本発明の半導体装置は、半導体基板の表面にドレイン領域から電流を導出するために形成されたドレイン導出端子と、前記半導体基板の裏面にソース領域の下方の前記ドレイン領域から前記ドレイン導出端子の下方の領域まで延在して形成された堀状の開口部と、前記堀状の開口部の中に形成された金属電極と、前記金属電極と電気的に接続された裏面電極と、を備えることを特徴とする。   According to another aspect of the present invention, there is provided a semiconductor device including a drain lead terminal formed on the surface of a semiconductor substrate for leading current from the drain region, and a drain lead terminal from the drain region below the source region on the back surface of the semiconductor substrate. A moat-shaped opening formed to extend to a region below, a metal electrode formed in the moat-shaped opening, and a back electrode electrically connected to the metal electrode, It is characterized by providing.

更に、本発明の半導体装置は、前記半導体基板が第１導電型であり、前記ＭＯＳ構造は、前記半導体基板の表面側に形成された第２導電型のチャネル層と、複数のゲート絶縁膜及びゲート電極と、前記ゲート絶縁膜に隣接して形成された第１導電型のソース層と、前記ソース層と電気的に接続して形成されたソース電極と、前記ソース層に挟まれ、前記半導体基板の表面から前記チャネル層の内部まで延在して形成された第２導電型のボディ層と、を備え、前記内壁はドレインとして機能し、前記金属電極及び前記裏面電極はドレイン電極であることを特徴とする。   Furthermore, in the semiconductor device of the present invention, the semiconductor substrate is of a first conductivity type, and the MOS structure has a second conductivity type channel layer formed on the surface side of the semiconductor substrate, a plurality of gate insulating films, A gate electrode; a source layer of a first conductivity type formed adjacent to the gate insulating film; a source electrode formed in electrical connection with the source layer; and the semiconductor layer sandwiched between the source layers A body layer of a second conductivity type formed extending from the surface of the substrate to the inside of the channel layer, the inner wall functions as a drain, and the metal electrode and the back electrode are drain electrodes It is characterized by.

また、本発明の半導体装置の製造方法は、半導体基板の表面側にドレインを共有する２つのＭＯＳ構造を形成する工程と、前記半導体基板の裏面側に前記ＭＯＳ構造の一方の前記ドレイン領域から、前記ＭＯＳ構造の他方の前記ドレイン領域まで延在する堀状の開口部を形成する工程と、前記堀状の開口部の中に金属電極を形成する工程と、前記金属電極と電気的に接続する裏面電極を形成する工程と、を含むことを特徴とする。   The method for manufacturing a semiconductor device according to the present invention includes a step of forming two MOS structures sharing a drain on the front surface side of a semiconductor substrate, and from one drain region of the MOS structure on the back surface side of the semiconductor substrate, Forming a trench-shaped opening extending to the other drain region of the MOS structure; forming a metal electrode in the trench-shaped opening; and electrically connecting to the metal electrode Forming a back electrode.

更に、本発明の半導体装置の製造方法は、半導体基板の表面にドレイン領域から電流を導出するためのドレイン導出端子を形成する工程と、前記半導体基板の裏面側にソースの下方のドレイン領域から前記ドレイン導出端子の下方まで延在する堀状の開口部を形成する工程と、前記堀状の開口部の中に金属電極を形成する工程と、前記金属電極と電気的に接続する裏面電極を形成する工程と、を含むことを特徴とする。   Furthermore, the method of manufacturing a semiconductor device according to the present invention includes a step of forming a drain lead terminal for leading current from the drain region on the surface of the semiconductor substrate, and the drain region below the source on the back side of the semiconductor substrate. Forming a trench-shaped opening extending below the drain lead-out terminal; forming a metal electrode in the trench-shaped opening; and forming a back electrode electrically connected to the metal electrode And a step of performing.

本発明の半導体装置の製造方法によれば、半導体基板の表面から縦方向、横方向、そして最後に、また、縦方向に連続して流れる電流経路の電気抵抗を低減する事が可能となり、高性能な半導体装置を製造する事ができる。   According to the method for manufacturing a semiconductor device of the present invention, it is possible to reduce the electrical resistance of a current path continuously flowing in the vertical direction, the horizontal direction, and finally the vertical direction from the surface of the semiconductor substrate. A high performance semiconductor device can be manufactured.

以下、本発明に係る半導体装置の製造方法について、図面を参照しながら詳細に説明する。初めに、図１〜図３において、本発明に係る、第１の実施形態についての半導体装置の特徴について、詳細に説明する。図１は本発明の第１の実施形態における半導体チップの平面図である。また、図２はその裏面図である。図３は、図２のＡ−Ａ間の断面図である。図１は、従来例と同様、半導体基板の表面に、Ｓ１で表示するソースバンプ電極１とＧ１で表示するゲートバンプ電極２からなるＭＯＳ構造と、Ｓ２で表示するソースバンプ電極１とＧ２で表示するゲートバンプ電極２とからなるＭＯＳ構造が形成されているのを示している。   Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to the drawings. First, the characteristics of the semiconductor device according to the first embodiment of the present invention will be described in detail with reference to FIGS. FIG. 1 is a plan view of a semiconductor chip according to the first embodiment of the present invention. FIG. 2 is a rear view thereof. 3 is a cross-sectional view taken along a line AA in FIG. FIG. 1 shows a MOS structure composed of a source bump electrode 1 indicated by S1 and a gate bump electrode 2 indicated by G1, and a source bump electrode 1 and G2 indicated by S2 on the surface of the semiconductor substrate as in the conventional example. It is shown that a MOS structure composed of the gate bump electrode 2 is formed.

周辺はゲート配線電極３がソース領域を取り囲み、内部のゲート電極１３と不図示の配線で接続されている。図２は、半導体基板の裏面に、両方のＭＯＳ型ＦＥＴの共通のドレイン領域を跨って、４本の堀状の開口部４が形成され、裏面電極５と堀状の開口部４の内壁に形成された金属電極６とが、電気的に接続されている状態を示す。図２の点線で示す丸印は、半導体基板の表側に形成された、ソースバンプ電極１並びにゲートバンプ電極２を裏面側から透視した状態を示している。なお、図２に示す、堀状の開口部４の本数は例示であり、４本に制限されるものでない。   In the periphery, the gate wiring electrode 3 surrounds the source region and is connected to the internal gate electrode 13 by a wiring (not shown). In FIG. 2, four moat-shaped openings 4 are formed on the back surface of the semiconductor substrate across the common drain region of both MOS FETs, and the inner surface of the back electrode 5 and the moat-shaped opening 4 is formed. A state in which the formed metal electrode 6 is electrically connected is shown. 2 indicate a state in which the source bump electrode 1 and the gate bump electrode 2 formed on the front side of the semiconductor substrate are seen through from the back side. In addition, the number of the moat-shaped openings 4 shown in FIG. 2 is an example, and is not limited to four.

図３は、それぞれのＭＯＳ構造が、どのように形成されているかを示している。Ｎ＋型ドレイン層７の上にＮ−型エピ層８が形成され、Ｎ−型エピ層８の中には酸化膜９を介して、Ｐ型チャネル層１０が形成されている。さらに、Ｐ型チャネル層１０の表面からＰ型チャネル層１０を貫通し、Ｎ−型エピ層８に至る複数のトレンチ１１が形成され、その内壁にゲート絶縁膜１２、その内部を充填するにゲート電極１３が形成される。図３において、４個のトレンチ１１が形成されているが、その個数は必要に応じ、増減される。トレンチ１１の内壁に形成されたゲート絶縁膜１２に隣接して、Ｎ＋型ソース層１４が、またＮ＋型ソース層１４とＮ＋型ソース層１４の間にＰ＋型ボディ層１５が形成される。   FIG. 3 shows how each MOS structure is formed. An N− type epi layer 8 is formed on the N + type drain layer 7, and a P type channel layer 10 is formed in the N− type epi layer 8 via an oxide film 9. Further, a plurality of trenches 11 penetrating from the surface of the P-type channel layer 10 through the P-type channel layer 10 to the N − -type epi layer 8 are formed, and a gate insulating film 12 is filled on the inner wall of the trench 11 and the gate is filled therein Electrode 13 is formed. In FIG. 3, four trenches 11 are formed, but the number thereof is increased or decreased as necessary. An N + type source layer 14 is formed adjacent to the gate insulating film 12 formed on the inner wall of the trench 11, and a P + type body layer 15 is formed between the N + type source layer 14 and the N + type source layer 14.

トレンチ１１内を充填するゲート電極１３の表面は、層間絶縁膜１６で覆われ、その上にソース電極１７が形成される。その上部に、窒化膜１８、ポリイミド膜１９が形成され、ソース電極１７と接続されたＵＢＭ（アンダー バンプ メタル）２０を介して、ハンダ等からなる、バンプ電極１が形成される。ＵＢＭ２０は、Ｎｉ／Ａｕ等が積層されて形成される。また、半導体基板の裏面側には、Ｎ＋型ドレイン層７内に、Ｎ＋型ドレイン層７とＮ−型エピ層８の界面近傍まで到達する堀状の開口部４が、一方のＭＯＳＦＥＴのドレイン領域から他方のＭＯＳＦＥＴのドレイン領域まで延在して形成される。また、堀状の開口部４の内壁には、裏面電極５と電気的に接続された金属電極６が形成される。   The surface of the gate electrode 13 filling the trench 11 is covered with an interlayer insulating film 16, and the source electrode 17 is formed thereon. A nitride film 18 and a polyimide film 19 are formed thereon, and a bump electrode 1 made of solder or the like is formed through a UBM (under bump metal) 20 connected to the source electrode 17. The UBM 20 is formed by stacking Ni / Au or the like. Further, on the back side of the semiconductor substrate, a trench-like opening 4 reaching the vicinity of the interface between the N + type drain layer 7 and the N− type epi layer 8 is formed in the N + type drain layer 7. To the drain region of the other MOSFET. A metal electrode 6 electrically connected to the back electrode 5 is formed on the inner wall of the moat-shaped opening 4.

図３に、本発明の第１の実施形態における半導体装置の、電流の流れを矢印で示す。ソースバンプ電極Ｓ１が、図１５に示す回路のリチューム電池１０１の負電極側に接続されている場合を考える。図１５において、充電状態の場合は、前述の如くソースバンプ電極Ｓ１側のＰ型チャネル層１０とＮ−型エピ層８で形成される、寄生ダイオード１０３ａは順方向となる。そのため、順方向電流が、Ｐ＋型ボディ層１５、Ｐ型チャネル層１０から、Ｎ−型エピ層８を通る矢印方向の縦方向電流として、Ｎ＋型ドレイン層７に流れこむ。この場合、大部分はＮ＋型ドレイン層７より抵抗の低い、堀状の開口部４内に形成された金属電極６内に流れ込む。   In FIG. 3, the current flow of the semiconductor device according to the first embodiment of the present invention is indicated by arrows. Consider the case where the source bump electrode S1 is connected to the negative electrode side of the rechargeable battery 101 in the circuit shown in FIG. In FIG. 15, in the charged state, the parasitic diode 103a formed by the P-type channel layer 10 and the N− type epi layer 8 on the source bump electrode S1 side as described above is in the forward direction. Therefore, a forward current flows from the P + type body layer 15 and the P type channel layer 10 into the N + type drain layer 7 as a vertical current passing through the N − type epi layer 8 in the arrow direction. In this case, most of the metal flows into the metal electrode 6 formed in the trench-shaped opening 4 having a lower resistance than that of the N + type drain layer 7.

堀状の開口部４に流れ込んだ電流の大部分は、堀状の開口部４内壁に形成された金属電極６内を電気的な最短経路を経由しつつ、ゲートに信号が印加され、オン状態にあるソースバンプ電極Ｓ２側のＭＯＳ構造のドレイン領域に向かう、矢印で示す横方向の電流となる。すなわち、本発明に係る半導体装置では図３に矢印で示す様に、堀状の開口部４内に形成された金属電極６内を、Ｎ−型エピ層８に近い領域ほど沢山の横方向の電流が流れる。したがって、裏面電極５の電流経路としての役目は、相対的に小さなものになる。   Most of the current flowing into the moat-shaped opening 4 is applied to the gate through the shortest electrical path through the metal electrode 6 formed on the inner wall of the moat-shaped opening 4, and is turned on. The current in the horizontal direction indicated by the arrow toward the drain region of the MOS structure on the source bump electrode S2 side in FIG. That is, in the semiconductor device according to the present invention, as indicated by an arrow in FIG. 3, in the metal electrode 6 formed in the moat-shaped opening 4, the region closer to the N− type epilayer 8 has more lateral directions. Current flows. Therefore, the role of the back electrode 5 as a current path is relatively small.

それに対して、従来構造では、図１８の矢印で示すように、先ず、ソースバンプ電極Ｓ１側のＰ＋型ボディ層１１２、Ｐ型チャネル層１１１から、Ｎ−型エピ層１１０へ向かい、図１５に示す寄生ダイオード１０３ａを通る順方向電流として、Ｎ＋型ドレイン層１０９に縦方向電流が流れこむ。縦方向電流は、大半が低抵抗のビアホール１０８内の金属電極１１４を経由して裏面電極１１５に流れ込む。その後、裏面電極１１５を横方向に流れる。
裏面電極は大半の横方向電流の電流経路としての大きな役割を占めている。 On the other hand, in the conventional structure, as indicated by an arrow in FIG. 18, first, from the P + type body layer 112 and the P type channel layer 111 on the source bump electrode S1 side toward the N− type epi layer 110, FIG. As a forward current passing through the parasitic diode 103a shown, a vertical current flows into the N + type drain layer 109. Most of the vertical current flows into the back electrode 115 via the metal electrode 114 in the low resistance via hole 108. Then, the back electrode 115 flows in the horizontal direction.
The back electrode occupies a large role as a current path for most lateral currents.

即ち、本発明においては、堀状の開口部４内の金属電極６の上部を、より多くの電流が流れることになるため、従来のビアホール構造の場合に比して堀状の開口部４を上から下に流れる電流の比率が小さくなり、当該縦方向の抵抗はビアホール構造に比し低減する。   That is, in the present invention, more current flows through the upper portion of the metal electrode 6 in the trench-shaped opening 4, so that the trench-shaped opening 4 is formed as compared with the conventional via hole structure. The ratio of current flowing from top to bottom is reduced, and the vertical resistance is reduced as compared to the via hole structure.

次に、横方向に流れる電流に対する抵抗について考察する。横方向の抵抗は、図１８に示す従来構造では、裏面電極１１５の抵抗がそれに相当する。本発明においては堀状の開口部４に形成された金属電極６の側面の抵抗が相当する。堀状の開口部４は、溝幅が数十μ〜２００μ程度で形成されることから、半導体基板の裏面側に、複数本形成する事ができる。その結果、横方向抵抗を所定の抵抗値以下にする事ができる。例えば、チップサイズをａ×ａ、裏面電極５の厚さをｔ、比抵抗をρ、堀状の開口部４の堀の深さを２００μｍ、堀状の開口部４の堀の本数をＸ、堀状の開口部４内の金属電極６の厚さを裏面電極５の厚さと同じｔとした場合、裏面電極５の抵抗Ｒ１と開口部４側壁の金属電極６の抵抗Ｒ２は略、それぞれ以下の様に表すことができる。   Next, the resistance to the current flowing in the lateral direction will be considered. The resistance in the lateral direction corresponds to the resistance of the back electrode 115 in the conventional structure shown in FIG. In the present invention, the resistance of the side surface of the metal electrode 6 formed in the moat-shaped opening 4 corresponds. Since the trench-shaped opening 4 is formed with a groove width of about several tens of μm to 200 μm, a plurality of the trench-shaped openings 4 can be formed on the back surface side of the semiconductor substrate. As a result, the lateral resistance can be reduced to a predetermined resistance value or less. For example, the chip size is a × a, the thickness of the back electrode 5 is t, the specific resistance is ρ, the depth of the trench 4 is 200 μm, the number of trenches of the trench 4 is X, When the thickness of the metal electrode 6 in the moat-shaped opening 4 is the same as the thickness of the back electrode 5, the resistance R1 of the back electrode 5 and the resistance R2 of the metal electrode 6 on the side wall of the opening 4 are substantially the following. It can be expressed as

この場合、横方向電流が流れる堀状の開口部４の側壁の枚数は、１の開口部当たり２枚で、開口部の個数がＸなので、合計２Ｘ枚となる。したがって、Ｒ１＝ａρ／（ａｔ）＝ρ／ｔであり、Ｒ２＝ａρ／（４００ｔＸ）となる。堀状の開口部４内には、２００×２Ｘの幅で、厚みｔ、長さａの金属板が形成されていることと等価だからである。裏面電極５の抵抗Ｒ１より開口部４内の金属電極６の抵抗Ｒ２を小さくするためには、Ｒ２＜Ｒ１からＸ＞ａ／４００となる。仮に、チップサイズが２ｍｍ×２ｍｍの場合、即ち、ａ＝２０００μｍの場合は、堀状の開口部４の本数ＸをＸ＞５本以上形成すれば、堀状の開口部４内の金属電極６の抵抗値を、裏面電極５の抵抗値よりも小さくできる。   In this case, the number of side walls of the moat-shaped opening 4 through which the lateral current flows is two per opening and the number of openings is X, so the total is 2X. Therefore, R1 = aρ / (at) = ρ / t, and R2 = aρ / (400 tX). This is because a metal plate having a width of 200 × 2 ×, a thickness t and a length a is formed in the moat-shaped opening 4. In order to make the resistance R2 of the metal electrode 6 in the opening 4 smaller than the resistance R1 of the back electrode 5, R2 <R1 to X> a / 400. If the chip size is 2 mm × 2 mm, that is, if a = 2000 μm, if the number X of the trench-shaped openings 4 is X> 5 or more, the metal electrodes 6 in the trench-shaped openings 4 are formed. Can be made smaller than the resistance value of the back electrode 5.

２００μｍ幅の堀状の開口部４を５個形成したとしても、全体の溝幅は合わせても１０００μｍであり、チップサイズ長２０００μｍに対して充分な余裕を持って、堀状の開口部４が形成できる。堀状の開口部４の幅を１００μｍにすれば、Ｘを１０本にしても、チップサイズに対する余裕は充分取れ、堀状の開口部４の抵抗Ｒ２＝（２０００／４０００）（ρ／ｔ）＝（Ｒ１）／２となり、堀状の開口部４の金属電極６の抵抗Ｒ２の抵抗値は、裏面電極５の抵抗Ｒ１の抵抗値の半分の値まで低減する事ができる。従来構造においては、半導体チップを縦横一定の比率でシュリンクした場合でも、裏面電極５の横方向の抵抗Ｒ１は、その厚みと比抵抗で決まる一定の値に留まるが、本発明においては堀状の開口部４の本数を増やすことにより、横方向の抵抗値を低減する事ができる。   Even if five 200 μm wide trench-shaped openings 4 are formed, the total groove width is 1000 μm, and the trench-shaped openings 4 have sufficient margin for a chip size length of 2000 μm. Can be formed. If the width of the moat-shaped opening 4 is 100 μm, even if X is 10, there is a sufficient margin for the chip size, and the resistance of the moat-shaped opening 4 R2 = (2000/4000) (ρ / t) = (R1) / 2, and the resistance value of the resistance R2 of the metal electrode 6 in the moat-shaped opening 4 can be reduced to half the resistance value of the resistance R1 of the back electrode 5. In the conventional structure, even when the semiconductor chip is shrunk at a constant vertical and horizontal ratio, the lateral resistance R1 of the back electrode 5 remains at a constant value determined by its thickness and specific resistance. By increasing the number of openings 4, the resistance value in the lateral direction can be reduced.

上述したように、本発明の第１の実施形態において、Ｎ＋型ドレイン層７を共通にする２つのＭＯＳ構造の間を、第１のＭＯＳ構造のＮ＋型ソース層１４から、第２のＭＯＳ構造のＮ＋型ソース層１４まで、共通するドレイン領域を経由して、縦方向、横方向、そしてまた、縦方向と連続して流れる電流経路の抵抗値を、従来構造に比して、大きく低減する事ができる。   As described above, in the first embodiment of the present invention, between the two MOS structures sharing the N + type drain layer 7, the N + type source layer 14 having the first MOS structure is connected to the second MOS structure. The resistance value of the current path flowing in the vertical direction, the horizontal direction, and also in the vertical direction through the common drain region to the N + type source layer 14 is greatly reduced as compared with the conventional structure. I can do things.

それでは、図４〜図１１に従い、ドレインを共通にする、２つのＭＯＳ構造を有する本発明の第１の実施形態における、半導体装置の製造方法について以下に説明する。本発明を理解するためには、２つのＭＯＳ構造の内の１つについて、またその内の一部の構造について記載すれば充分なので、そのような図面にて説明を進める。また、本発明の半導体装置は、その表面にハンダバンプ等を形成したＦｌｉｐ Ｃｈｉｐ構成になっているが、発明の要旨の把握には必要ないので、バンプ電極形成前までの工程について説明する。初めに、図４に示すように、Ｎ＋型ドレイン層７となる、例えば厚さ２００μｍの半導体ウエハを準備し、その表面に所定のエピタキシャル法により、Ｎ−型エピ層８を、所定の厚さになるように形成する。   A method for manufacturing a semiconductor device according to the first embodiment of the present invention having two MOS structures having a common drain will now be described with reference to FIGS. In order to understand the present invention, it is sufficient to describe one of the two MOS structures and a part of the structure, and the description will proceed with such drawings. Further, the semiconductor device of the present invention has a flip chip configuration in which solder bumps and the like are formed on the surface thereof, but is not necessary for grasping the gist of the invention, so the steps before the bump electrode formation will be described. First, as shown in FIG. 4, a semiconductor wafer having a thickness of 200 μm, for example, serving as the N + type drain layer 7 is prepared, and an N− type epilayer 8 is formed on the surface by a predetermined epitaxial method. To be formed.

次に図５に示すように、酸化膜９をマスクに、ダメージ軽減用の酸化膜２１を介してＮ−型エピ層８内にＢ（ボロン）等をイオン注入し、Ｎ−型エピ層８の主表面に、Ｐ型チャネル層１０を所定の深さとなるよう形成する。次に、図６に示すように、酸化膜２１上にＣＶＤにより窒化膜や酸化膜等からなる複合膜２１Ａを形成し、所定のフォトリソグラフィ技術によりパターニングする。そして、複合膜２１Ａをマスクとして、半導体層をドライエッチング等し、所定の開口径のトレンチ１１を、Ｐ型チャネル層１０からＮ−型エピ層８の内部まで到達するように形成する。   Next, as shown in FIG. 5, using the oxide film 9 as a mask, B (boron) or the like is ion-implanted into the N − type epi layer 8 through the oxide film 21 for reducing damage, and the N − type epi layer 8. A P-type channel layer 10 is formed to a predetermined depth on the main surface. Next, as shown in FIG. 6, a composite film 21A made of a nitride film, an oxide film or the like is formed on the oxide film 21 by CVD, and is patterned by a predetermined photolithography technique. Then, using the composite film 21A as a mask, the semiconductor layer is subjected to dry etching or the like, and the trench 11 having a predetermined opening diameter is formed so as to reach from the P-type channel layer 10 to the inside of the N − -type epi layer 8.

次に、図７に示すように、複合膜２１Ａをエッチングにより除去した後に、熱処理や、エッチングにより、トレンチ１１内壁のダメージ層を除去し、かつトレンチ１１の開口部コーナー及び底部コーナーを丸くする。次に、熱酸化によりトレンチ１１内壁にゲート絶縁膜１２を形成し、更に、ＣＶＤによりポリシリコン膜２２を、トレンチ１１内を埋め込み、半導体基板の表面全体を被覆するように堆積する。   Next, as shown in FIG. 7, after the composite film 21A is removed by etching, the damaged layer on the inner wall of the trench 11 is removed by heat treatment or etching, and the opening corner and the bottom corner of the trench 11 are rounded. Next, a gate insulating film 12 is formed on the inner wall of the trench 11 by thermal oxidation, and a polysilicon film 22 is deposited by CVD so as to fill the trench 11 and cover the entire surface of the semiconductor substrate.

次に、図８に示すように、ポリシリコン膜２２をエッチバックして、ゲート電極１３を形成する。このとき、好ましくは、図８で示されるように、ゲート電極１３の上端が、Ｐ型チャネル層１０の表面よりも、数μｍ程度下がった位置まで行う。次に、ゲート電極１３上及びゲート絶縁膜１２上を含む半導体基板表面上に、ＣＶＤにより酸化膜を堆積し、その後、Ｐ型チャネル層１０の表面が、露出するまでエッチバックする。これにより、ゲート電極１３の上面側が、ゲート絶縁膜１２と一体的に覆われた状態となる。   Next, as shown in FIG. 8, the polysilicon film 22 is etched back to form the gate electrode 13. At this time, preferably, as shown in FIG. 8, the process is performed until the upper end of the gate electrode 13 is lowered by several μm from the surface of the P-type channel layer 10. Next, an oxide film is deposited by CVD on the surface of the semiconductor substrate including the gate electrode 13 and the gate insulating film 12, and then etched back until the surface of the P-type channel layer 10 is exposed. As a result, the upper surface side of the gate electrode 13 is integrally covered with the gate insulating film 12.

次に、図９に示すように、先ずは、不図示のレジスト膜をマスクとして、Ｐ型チャネル層１０内に、Ｂ（ボロン）等をイオン注入し、その後、熱処理を行うことにより、Ｐ＋型ボディ層１５を形成する。次に、同じく図９に示すように、レジスト膜２３をマスクにして、Ｐ型チャネル層１０の上層部に、Ａｓ（砒素）等をイオン注入し、その後熱処理を行い、Ｎ＋型ソース層１４を、トレンチゲート絶縁膜１２に隣接して形成する。   Next, as shown in FIG. 9, first, B (boron) or the like is ion-implanted into the P-type channel layer 10 using a resist film (not shown) as a mask, and then heat treatment is performed, so that a P + type is obtained. The body layer 15 is formed. Next, as shown in FIG. 9 as well, using the resist film 23 as a mask, As (arsenic) or the like is ion-implanted into the upper layer portion of the P-type channel layer 10, and then heat treatment is performed, so that the N + type source layer 14 is formed. And formed adjacent to the trench gate insulating film 12.

次に、図１０に示すように、ＢＰＳＧ等の絶縁膜を、半導体基板の表面全面に被着し、Ｎ＋型ソース層１４及びＰ＋型ボディ層１５を露出するように、当該絶縁膜をエッチングし、トレンチ１１上に、層間絶縁膜１６を形成する。次にスパッタリング等により、アルミ等の金属材料を半導体基板の表面に被着し、所定のフォトエッチング工程を経て、その後アロイ処理を行うことにより、ソース電極１７を形成する。そして、図示した説明は省略するが、窒化膜等から成るパッシベーション膜を形成する。   Next, as shown in FIG. 10, an insulating film such as BPSG is deposited on the entire surface of the semiconductor substrate, and the insulating film is etched so that the N + type source layer 14 and the P + type body layer 15 are exposed. An interlayer insulating film 16 is formed on the trench 11. Next, a metal material such as aluminum is deposited on the surface of the semiconductor substrate by sputtering or the like, followed by a predetermined photoetching process, and then an alloy process is performed to form the source electrode 17. Although not shown in the figure, a passivation film made of a nitride film or the like is formed.

次に、図１１に示すように、半導体基板の裏面に、図２に示すような堀状の開口部４を形成するため、レジスト等でマスクを形成し、半導体基板を、その裏面側からエッチングする。次に、半導体基板の裏面からバリア層、シード層を形成した後、Ｃｕ層等からなる裏面電極５並びに堀状の開口部４の内壁に対する金属電極６を形成する。この場合、堀状の開口部４を、金属電極６が埋め込むように形成してもよいし、その内壁上に、裏面電極５と同じ厚みの金属電極６を形成しても良い。Ｎ＋型ソース層１４やＰ＋型ボディ層１５の下方のＮ＋型ドレイン層７内に、堀状の開口部４が、Ｎ−型エピ層８の直下の部分で、隣接するＭＯＳ構造それぞれの、ドレイン層間に跨って形成されている。   Next, as shown in FIG. 11, in order to form a trench-shaped opening 4 as shown in FIG. 2 on the back surface of the semiconductor substrate, a mask is formed with a resist or the like, and the semiconductor substrate is etched from the back surface side. To do. Next, after forming a barrier layer and a seed layer from the back surface of the semiconductor substrate, a back electrode 5 made of a Cu layer or the like and a metal electrode 6 for the inner wall of the moat-shaped opening 4 are formed. In this case, the moat-shaped opening 4 may be formed so as to be embedded by the metal electrode 6, or the metal electrode 6 having the same thickness as the back electrode 5 may be formed on the inner wall thereof. In the N + type drain layer 7 below the N + type source layer 14 and the P + type body layer 15, a trench-shaped opening 4 is formed in the portion immediately below the N− type epi layer 8, and the drain of each adjacent MOS structure. It is formed across the layers.

また、堀状の開口部４内壁の中には、裏面電極５と電気的に接続された、低抵抗の金属電極６が形成されているのがわかる。なお、堀状の開口部４の方が、従来のビアホール１０８による開口部に比べて、開口面積が広いため、金属電極６を埋め込むのが容易という利点もある。最後に、半導体基板の表面上には、不図示のハンダバンプ電極を形成する諸作業が行われ、本発明に係る半導体装置は完成する。   It can also be seen that a low-resistance metal electrode 6 electrically connected to the back electrode 5 is formed in the inner wall of the moat-shaped opening 4. The moat-shaped opening 4 has an advantage that the metal electrode 6 can be easily embedded because the opening area is larger than that of the opening formed by the conventional via hole 108. Finally, various operations for forming solder bump electrodes (not shown) are performed on the surface of the semiconductor substrate, and the semiconductor device according to the present invention is completed.

本発明の第２の実施形態である、パワー系の縦型ＭＯＳＦＥＴであって、主にＦｌｉｐ Ｃｈｉｐ用途のドレイン導出電極２４を有する半導体装置について、以下に図面に従って説明する。図において、第１の実施形態と同じ構成については、同一の符号を付し、説明を省略する。図１２に示すように、この場合も、半導体基板の裏面側に堀状の開口部４を設けることは、第１の実施形態と変わりはない。   A semiconductor device having a drain lead-out electrode 24 mainly used for a flip chip will be described below with reference to the drawings. In the figure, the same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted. As shown in FIG. 12, also in this case, the provision of the moat-shaped opening 4 on the back side of the semiconductor substrate is the same as in the first embodiment.

Ｎ＋型ドレイン層７に流れるこむ電流が、堀状の開口部４に形成された金属電極６を、横方向に流れる点も、第１の実施形態と同一である。最後に、半導体基板の表面に形成されたドレイン導出電極２４に向かい縦方向に流れる電流も、流れ込む先が異なるだけで同一である。したがって、かかる構成にすることにより、図１９に示す従来構造に比し、第１の実施形態で得られたと同様、電流経路の抵抗を下げる効果を得る事ができる。図１２では、ドレイン導出電極２４に向かう堀状の開口部４が、垂直に形成されているが、図１３の如く、テーパー形状に形成すれば、より電流経路の抵抗を下げる事ができる。   The point that the current flowing in the N + type drain layer 7 flows in the lateral direction through the metal electrode 6 formed in the moat-shaped opening 4 is the same as in the first embodiment. Finally, the current flowing in the vertical direction toward the drain lead-out electrode 24 formed on the surface of the semiconductor substrate is the same except for the flow destination. Therefore, by adopting such a configuration, it is possible to obtain an effect of reducing the resistance of the current path as compared with the conventional structure shown in FIG. 19 as in the case of the first embodiment. In FIG. 12, the moat-shaped opening 4 toward the drain lead-out electrode 24 is formed vertically, but if it is formed in a tapered shape as shown in FIG. 13, the resistance of the current path can be further reduced.

第３の実施形態について、図１４に従って説明する。第１の実施形態においては、半導体基板の裏面側に、複数本の堀状の開口部４を形成したが、本実施形態においては、半導体チップの裏面全体を、１つのアーチ形状にエッチングした点が特徴となる。図１４においては、その電流経路の抵抗低減という特徴を示せば良いので、トレンチゲート部分やハンダバンプ部分は省略し、図１のＢ−Ｂ間の断面を記載してある。即ち、図１４においては、図の手前側から奥側に向かって、２つのＭＯＳ構造が並んで形成されている。手前のＭＯＳ構造のＮ＋型ソース層１４から、アーチ形状に形成された金属電極６まで、実線の矢印で示すように、縦方向の電流が流れる。   A third embodiment will be described with reference to FIG. In the first embodiment, a plurality of trench-shaped openings 4 are formed on the back surface side of the semiconductor substrate. However, in this embodiment, the entire back surface of the semiconductor chip is etched into one arch shape. Is a feature. In FIG. 14, the feature of reducing the resistance of the current path may be shown. Therefore, the trench gate part and the solder bump part are omitted, and the cross section between BB in FIG. 1 is shown. That is, in FIG. 14, two MOS structures are formed side by side from the near side to the far side in the figure. A vertical current flows from the N + type source layer 14 having the MOS structure in the foreground to the metal electrode 6 formed in an arch shape, as indicated by a solid line arrow.

次にアーチ形状の金属電極６を、手前から奥側のＭＯＳ構造のドレイン領域に向かい、横方向の電流が流れる。最後に奥側のＭＯＳ構造を、金属電極６からＮ＋型ソース層１４に向かって点線の矢印で示した縦方向の電流が流れる。縦方向の電流はアーチ状の金属電極６まで流れ、裏面電極５まで流れる必要ないため、縦方向の抵抗は減少する。また、アーチ状の金属電極６の電流の流れる方向の断面積は、裏面電極５の断面積より当然に大きくなるため、横方向の抵抗も小さくなる。したがって、手前のＭＯＳＦＥＴのＮ＋型ソース層１４からアーチ状金属電極６を経由して、奥側のＭＯＳＦＥＴのＮ＋型ソース層１４に至る電流経路の抵抗低減を図る事ができる。   Next, the arch-shaped metal electrode 6 is directed from the near side to the drain region of the MOS structure on the far side, and a lateral current flows. Finally, the vertical current indicated by the dotted arrow flows from the metal electrode 6 toward the N + type source layer 14 through the MOS structure on the back side. Since the vertical current flows to the arch-shaped metal electrode 6 and does not need to flow to the back electrode 5, the vertical resistance decreases. Moreover, since the cross-sectional area of the arch-shaped metal electrode 6 in the direction in which the current flows is naturally larger than the cross-sectional area of the back electrode 5, the lateral resistance is also reduced. Therefore, it is possible to reduce the resistance of the current path from the N + type source layer 14 of the front MOSFET to the N + type source layer 14 of the backside MOSFET via the arched metal electrode 6.

なお、この場合、半導体基板の裏面側が大きくエッチングされるが、その形状がアーチ状になるため、機械的強度を大きくする事ができるという利点もある。この場合、半導体基板の裏面を、ワックス等をマスクにして、スプレーエッチングで、スプレーの方向と強度等を適切に設定することにより、簡単に安価に、アーチ形状を実現できることから有効な手段である。   In this case, the back surface side of the semiconductor substrate is largely etched, but since the shape is arched, there is an advantage that the mechanical strength can be increased. In this case, the back surface of the semiconductor substrate is an effective means because an arch shape can be realized easily and inexpensively by setting the direction and strength of spraying appropriately by spray etching using wax as a mask. .

本発明は、上記実施形態に限定されるものでなく、発明思想が同一である限り、他の実施形態にも適用ができる。例えば、構成要素のＮ型をＰ型に、Ｐ型をＮ型に変更した半導体装置に於いても同様の効果を得る事ができる。また、上記の実施形態に種々の機能を有する半導体回路が集積された半導体装置にも適用されることは言うまでも無い。   The present invention is not limited to the above embodiment, and can be applied to other embodiments as long as the inventive idea is the same. For example, the same effect can be obtained in a semiconductor device in which the N-type component is changed to the P-type and the P-type is changed to the N-type. It goes without saying that the present invention is also applicable to a semiconductor device in which semiconductor circuits having various functions are integrated.

本発明の第１の実施形態における半導体装置の製造方法を示す平面図である。It is a top view which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. 本発明の第１の実施形態における半導体装置の製造方法を示す裏面図である。It is a back view which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. 本発明の第１の実施形態における半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. 本発明の第１の実施形態における半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. 本発明の第１の実施形態における半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. 本発明の第１の実施形態における半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. 本発明の第１の実施形態における半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. 本発明の第１の実施形態における半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. 本発明の第１の実施形態における半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. 本発明の第１の実施形態における半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. 本発明の第１の実施形態における半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. 本発明の第２の実施形態における半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device in the 2nd Embodiment of this invention. 本発明の第２の実施形態における半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device in the 2nd Embodiment of this invention. 本発明の第３の実施形態における半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device in the 3rd Embodiment of this invention. リチューム電池の充放電時の保護回路である。It is a protection circuit at the time of charge / discharge of a lithium battery. 従来の実施形態における半導体装置の製造方法を示す平面図である。It is a top view which shows the manufacturing method of the semiconductor device in conventional embodiment. 従来の実施形態における半導体装置の製造方法を示す裏面図である。It is a back view which shows the manufacturing method of the semiconductor device in conventional embodiment. 従来の実施形態における半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device in conventional embodiment. 従来の実施形態における半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device in conventional embodiment.

符号の説明Explanation of symbols

１ ソースバンプ電極 ２ ゲートバンプ電極 ３ ゲート配線電極
４ 堀状の開口部 ５ 裏面電極 ６ 金属電極 ７ Ｎ＋型ドレイン層
８ Ｎ−型エピ層 ９ 酸化膜 １０ Ｐ型チャネル層
１１ トレンチ １２ ゲート絶縁膜 １３ ゲート電極 １４ Ｎ＋型ソース層
１５ Ｐ＋型ボディ層 １６ 層間絶縁膜 １７ ソース電極 １８ 窒化膜
１９ ポリイミド膜 ２０ ＵＢＭ（アンダー バンプ メタル） ２１ 酸化膜
２１Ａ 複合膜 ２２ ポリシリコン ２３ レジスト膜
２４ ドレイン導出電極 １０１ リチューム電池 １０２ 半導体装置
１０３ 放電用ＭＯＳＦＥＴ １０３ａ 寄生ダイオード
１０４ 充電用ＭＯＳＦＥＴ １０４ａ 寄生ダイオード
１０５ コントロール用デバイス １０６ ソースバンプ電極
１０７ ゲートバンプ電極 １０８ ビアホール １０９ Ｎ＋型ドレイン層
１１０ Ｎ−型エピ層 １１１ Ｐ型チャネル層 １１２ Ｐ＋型ボディ層
１１３ Ｎ＋型ソース層 １１４ 金属電極 １１５ 裏面電極
１１６ ドレイン導出電極 DESCRIPTION OF SYMBOLS 1 Source bump electrode 2 Gate bump electrode 3 Gate wiring electrode 4 Trench-shaped opening 5 Back surface electrode 6 Metal electrode 7 N + type drain layer 8 N− type epi layer 9 Oxide film 10 P type channel layer 11 Trench 12 Gate insulating film 13 Gate electrode 14 N + type source layer 15 P + type body layer 16 Interlayer insulating film 17 Source electrode 18 Nitride film 19 Polyimide film 20 UBM (under bump metal) 21 Oxide film 21A Composite film 22 Polysilicon 23 Resist film 24 Drain lead electrode 101 Rituum Battery 102 Semiconductor device 103 Discharge MOSFET 103a Parasitic diode 104 Charging MOSFET 104a Parasitic diode 105 Control device 106 Source bump electrode 107 Gate bump electrode 108 Via hole 109 N + type drain layer 11 N- type epitaxial layer 111 P-type channel layer 112 P + -type body layers 113 N + -type source layer 114 metal electrode 115 back electrode 116 drain leading electrode

Claims (9)

半導体基板の表面側に形成されたドレインを共有する２つのＭＯＳ構造と、
前記半導体基板の裏面側に前記ＭＯＳ構造の一方のドレイン領域から、前記ＭＯＳ構造の他方の前記ドレイン領域まで延在して形成された堀状の開口部と、
前記堀状の開口部の中に形成された金属電極と、
前記金属電極と電気的に接続された裏面電極と、を備えることを特徴とする半導体装置。 Two MOS structures sharing a drain formed on the surface side of the semiconductor substrate;
A trench-like opening formed on the back side of the semiconductor substrate extending from one drain region of the MOS structure to the other drain region of the MOS structure;
A metal electrode formed in the moat-shaped opening;
A semiconductor device comprising: a back electrode electrically connected to the metal electrode. 半導体基板の表面にドレイン領域から電流を導出するために形成されたドレイン導出端子と、
前記半導体基板の裏面にソース領域の下方の前記ドレイン領域から前記ドレイン導出端子の下方の領域まで延在して形成された堀状の開口部と、
前記堀状の開口部の中に形成された金属電極と、
前記金属電極と電気的に接続された裏面電極と、を備えることを特徴とする半導体装置。 A drain lead terminal formed to lead current from the drain region to the surface of the semiconductor substrate;
A trench-shaped opening formed on the back surface of the semiconductor substrate extending from the drain region below the source region to a region below the drain lead-out terminal;
A metal electrode formed in the moat-shaped opening;
A semiconductor device comprising: a back electrode electrically connected to the metal electrode. 前記堀状の開口部が前記ドレイン導出端子と接続するように形成されたことを特徴とする請求項２に記載の半導体装置。 The semiconductor device according to claim 2, wherein the trench-shaped opening is formed so as to be connected to the drain lead-out terminal. 前記半導体基板は第１導電型であり、
前記ＭＯＳ構造は、前記半導体基板の表面側に形成された第２導電型のチャネル層と、
複数のゲート絶縁膜及びゲート電極と、
前記ゲート絶縁膜に隣接して形成された第１導電型のソース層と、
前記ソース層と電気的に接続して形成されたソース電極と、
前記ソース層に挟まれ、前記半導体基板の表面から前記チャネル層の内部まで延在して形成された第２導電型のボディ層と、を備え、前記金属電極及び前記裏面電極はドレイン電極であることを特徴とする請求項１乃至請求項３に記載の半導体装置。 The semiconductor substrate is of a first conductivity type;
The MOS structure includes a second conductivity type channel layer formed on a surface side of the semiconductor substrate,
A plurality of gate insulating films and gate electrodes;
A source layer of a first conductivity type formed adjacent to the gate insulating film;
A source electrode formed in electrical connection with the source layer;
A body layer of a second conductivity type sandwiched between the source layers and extending from the surface of the semiconductor substrate to the inside of the channel layer, wherein the metal electrode and the back electrode are drain electrodes The semiconductor device according to any one of claims 1 to 3. 前記開口部がアーチ状の形状で形成されることを特徴とする請求項１乃至請求項４に記載の半導体装置。 The semiconductor device according to claim 1, wherein the opening is formed in an arch shape. 前記ゲート電極はトレンチ型であることを特徴とする請求項１乃至請求項５に記載の半導体装置。 The semiconductor device according to claim 1, wherein the gate electrode is a trench type. 半導体基板の表面側にドレインを共有する２つのＭＯＳ構造を形成する工程と、
前記半導体基板の裏面側に前記ＭＯＳ構造の一方の前記ドレイン領域から、前記ＭＯＳ構造の他方の前記ドレイン領域まで延在する堀状の開口部を形成する工程と、
前記堀状の開口部の中に金属電極を形成する工程と、
前記金属電極と電気的に接続する裏面電極を形成する工程と、を含むことを特徴とする半導体装置の製造方法。 Forming two MOS structures sharing a drain on the surface side of the semiconductor substrate;
Forming a trench-like opening extending from one drain region of the MOS structure to the other drain region of the MOS structure on the back side of the semiconductor substrate;
Forming a metal electrode in the moat-shaped opening;
Forming a back electrode electrically connected to the metal electrode. A method for manufacturing a semiconductor device, comprising: 半導体基板の表面にドレイン領域から電流を導出するためのドレイン導出端子を形成する工程と、
前記半導体基板の裏面側にソースの下方のドレイン領域から前記ドレイン導出端子の下方まで延在する堀状の開口部を形成する工程と、
前記堀状の開口部の中に金属電極を形成する工程と、
前記金属電極と電気的に接続する裏面電極を形成する工程と、を含むことを特徴とする
半導体装置の製造方法。 Forming a drain lead terminal for drawing current from the drain region on the surface of the semiconductor substrate;
Forming a trench-shaped opening extending from the drain region below the source to the bottom of the drain lead terminal on the back side of the semiconductor substrate;
Forming a metal electrode in the moat-shaped opening;
Forming a back electrode electrically connected to the metal electrode. A method for manufacturing a semiconductor device, comprising: 前記堀状の開口部を前記ドレイン導出端子に接続して形成することを特徴とする請求項８に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 8, wherein the trench-shaped opening is formed by being connected to the drain lead-out terminal.
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010103208A (en) * 2008-10-22 2010-05-06 Denso Corp Semiconductor device
WO2016203764A1 (en) * 2015-06-17 2016-12-22 パナソニックＩｐマネジメント株式会社 Semiconductor device and module component
JP2017130527A (en) * 2016-01-19 2017-07-27 力祥半導體股▲フン▼有限公司ＵＢＩＱ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｃｏｒｐ． Semiconductor device
US10355124B1 (en) 2018-03-23 2019-07-16 Kabushiki Kaisha Toshiba Semiconductor device
JP2020035919A (en) * 2018-08-30 2020-03-05 株式会社東芝 Semiconductor device and method of manufacturing the same
EP3836201A1 (en) * 2019-12-11 2021-06-16 Infineon Technologies Austria AG Semiconductor switch element and method of manufacturing the same
TWI747754B (en) * 2018-12-19 2021-11-21 日商新唐科技日本股份有限公司 Semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003101025A (en) * 2001-09-26 2003-04-04 Toshiba Corp Semiconductor device
JP2004134762A (en) * 2002-09-19 2004-04-30 Denso Corp Semiconductor device
JP2007150176A (en) * 2005-11-30 2007-06-14 Sharp Corp Semiconductor device and manufacturing method thereof
JP2008140828A (en) * 2006-11-30 2008-06-19 Rohm Co Ltd Semiconductor device and method for manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003101025A (en) * 2001-09-26 2003-04-04 Toshiba Corp Semiconductor device
JP2004134762A (en) * 2002-09-19 2004-04-30 Denso Corp Semiconductor device
JP2007150176A (en) * 2005-11-30 2007-06-14 Sharp Corp Semiconductor device and manufacturing method thereof
JP2008140828A (en) * 2006-11-30 2008-06-19 Rohm Co Ltd Semiconductor device and method for manufacturing the same

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010103208A (en) * 2008-10-22 2010-05-06 Denso Corp Semiconductor device
WO2016203764A1 (en) * 2015-06-17 2016-12-22 パナソニックＩｐマネジメント株式会社 Semiconductor device and module component
JP2017130527A (en) * 2016-01-19 2017-07-27 力祥半導體股▲フン▼有限公司ＵＢＩＱ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｃｏｒｐ． Semiconductor device
US10355124B1 (en) 2018-03-23 2019-07-16 Kabushiki Kaisha Toshiba Semiconductor device
JP7101085B2 (en) 2018-08-30 2022-07-14 株式会社東芝 Semiconductor device and manufacturing method of semiconductor device
CN110875373A (en) * 2018-08-30 2020-03-10 株式会社东芝 Semiconductor device and method for manufacturing the same
JP2020035919A (en) * 2018-08-30 2020-03-05 株式会社東芝 Semiconductor device and method of manufacturing the same
US11695043B2 (en) * 2018-08-30 2023-07-04 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
CN110875373B (en) * 2018-08-30 2024-01-02 株式会社东芝 Semiconductor device and method for manufacturing the same
TWI747754B (en) * 2018-12-19 2021-11-21 日商新唐科技日本股份有限公司 Semiconductor device
TWI761740B (en) * 2018-12-19 2022-04-21 日商新唐科技日本股份有限公司 semiconductor device
EP3836201A1 (en) * 2019-12-11 2021-06-16 Infineon Technologies Austria AG Semiconductor switch element and method of manufacturing the same
US11581369B2 (en) * 2019-12-11 2023-02-14 Infineon Technologies Austria Ag Semiconductor switch element and method of manufacturing the same

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