JP2018067663A - Diode element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a diode element capable of reducing a resistance value.SOLUTION: A diode element includes a semiconductor layer 11 having a first principal surface 31 and a second principal surface 32. A first impurity region 51 is formed in a surface layer part on the first principal surface 31 side of the semiconductor layer 11. A second impurity region 52 is formed in a surface layer part of the first impurity region 51 so as to be electrically connected to the first impurity region 51. A third impurity region 53 is formed on the second principal surface 32 side of the semiconductor layer 11 with respect to the first impurity region 51 so as to be electrically connected to the first impurity region 51. The diode element also includes an electrode structure 61 including an embedded conductor layer 62 penetrating the first impurity region 51 from the first principal surface 31 of the semiconductor layer 11 so as to be electrically connected to the third impurity region 53 and having a smaller resistivity than a resistivity of the semiconductor layer 11.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a diode element.

Patent Document 1 discloses a semiconductor device as an example of a diode element. The semiconductor device includes an n ⁺⁺ type first semiconductor region. A p ⁻ -type second semiconductor region is formed on the first semiconductor region. Between the first semiconductor region and the second semiconductor region, there is formed a p ⁺ -type third semiconductor region whose bottom is in contact with the first semiconductor region and whose top is in contact with the second semiconductor region. An n ⁺ -type fourth semiconductor region is formed in the surface layer portion of the second semiconductor region.

Japanese Patent Laid-Open No. 2006-72259

  In the structure of the diode element according to Patent Document 1, when a voltage equal to or higher than the threshold voltage is applied between the first semiconductor region and the fourth impurity region, the first semiconductor region, the second semiconductor region, the third semiconductor region, and A current path connecting the fourth impurity regions is formed. In such a structure, since the semiconductor region is a main current path, there is a problem that the resistance value is relatively high. It is considered that the resistance value can be reduced by increasing the impurity concentration of the first semiconductor region. However, in this case, since the characteristics of the diode formed in another region are changed, there is a limit to the reduction of the resistance value due to the increase in the impurity concentration of the first semiconductor region.

  Accordingly, an object of the present invention is to provide a diode element capable of reducing the resistance value.

  A diode element according to one aspect of the present invention includes a semiconductor layer having a first main surface and a second main surface, and a first conductivity type first formed in a surface layer portion of the semiconductor layer on the first main surface side. An impurity region; a second impurity region of a second conductivity type formed in a surface layer portion of the first impurity region and electrically connected to the first impurity region; and the semiconductor layer with respect to the first impurity region A third impurity region of a second conductivity type formed on the second main surface side and electrically connected to the first impurity region, and the semiconductor electrically connected to the third impurity region An electrode structure including a buried conductor layer embedded in the semiconductor layer from the first main surface of the layer through the first impurity region and having a resistivity smaller than the resistivity of the semiconductor layer.

  A diode element according to another aspect of the present invention is a diode element including a semiconductor layer having a first main surface and a second main surface, and having a first element formation region and a second element formation region formed thereon, The first element formation region and the second element formation region are a first conductivity type first impurity region formed in a surface layer portion of the semiconductor layer on the first main surface side, and a surface layer of the first impurity region. A second conductivity type second impurity region electrically connected to the first impurity region, and formed on the second main surface side of the semiconductor layer with respect to the first impurity region, A third impurity region of a second conductivity type electrically connected to the first impurity region, and the first main surface of the semiconductor layer to be electrically connected to the third impurity region from the first main surface. Embedded in the semiconductor layer through the impurity region, and the semiconductor Comprising the electrode structure including a buried conductive layer having a smaller resistivity than, respectively.

  The diode element according to one aspect of the present invention is embedded in the semiconductor layer through the first impurity region from the first main surface of the semiconductor layer so as to be electrically connected to the third impurity region, and the semiconductor layer And an electrode structure including a buried conductor layer having a resistivity lower than that of the electrode. As a result, the resistance value of the current path connecting the electrode structure, the first impurity region, the second impurity region, and the third impurity region can be reduced.

  In the diode element according to another aspect of the present invention, the first impurity region is formed from the first main surface of the semiconductor layer so that the first element formation region and the second element formation region are electrically connected to the third impurity region. It includes an electrode structure including an embedded conductor layer that penetrates and is embedded in the semiconductor layer and that has a resistivity smaller than the resistivity of the semiconductor layer. Thereby, in the first element formation region and the second element formation region, the resistance value of the current path connecting the electrode structure, the first impurity region, the second impurity region, and the third impurity region can be reduced.

FIG. 1 is a perspective view of a chip diode according to a first embodiment of the present invention. FIG. 2 is a top view of the chip diode of FIG. FIG. 3 is a longitudinal sectional view taken along one-dot chain line III-III in FIG. FIG. 4 is an enlarged view showing the first element formation region of FIG. 3 and the surrounding structure. FIG. 5 is a diagram in which the structure on the semiconductor layer of the chip diode of FIG. 1 is removed, and is a plan view for explaining the structure of the main surface of the semiconductor layer. 6 is an electric circuit diagram showing an electrical structure of the chip diode of FIG. FIG. 7 is an electric circuit diagram showing the electrical structure of the chip diode of FIG. FIG. 8 is a longitudinal sectional view of a chip diode according to a second embodiment of the present invention. FIG. 9 is an electric circuit diagram showing an electrical structure of the chip diode of FIG. FIG. 10 is an electric circuit diagram showing the electrical structure of the chip diode of FIG. FIG. 11 is a longitudinal sectional view of a chip diode according to a third embodiment of the present invention. 12 is an electric circuit diagram showing an electrical structure of the chip diode of FIG. FIG. 13 is an electric circuit diagram showing the electrical structure of the chip diode of FIG. FIG. 14 is a schematic enlarged sectional view showing a modification of the electrode structure.

Hereinafter, a plurality of embodiments when a diode element according to the present invention is applied to a chip diode will be described in detail with reference to the accompanying drawings.
<First Embodiment>
FIG. 1 is a perspective view of the chip diode 1 according to the first embodiment of the present invention. FIG. 2 is a top view of the chip diode 1 of FIG. FIG. 3 is a longitudinal sectional view taken along one-dot chain line III-III in FIG. FIG. 4 is an enlarged view showing the structure of the first element formation region 41 in FIG. 3 and its surroundings. FIG. 5 is a diagram in which the structure on the semiconductor layer 11 of the chip diode 1 of FIG. 1 is removed, and is a plan view for explaining the structure of the main surface of the semiconductor layer 11.

The chip diode 1 is a chip component type semiconductor called 0603 (0.6 mm × 0.3 mm) chip, 0402 (0.4 mm × 0.2 mm) chip, 03015 (0.3 mm × 0.15 mm) chip or the like. Device.
With reference to FIG. 1 and FIG. 2, the chip diode 1 includes a rectangular parallelepiped chip body 2. The chip body 2 includes a first main surface 3, an opposite second main surface 4, and side surfaces 5A and 5B connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 of the chip body 2 are formed in a rectangular shape in a plan view (hereinafter simply referred to as “plan view”) viewed from the normal direction of the first main surface 3. Yes. The side surfaces 5 </ b> A and 5 </ b> B of the chip body 2 include a pair of long side surfaces 5 </ b> A extending along the longitudinal direction of the chip body 2 and a pair of short side surfaces 5 </ b> B extending along the short direction of the chip body 2. It is. The aforementioned “0603”, “0402”, “03015” and the like are defined by the length of the long side surface 5A and the length of the short side surface 5B. The thickness of the chip body 2 is, for example, 50 μm or more and 400 μm or less (in this embodiment, about 250 μm).

  On the first main surface 3 of the chip body 2, a first external terminal 6 and a second external terminal 7 are formed with a space therebetween. The first external terminal 6 is formed in a rectangular shape along the short side direction of the chip body 2 at one end in the longitudinal direction of the chip body 2 (left end in FIG. 1). The second external terminal 7 is formed in a rectangular shape along the short direction of the chip body 2 at the other end in the longitudinal direction of the chip body 2 (the end on the right side in FIG. 1).

  Referring to FIG. 3, chip body 2 includes support substrate 10, semiconductor layer 11 formed on support substrate 10, surface insulating layer 12 covering semiconductor layer 11, and first insulating layer 12 covering surface insulating layer 12. The first insulating layer 13 and the second insulating layer 14 covering the first insulating layer 13 are included. The first main surface 3 of the chip body 2 is formed by the second insulating layer 14. The second main surface 4 of the chip body 2 is formed by the support substrate 10. Side surfaces 5 </ b> A and 5 </ b> B of the chip body 2 are formed by the support substrate 10, the semiconductor layer 11, the surface insulating layer 12, the first insulating layer 13 and the second insulating layer 14. The first external terminal 6 and the second external terminal 7 described above are formed on the second insulating layer 14 with a space therebetween. Hereinafter, these structures will be described more specifically.

  In this embodiment, the support substrate 10 is formed in a rectangular parallelepiped shape, and the first main surface 21, the opposite second main surface 22, and the side surface connecting the first main surface 21 and the second main surface 22. 23A, 23B. The second main surface 22 of the support substrate 10 forms the second main surface 4 of the chip body 2. The side surfaces 23A and 23B of the support substrate 10 form part of the side surfaces 5A and 5B of the chip body 2, respectively.

  The support substrate 10 has a stacked structure including a silicon semiconductor substrate 24 and a buried insulating layer 25 formed on the main surface of the semiconductor substrate 24. The semiconductor substrate 24 may be a high-resistance silicon substrate with no impurities added. The buried insulating layer 25 covers the entire main surface of the semiconductor substrate 24 and covers the entire second main surface 32 of the semiconductor layer 11 to electrically insulate the semiconductor layer 11 from the semiconductor substrate 24. doing. In the present embodiment, the buried insulating layer 25 includes silicon oxide and is formed as a BOX (Buried Oxide) layer.

  In this embodiment, the semiconductor layer 11 is formed in a rectangular parallelepiped shape, and the first main surface 31, the opposite second main surface 32, and the side surface connecting the first main surface 31 and the second main surface 32. 33A, 33B. The second major surface 32 of the semiconductor layer 11 is in contact with the first major surface 21 of the support substrate 10 (that is, the buried insulating layer 25). The side surfaces 33A and 33B of the semiconductor layer 11 form part of the side surfaces 5A and 5B of the chip body 2, respectively.

  Referring to FIGS. 3 to 5, a first element formation region 41 and a second element formation region 42 are formed in the semiconductor layer 11. The first element formation region 41 and the second element formation region 42 are regions where diodes are formed. The first element formation region 41 is formed in the semiconductor layer 11 on one side in the longitudinal direction of the semiconductor layer 11. The second element formation region 42 is formed in the semiconductor layer 11 on the other side in the longitudinal direction of the semiconductor layer 11. The first element formation region 41 and the second element formation region 42 face each other in the longitudinal direction of the semiconductor layer 11. In the present embodiment, the first element formation region 41 and the second element formation region 42 are formed in a square shape in plan view parallel to each side of the semiconductor layer 11.

  3 to 5, a first element isolation structure 43 for electrically insulating the first element formation region 41 and the second element formation region 42 from each other is formed in the semiconductor layer 11. In FIG. 5, the first element isolation structure 43 is shown by cross hatching for the sake of clarity. The first element isolation structure 43 includes an endless first portion 44 that surrounds the first element forming region 41 and an endless second portion 45 that surrounds the second element forming region 42. In the present embodiment, the first portion 44 and the second portion 45 of the first element isolation structure 43 are formed in a square shape in plan view parallel to each side of the semiconductor layer 11.

  In the present embodiment, the first portion 44 and the second portion 45 of the first element isolation structure 43 are integrally formed between the first element formation region 41 and the second element formation region 42. The first portion 44 and the second portion 45 that are integrally formed are formed as a separation portion 46 that separates the first element formation region 41 and the second element formation region 42. In the case where the first portion 44 and the second portion 45 are formed with a space therebetween, the isolation portion 46 of the first element isolation structure 43 is a first portion that faces each other across a partial region of the semiconductor layer 11. A portion 44 and a second portion 45 may be included.

  Referring to FIGS. 3 and 4, first element isolation structure 43 has a DTI (Deep Trench Isolation) structure. More specifically, the first element isolation structure 43 is formed along the inner wall of the through hole 47 that exposes the buried insulating layer 25 from the first main surface 31 to the second main surface 32 of the semiconductor layer 11. The first inner wall insulating film 48 and the first material layer 49 embedded in the through hole 47 through the first inner wall insulating film 48 are included. The first inner wall insulating film 48 includes, for example, silicon oxide. The first material layer 49 includes, for example, polysilicon with no impurities added.

The first material layer 49 may include an insulating material. Therefore, the first element isolation structure 43 may have a structure in which an insulator (the first inner wall insulating film 48 and the first material layer 49 made of an insulating material) is embedded in the through hole 47.
The first element formation region 41 is a region defined by the buried insulating layer 25 and the first portion 44 of the first element isolation structure 43 in the semiconductor layer 11. The second element formation region 42 is a region defined by the buried insulating layer 25 and the second portion 45 of the first element isolation structure 43 in the semiconductor layer 11.

Referring to FIGS. 3 and 4, first element formation region 41 includes p-type (first conductivity type) first impurity region 51, n ⁺ -type (second conductivity type) second impurity region 52, and , An n-type third impurity region 53 and an n-type fourth impurity region 54.
With reference to FIGS. 3 and 4, p-type first impurity region 51 is formed on the first main surface 31 side of semiconductor layer 11. The first impurity region 51 includes a p ⁻ type low concentration region 55 and a p type high concentration region 56 having a p type impurity concentration higher than the p type impurity concentration of the p ⁻ type low concentration region 55. The p ⁻ type low concentration region 55 is formed on the first main surface 31 side of the semiconductor layer 11 so as to be exposed from the first main surface 31 of the semiconductor layer 11. The p ⁻ type low concentration region 55 is formed over the entire first element formation region 41 in plan view.

The p-type high concentration region 56 is formed on the second main surface 32 side of the semiconductor layer 11 with respect to the p ⁻ type low concentration region 55. With reference to FIG. 5, the p-type high concentration region 56 is formed in a strip shape extending along the short direction of the semiconductor layer 11 in the present embodiment. With respect to the longitudinal direction of the semiconductor layer 11, the p-type high concentration region 56 traverses one end formed so as to be in contact with the first element isolation structure 43 and the central region of the first element formation region 41, and the first element isolation. And the other end portion formed at an interval from the separation portion 46 of the structure 43 to one side in the longitudinal direction.

The first impurity region 51 has a concentration profile in which the p-type impurity concentration continuously increases from the p ⁻ -type low concentration region 55 toward the p-type high concentration region 56. Thus, in FIG. 3 and FIG. 4, p ^- the boundary region between the type low-concentration region 55 and the p-type high concentration region 56 is clearly shown, in fact, p ^- -type low concentration region 55 The boundary region between the p-type high concentration region 56 is not clearly grasped or cannot be clearly grasped.

Referring to FIGS. 3 and 4, n ⁺ -type second impurity region 52 is formed in the surface layer portion of first impurity region 51 so as to be exposed from first main surface 31 of semiconductor layer 11. Referring to FIG. 5, the first impurity region 51 has an end shape in plan view extending along the short direction of the semiconductor layer 11 in the central region of the first element formation region 41 (in this embodiment, a rectangular shape in plan view). ). A pn junction is formed between the first impurity region 51 and the second impurity region 52. By a pn junction between the first impurity region 51 and the second impurity region 52, a first pn junction having the p ⁻ type low concentration region 55 of the first impurity region 51 as an anode and the second impurity region 52 as a cathode. A diode D1 is formed.

Referring to FIGS. 3 and 4, n-type third impurity region 53 is formed on the second main surface 32 side of semiconductor layer 11 with respect to first impurity region 51. The third impurity region 53 includes an n-type high concentration region 57 and an n ⁻ type low concentration region 58 having an n-type impurity concentration lower than the n-type impurity concentration of the n-type high concentration region 57. The n-type high concentration region 57 and the n ⁻ type low concentration region 58 are formed over the entire first element formation region 41 in plan view.

The n-type high concentration region 57 is formed on the second main surface 32 side of the semiconductor layer 11 with respect to the first impurity region 51 and is electrically connected to the p-type high concentration region 56 of the first impurity region 51. Yes. The n ⁻ type low concentration region 58 is formed on the second main surface 32 side of the semiconductor layer 11 with respect to the n type high concentration region 57, and is electrically connected to the n type high concentration region 57. The n ⁻ type low concentration region 58 forms the second main surface 32 of the semiconductor layer 11 and is in contact with the first main surface 21 of the support substrate 10.

The third impurity region 53 has a concentration profile in which the n-type impurity concentration continuously decreases from the n-type high concentration region 57 toward the n ⁻ -type low concentration region 58. Therefore, in FIG. 3 and FIG. 4, the boundary region between the n-type high concentration region 57 and the n ⁻ type low concentration region 58 is clearly shown, but actually, the n type high concentration region 57 and n ⁻ The boundary region between the mold low concentration regions 58 is not easily grasped or cannot be grasped clearly.

  Between the first impurity region 51 and the third impurity region 53, more specifically, between the p-type high concentration region 56 of the first impurity region 51 and the n-type high concentration region 57 of the third impurity region 53, A pn junction is formed. By the pn junction between the p-type high concentration region 56 of the first impurity region 51 and the n-type high concentration region 57 of the third impurity region 53, the p-type high concentration region 56 of the first impurity region 51 is used as an anode, and A Zener diode DZ having the n-type high concentration region 57 of the third impurity region 53 as a cathode is formed. The zener diode DZ is connected in anti-series with the first pn junction diode D1 through the first impurity region 51.

3 and 4, n-type fourth impurity region 54 is a region between p ⁻ -type low concentration region 55 of first impurity region 51 and n-type high concentration region 57 of third impurity region 53. Is formed. The fourth impurity region 54 is electrically connected to the p ⁻ type low concentration region 55 of the first impurity region 51 and the n type high concentration region 57 of the third impurity region 53. The fourth impurity region 54 is formed in the same layer as the p-type high concentration region 56 of the first impurity region 51.

  Referring to FIG. 5, in the present embodiment, the fourth impurity region 54 is a semiconductor layer 11 in a region between the p-type high concentration region 56 of the first impurity region 51 and the isolation portion 46 of the first element isolation structure 43. It is formed in a belt shape extending along the short direction. With respect to the longitudinal direction of the semiconductor layer 11, the fourth impurity region 54 is formed with a width smaller than the width of the p-type high concentration region 56 of the first impurity region 51. With respect to the longitudinal direction of the semiconductor layer 11, the fourth impurity region 54 is in contact with one end portion formed so as to be in contact with the p-type high concentration region 56 of the first impurity region 51 and the isolation portion 46 of the first element isolation structure 43. And the other end portion formed as described above.

A pn junction is formed between the p ⁻ type low concentration region 55 of the first impurity region 51 and the fourth impurity region 54. By the pn junction between the p ⁻ type low concentration region 55 of the first impurity region 51 and the fourth impurity region 54, the p ⁻ type low concentration region 55 of the first impurity region 51 is used as an anode, and the fourth impurity region A second pn junction diode D2 having a cathode 54 is formed. The second pn junction diode D2 is electrically connected to the Zener diode DZ through the third impurity region 53. The second pn junction diode D2 is connected in parallel to the anti-series circuit of the first pn junction diode D1 and the Zener diode DZ.

With reference to FIGS. 3 and 4, the first impurity region 51, p ^- -type low concentration are formed in the surface layer of the region 55, and, p ^- -type low concentration region higher p-type than the p-type impurity concentration of 55 A p ⁺ type contact region 59 having an impurity concentration is included. The p ⁺ -type contact region 59 is formed in a region facing the fourth impurity region 54 in the surface layer portion of the p ⁻ -type low concentration region 55. Referring to FIG. 5, p ⁺ -type contact region 59 includes second impurity region 52 and isolation portion 46 of first element isolation structure 43 on the other side in the longitudinal direction of semiconductor layer 11 with respect to second impurity region 52. Is formed in a band shape extending along the short direction of the semiconductor layer 11. The p ⁺ -type contact region 59 is formed at a distance from the first element isolation structure 43.

  Referring to FIGS. 3 and 4, first element formation region 41 includes an electrode structure 61. Referring to FIG. 5, the electrode structure 61 is formed in a region between the first element isolation structure 43 and the second impurity region 52 on one side in the longitudinal direction of the semiconductor layer 11 with respect to the second impurity region 52. Has been. The electrode structure 61 is formed in a strip shape extending along the short direction of the semiconductor layer 11. The electrode structure 61 is formed at a distance from the first element isolation structure 43 and the second impurity region 52.

  Referring to FIGS. 3 and 4, electrode structure 61 penetrates through first impurity region 51 from first main surface 31 of semiconductor layer 11 so as to be electrically connected to third impurity region 53. 11 and an insulating film 63 that electrically insulates the embedded conductor layer 62 from the first impurity region 51. The buried conductor layer 62 has a resistivity smaller than the resistivity of the semiconductor layer 11, more specifically, the resistivity of the n-type high concentration region 57 of the third impurity region 53. In this embodiment, a metal buried conductor layer 62 is formed.

The electrode structure 61 is formed so as to penetrate the p ⁻ type low concentration region 55 and the p type high concentration region 56 of the first impurity region 51 from the first main surface 31 of the semiconductor layer 11 so as to reach the third impurity region 53. The buried conductor layer 62 is buried in the trench 64 with the insulating film 63 interposed therebetween. The trench 64 includes a side wall and a bottom wall, and is formed in a tapered shape in which the width of the bottom wall is narrower than the opening width in the longitudinal direction and the short side direction of the semiconductor layer 11. The first impurity region 51 and the third impurity region 53 are exposed from the sidewall of the trench 64. A third impurity region 53 is exposed from the bottom wall of the trench 64.

  The insulating film 63 covers the sidewall of the trench 64 so that the third impurity region 53 is exposed from the trench 64. More specifically, the insulating film 63 covers the entire side wall of the trench 64 so that the third impurity region 53 is exposed from the bottom wall of the trench 64. The insulating film 63 includes one surface (the surface on the semiconductor layer 11 side) and the other surface on the opposite side, and the one surface and the other surface are formed along the side wall of the trench 64.

The buried conductor layer 62 fills the concave space defined by the insulating film 63 and the bottom wall of the trench 64. Between the side surface of the buried conductor layer 62 and the p ⁻ type low concentration region 55 of the first impurity region 51 and between the side surface of the buried conductor layer 62 and the p type high concentration region 56 of the first impurity region 51. The insulating film 63 is interposed, so that the buried conductor layer 62 is electrically insulated from the first impurity region 51. The buried conductor layer 62 is electrically connected to the third impurity region 53 by being joined to the third impurity region 53 exposed from the bottom wall of the trench 64.

Referring to FIGS. 3 and 4, in the present embodiment, third impurity region 53 includes an n ⁺ -type contact region 65 having an n-type impurity concentration higher than the n-type impurity concentration of n-type high concentration region 57. . The n ⁺ -type contact region 65 is formed in a region in contact with the bottom of the trench 64 in the n-type high concentration region 57. More specifically, referring to FIG. 5, n ⁺ -type contact region 65 is formed along the corner portion connecting the bottom wall and side wall of trench 64 in addition to the bottom wall of trench 64. Conductive layer 62 embedded forms an ohmic contact between the n ⁺ -type contact region 65, n-type high-concentration region 57 and the electric third impurity region 53 through the n ⁺ -type contact region 65 Connected. A part of the n ⁺ type contact region 65 may be formed in the n ⁻ type low concentration region 58 of the third impurity region 53.

  Referring to FIG. 4, the buried conductor layer 62 has a stacked structure including a first conductor layer 66 and a second conductor layer 67 in the present embodiment. The first conductor layer 66 includes one surface (the surface on the semiconductor layer 11 side) and the other surface on the opposite side, and the one surface and the other surface are formed along the bottom walls of the insulating film 63 and the trench 64. It has a structure. The first conductor layer 66 may have a single layer structure composed of a titanium nitride layer or a titanium layer, or a laminated structure including a titanium nitride layer and a titanium layer formed on the titanium nitride layer. It may be. The first conductor layer 66 functions as a barrier electrode layer by including a titanium nitride layer and / or a titanium layer. On the other hand, the second conductor layer 67 fills the concave space defined by the first conductor layer 66. The second conductor layer 67 includes, for example, tungsten or copper.

  The electrode structure 61 is electrically connected to the aforementioned Zener diode DZ through the third impurity region 53. Therefore, when a voltage equal to or higher than a predetermined threshold voltage is applied between the anti-series circuit of the first pn junction diode D1 and the Zener diode DZ, the electrode structure 61 having a relatively low resistance value and the first structure having a relatively low resistance value. A current path reaching the anti-series circuit through the n-type high concentration region 57 of the three impurity regions 53 can be formed. Therefore, the resistance value can be reduced in the current path formed in the first element formation region 41.

  3 to 5, the first element formation region 41 includes a second element isolation structure 71 that electrically isolates the p-type high concentration region 56 and the fourth impurity region 54 of the first impurity region 51, and And third element isolation structures 72A and 72B for adjusting a planar view area of the pn junction between the first impurity region 51 and the third impurity region 53 (that is, a planar view area of the Zener diode DZ). In FIG. 5, the second element isolation structure 71 and the third element isolation structures 72A and 72B are shown by cross-hatching for the sake of clarity.

  Referring to FIG. 5, the second element isolation structure 71 has a short side of the semiconductor layer 11 along the boundary region B between the p-type high concentration region 56 of the first impurity region 51 and the fourth impurity region 54. It is formed in a strip shape extending along the direction. In the present embodiment, the second element isolation structure 71 is formed in a region between the boundary region B and the isolation part 46 of the first element isolation structure 43 in plan view. With respect to the short direction of the semiconductor layer 11, one end and the other end of the second element isolation structure 71 are connected to the first element isolation structure 43.

Referring to FIGS. 3 and 4, second element isolation structure 71 has a DTI (Deep Trench Isolation) structure. More specifically, the second element isolation structure 71 penetrates the p ⁻ type low concentration region 55 and the fourth impurity region 54 from the first main surface 31 of the semiconductor layer 11 so as to reach the third impurity region 53. A second inner wall insulating film 74 formed along the inner wall of the formed trench 73 and a second material layer 75 embedded in the trench 73 via the second inner wall insulating film 74 are included. Second inner wall insulating film 74 includes, for example, silicon oxide. Second material layer 75 includes, for example, impurity-free polysilicon.

The second material layer 75 may include an insulating material. Therefore, the second element isolation structure 71 may have a structure in which an insulator (the second inner wall insulating film 74 and the second material layer 75 made of an insulating material) is embedded in the trench 73.
Referring to FIG. 5, third element isolation structures 72A and 72B include third element isolation structure 72A and third element isolation structure 72B formed so as to sandwich second impurity region 52 from both sides in the longitudinal direction of semiconductor layer 11. including. The third element isolation structure 72 </ b> A is formed in a strip shape extending along the short direction of the semiconductor layer 11 on one side in the longitudinal direction of the semiconductor layer 11 with respect to the second impurity region 52. The third element isolation structure 72 </ b> A is formed in a region between the second impurity region 52 and the electrode structure 61. With respect to the short side direction of the semiconductor layer 11, one end and the other end of the third element isolation structure 72 </ b> A are connected to the first element isolation structure 43.

  The third element isolation structure 72 </ b> B is formed in a strip shape extending along the short direction of the semiconductor layer 11 on the other side in the longitudinal direction of the semiconductor layer 11 with respect to the second impurity region 52. In the present embodiment, the third element isolation structure 72 </ b> B is formed in a region between the boundary region B between the p-type high concentration region 56 and the fourth impurity region 54 and the second impurity region 52. With respect to the short direction of the semiconductor layer 11, one end and the other end of the third element isolation structure 72 </ b> B are connected to the first element isolation structure 43.

  Referring to FIGS. 3 and 4, third element isolation structures 72A and 72B have a DTI (Deep Trench Isolation) structure. More specifically, the third element isolation structures 72 </ b> A and 72 </ b> B have trenches 76 formed so as to penetrate the first impurity region 51 from the first main surface 31 of the semiconductor layer 11 so as to reach the third impurity region 53. A third inner wall insulating film 77 formed along the inner wall, and a third material layer 78 embedded in the trench 76 via the third inner wall insulating film 77 are included. Third inner wall insulating film 77 includes, for example, silicon oxide. Third material layer 78 includes, for example, polysilicon to which no impurities are added.

The third material layer 78 may include an insulating material. Accordingly, the third element isolation structures 72A and 72B may have a structure in which an insulator (the third inner wall insulating film 77 and the third material layer 78 made of an insulating material) is embedded in the trench 76.
Referring to FIG. 5, the planar area of the pn junction between the first impurity region 51 and the third impurity region 53 (that is, the planar area of the Zener diode DZ) is the first element isolation structure 43, the third Adjustment is possible by changing the planar view area of the region D surrounded by the element isolation structure 72A and the third element isolation structure 72B. Thereby, the electrical parameters of the Zener diode DZ can be adjusted.

  The second element isolation structure 71 formed in the area between the boundary region B between the p-type high concentration region 56 and the fourth impurity region 54 and the isolation portion 46 of the first element isolation structure 43 provides a p-type high The electrical insulation of the fourth impurity region 54 with respect to the concentration region 56 is enhanced. In addition, the third element isolation structure 72B formed in the region between the boundary region B and the second impurity region 52 enhances the electrical insulation of the p-type high concentration region 56 with respect to the fourth impurity region 54. ing. Therefore, in the present embodiment, the electrical isolation between the p-type high concentration region 56 and the fourth impurity region 54 is enhanced by the second element isolation structure 71 and the third element isolation structure 72B sandwiching the boundary region B. ing.

  In the present embodiment, it can be considered that the third element isolation structure 72B forms the second element isolation structure 71 that electrically isolates the p-type high concentration region 56 and the fourth impurity region 54. In this case, the second element isolation structure 71 is formed on the fourth impurity region 54 side with respect to the boundary region B, and on the p-type high concentration region 56 side with respect to the boundary region B. And the second element isolation structure 71 (third element isolation structure 72B).

  In another form, the second element isolation structure 71 and the third element isolation structure 72B may be integrally formed. That is, the second element isolation structure 71 may be formed that extends from the first major surface 31 of the semiconductor layer 11 through the boundary region B to the third impurity region 53. In yet another embodiment, a plurality of second element isolation structures 71 sandwiching the boundary region B are formed, while a plurality of third element isolation structures 72A and 72B sandwiching the second impurity region 52 are formed. Also good.

  Referring to FIGS. 3 and 5, the second element formation region 42 is similar to the first element formation region 41 in the first impurity region 51, the second impurity region 52, the third impurity region 53, and the fourth impurity region. 54, an electrode structure 61, a second element isolation structure 71, third element isolation structures 72A, 72B, and the like. In the present embodiment, the second element formation region 42 has a structure that is substantially line symmetric with the first element formation region 41 with the first element isolation structure 43 interposed therebetween. Since the structure on the second element formation region 42 side is substantially the same as the structure on the first element formation region 41 side, the structure on the second element formation region 42 side is the same as the structure on the first element formation region 41 side. The reference numerals are attached and the description is omitted.

The structure of the semiconductor layer 11 will be supplemented. The semiconductor layer 11 includes an epitaxial layer 81 formed by epitaxially growing silicon from the first main surface 21 of the support substrate 10 (the main surface of the buried insulating layer 25). More specifically, the semiconductor layer 11 includes an n ⁻ type epitaxial layer 82 formed on the first main surface 21 of the support substrate 10 and an n type epitaxial layer 83 formed on the n ⁻ type epitaxial layer 82. P-type epitaxial layer 84 and n-type epitaxial layer 85 formed on n-type epitaxial layer 83, and p ⁻ -type epitaxial layer 86 formed on p-type epitaxial layer 84 and n-type epitaxial layer 85. Including.

The p ⁻ type epitaxial layer 86 forms the first main surface 31 of the semiconductor layer 11, and the n ⁻ type epitaxial layer 82 forms the second main surface 32 of the semiconductor layer 11. Further, the side surfaces 33A and 33B of the semiconductor layer 11 are formed by the n ⁻ type epitaxial layer 82, the n type epitaxial layer 83, the p type epitaxial layer 84, the n type epitaxial layer 85, and the p ⁻ type epitaxial layer 86.

The p ⁻ type low concentration region 55 and the p type high concentration region 56 of the first impurity region 51 are a partial region of the p ⁻ type epitaxial layer 86 and the p type epitaxial layer 84 partitioned by the first element isolation structure 43. Each region is formed by a part of the region. The second impurity region 52 is formed by introducing an n-type impurity into the surface layer portion of the p ⁻ type epitaxial layer 86 (that is, the p ⁻ type low concentration region 55 of the first impurity region 51).

The n-type high concentration region 57 and the n ⁻ -type low concentration region 58 of the third impurity region 53 are a partial region of the n-type epitaxial layer 83 and the n ⁻ -type epitaxial layer 82 defined by the first element isolation structure 43. Each region is formed by a part of the region. The fourth impurity region 54 is formed by a partial region of the n-type epitaxial layer 85 partitioned by the first element isolation structure 43.

The p ⁺ type contact region 59 is formed by introducing p type impurities into the surface layer portion of the p ⁻ type epitaxial layer 86 (that is, the p ⁻ type low concentration region 55 of the first impurity region 51). The n ⁺ -type contact region 65 is formed by introducing an n-type impurity into the n-type high concentration region 57 exposed from the bottom of the trench 64 of the electrode structure 61.
Referring again to FIG. 3, the surface insulating layer 12 is formed on the first main surface 31 of the semiconductor layer 11 so as to cover the entire area of the first main surface 31 of the semiconductor layer 11. The surface insulating layer 12 may have a laminated structure in which a plurality of insulating films are laminated, or may have a single layer structure made of a single insulating film. The plurality of insulating films or the single insulating film may contain silicon oxide or silicon nitride.

Referring to FIG. 3, in each of first element formation region 41 and second element formation region 42, first contact hole 91 exposing electrode structure 61 and second impurity region are formed in surface insulating layer 12. A second contact hole 92 exposing 52 and a third contact hole 93 exposing the p ⁺ -type contact region 59 are formed.
In each of the first element formation region 41 and the second element formation region 42, a first contact electrode 94 that fills the first contact hole 91 and covers the surface insulation layer 12 on the surface insulation layer 12; A second contact electrode 95 filling the second contact hole 92 and covering the surface insulating layer 12, and a third contact electrode 96 filling the third contact hole 93 and covering the surface insulating layer 12 are formed.

The first contact electrode 94 is electrically connected to the electrode structure 61 in the first contact hole 91. The second contact electrode 95 is electrically connected to the second impurity region 52 in the second contact hole 92. Third contact electrode 96 is electrically connected to p ⁺ -type contact region 59 in third contact hole 93. First contact electrode 94, second contact electrode 95, and third contact electrode 96 include, for example, aluminum.

  Referring to FIG. 3, first insulating layer 13 is formed on surface insulating layer 12 so as to cover first contact electrode 94, second contact electrode 95, and third contact electrode 96. The first insulating layer 13 has a single layer structure of the resin layer 97. The resin layer 97 is, for example, a photosensitive resin, more specifically, a negative type photoresist containing an epoxy resin, or a polyimide resin. The thickness of the first insulating layer 13 is, for example, not less than 5 μm and not more than 100 μm (about 50 μm in this embodiment). The first insulating layer 13 includes a first opening 98 for exposing the first contact electrode 94, a second opening 99 for exposing the second contact electrode 95, and a third opening 100 for exposing the third contact electrode 96. Has been. On the first insulating layer 13, a first connection wiring 101, a second connection wiring 102, and a third connection wiring 103 are formed.

  The first connection wiring 101 is formed, for example, in a rectangular shape in plan view along the short direction of the semiconductor layer 11 immediately below the first external terminal 6. The first connection wiring 101 enters the first opening 98 on the first element formation region 41 side from the surface of the first insulating layer 13, and the first contact electrode on the first element formation region 41 side in the first opening 98. 94 is electrically connected. Accordingly, the first connection wiring 101 is electrically connected to the electrode structure 61 on the first element formation region 41 side.

  The second connection wiring 102 is formed, for example, in a rectangular shape in plan view along the short direction of the semiconductor layer 11 immediately below the second external terminal 7. The second connection wiring 102 enters the first opening 98 on the second element formation region 42 side from the surface of the first insulating layer 13, and the first contact electrode on the second element formation region 42 side in the first opening 98. 94 is electrically connected. Thereby, the second connection wiring 102 is electrically connected to the electrode structure 61 on the second element formation region 42 side.

  The third connection wiring 103 is formed, for example, in a rectangular shape in plan view parallel to each side of the semiconductor layer 11 in the region between the first connection wiring 101 and the second connection wiring 102. The third connection wiring 103 enters the second opening 99 and the third opening 100 on the first element formation region 41 side from the surface of the first insulating layer 13. In addition, the third connection wiring 103 enters the second opening 99 and the third opening 100 on the second element formation region 42 side from the surface of the first insulating layer 13.

The third connection wiring 103 is electrically connected to the second contact electrode 95 and the third contact electrode 96 on the first element formation region 41 side in the second opening 99 and the third opening 100 on the first element formation region 41 side. It is connected to the. The third connection wiring 103 is connected to the second contact electrode 95 and the third contact electrode 96 on the second element formation region 42 side in the second opening 99 and the third opening 100 on the second element formation region 42 side. Electrically connected. Thus, the third connection wire 103, the first element forming region 41 side second impurity regions 52 and ^{the p +} -type contact region 59, and the second impurity regions 52 and ^{the p +} -type second element forming region 42 side The contact region 59 is electrically connected.

  The first connection wiring 101, the second connection wiring 102, and the third connection wiring 103 each have a laminated structure including a first conductor layer 104 and a second conductor layer 105. The first conductor layer 104 includes one surface (the surface on the first insulating layer 13 side) and the other surface on the opposite side, and these one surface and the other surface are the inner wall of the first contact hole 91 and the second contact hole. It has a structure formed along the surface of the first insulating layer 13 including the inner wall of 92 and the inner wall of the third contact hole 93.

  The first conductor layer 104 may have a single layer structure composed of a titanium nitride layer or a titanium layer, or a laminated structure including a titanium nitride layer and a titanium layer formed on the titanium nitride layer. It may be. The first conductor layer 104 functions as a barrier electrode layer by including a titanium nitride layer and / or a titanium layer. On the other hand, the second conductor layer 105 fills the concave space defined by the first conductor layer 104. Second conductor layer 105 includes, for example, copper.

  The second insulating layer 14 is formed on the first insulating layer 13 so as to cover the first connection wiring 101, the second connection wiring 102, and the third connection wiring 103. The second insulating layer 14 has a single layer structure of the resin layer 106. Resin layer 106 includes, for example, a polyimide resin. In the second insulating layer 14, a first pad opening 107 that exposes the first connection wiring 101 and a second pad opening 108 that exposes the second connection wiring 102 are formed.

  The first external terminal 6 is formed in the first pad opening 107. The first external terminal 6 is electrically connected to the first connection wiring 101 in the first pad opening 107. Thus, the first external terminal 6 is electrically connected to the electrode structure 61 on the first element formation region 41 side via the first connection wiring 101. The first external terminal 6 is formed so as to protrude from the second insulating layer 14, and has a covering portion that covers the second insulating layer 14. In the present embodiment, the first external terminal 6 includes tin (Sn). The first external terminal 6 may have a stacked structure in which a plurality of metal films are stacked. The plurality of metal films may include a Ni film, a Pd film, and an Au film stacked in this order from the first connection wiring 101.

  The second external terminal 7 is formed in the second pad opening 108. The second external terminal 7 is electrically connected to the second connection wiring 102 in the second pad opening 108. Thereby, the second external terminal 7 is electrically connected to the electrode structure 61 on the second element formation region 42 side via the second connection wiring 102. The second external terminal 7 is formed so as to protrude from the second insulating layer 14, and has a covering portion that covers the second insulating layer 14. In the present embodiment, the second external terminal 7 includes tin (Sn). The second external terminal 7 may have a stacked structure in which a plurality of metal films are stacked. The plurality of metal films may include a Ni film, a Pd film, and an Au film stacked in this order from the second connection wiring 102.

Next, the electrical structure of the chip diode 1 will be described with reference to FIG. FIG. 6 is an electric circuit diagram showing an electrical structure of the chip diode 1 of FIG.
Referring to FIG. 6, the chip diode 1 includes a first parallel circuit electrically connected to the first external terminal 6 and the second external terminal 7 between the first external terminal 6 and the second external terminal 7. 111 and a series circuit of the second parallel circuit 112 are included. The first parallel circuit 111 is formed by a first pn junction diode D1, a Zener diode DZ, and a second pn junction diode D2 on the first element formation region 41 side, and the second parallel circuit 112 is on the second element formation region 42 side. The first pn junction diode D1, the Zener diode DZ, and the second pn junction diode D2.

  The first parallel circuit 111 and the second parallel circuit 112 include an anti-series circuit 113 of a first pn junction diode D1 and a Zener diode DZ, and a second pn junction diode D2 connected in parallel to the anti-series circuit 113, respectively. The first parallel circuit 111 and the second parallel circuit 112 include an anode connection portion 114 in which the anode of the first pn junction diode D1 and the anode of the Zener diode DZ are electrically connected, the cathode of the Zener diode DZ, and the second pn junction diode D2. A cathode connection portion 115 to which the cathodes of the first pn junction diode D1 and an anode of the second pn junction diode D2 are electrically connected.

  The cathode connection portion 115 of the first parallel circuit 111 is electrically connected to the first external terminal 6. The cathode connection portion 115 of the second parallel circuit 112 is electrically connected to the second external terminal 7. The anode / cathode connection part 116 of the first parallel circuit 111 and the anode / cathode connection part 116 of the second parallel circuit 112 are electrically connected to each other. The anode connection portions 114 of the first parallel circuit 111 and the second parallel circuit 112 are formed by the first impurity region 51 described above. The cathode connection portions 115 of the first parallel circuit 111 and the second parallel circuit 112 are formed by the third impurity region 53 described above. The anode / cathode connection portions 116 of the first parallel circuit 111 and the second parallel circuit 112 are formed by the third connection wiring 103 described above.

When a voltage equal to or higher than a predetermined threshold voltage is applied between the first external terminal 6 and the second external terminal 7 with the first external terminal 6 as a reference potential (for example, ground potential), the reverse of the second parallel circuit 112 side A current flows from the second external terminal 7 to the first external terminal 6 through a series circuit connecting the series circuit 113 and the second pn junction diode D2 on the first parallel circuit 111 side.
When a voltage equal to or higher than a predetermined threshold voltage is applied between the first external terminal 6 and the second external terminal 7 with the second external terminal 7 as a reference potential (for example, ground potential), the reverse of the first parallel circuit 111 side A current flows from the first external terminal 6 to the second external terminal 7 through a series circuit connecting the series circuit 113 and the second pn junction diode D2 on the second parallel circuit 112 side.

When the absolute value of the voltage (potential difference) between the first external terminal 6 and the second external terminal 7 is less than a predetermined threshold voltage, the first parallel terminal 111 and the second parallel circuit 112 cause the first external terminal 6 and the second external terminal 112 to Current is prevented from flowing between the external terminals 7.
According to the chip diode 1 that realizes such an operation, a protection circuit that protects the electric circuit from an overvoltage, ESD (Electro Static Discharge) or the like can be provided by being incorporated in a part of the electric circuit, for example. .

Next, the capacitance between the first external terminal 6 and the second external terminal 7 will be described with reference to FIG. FIG. 7 is an electric circuit diagram showing the electrical structure of the chip diode 1 of FIG.
In FIG. 7, the capacitance of the first pn junction diode D1 is indicated by C1. Further, the capacitance of the second pn junction diode D2 is indicated by C2. Further, the capacitance of the Zener diode DZ is indicated by CZ. The combined capacity CS of the first parallel circuit 111 and the combined capacity CS of the second parallel circuit 112 are substantially equal. Therefore, if the parasitic capacitance between the first external terminal 6 and the second external terminal 7 is CP, the combined capacitance CE between the first external terminal 6 and the second external terminal 7 is expressed by the following equation (1) and ( 2) is given by:

In the present embodiment, the capacitance C1 of the first pn junction diode D1 is, for example, not less than 0.05 pF and not more than 0.5 pF. Further, the capacitance C2 of the second pn junction diode D2 is, for example, not less than 0.05 pF and not more than 0.5 pF. Further, the capacitance CZ of the Zener diode DZ is, for example, not less than 5 pF and not more than 1000 pF.
The electrostatic capacitance CZ of the Zener diode DZ is extremely large compared to the electrostatic capacitance C1 of the first pn junction diode D1 (C1 << CZ). Therefore, the combined capacitance CE of the above equation (1) is approximated by the following equation (3).

  As shown in the above equation (3), the combined capacitance CE between the first external terminal 6 and the second external terminal 7 is a relatively small value of the capacitance C1 and the second pn junction of the first pn junction diode D1. It can be determined based on the capacitance C2 of the diode D2. Therefore, even if the planar view area of the Zener diode DZ is increased and the capacitance CZ of the Zener diode DZ is increased, the combined capacitance CE between the first external terminal 6 and the second external terminal 7 is reduced. Can do. More specifically, the planar view area of the Zener diode DZ is a region D (see FIG. 5) surrounded by the first element isolation structure 43, the third element isolation structure 72A, and the third element isolation structure 72B.

  As described above, in the chip diode 1 according to the present embodiment, the first main surface 31 of the semiconductor layer 11 so that the first element formation region 41 and the second element formation region 42 are electrically connected to the third impurity region 53. To the first impurity region 51 and embedded in the semiconductor layer 11 and includes an electrode structure 61 including a buried conductor layer 62 having a resistivity smaller than the resistivity of the semiconductor layer 11. More specifically, the electrode structure 61 includes a metal buried conductor layer 62 having a resistivity smaller than that of the third impurity region 53. Thereby, in the first element formation region 41 and the second element formation region 42, the resistance value of the current path connecting the electrode structure 61, the third impurity region 53, the second impurity region 52, and the first impurity region 51 is reduced. be able to.

In the chip diode 1 according to the present embodiment, the electrode structure 61 includes an insulating film 63 that electrically isolates the embedded conductor layer 62 from the first impurity region 51. This insulating film 63 is formed between the side surface of the buried conductor layer 62 and the p ⁻ type low concentration region 55 of the first impurity region 51, and between the side surface of the buried conductor layer 62 and the p type high concentration of the first impurity region 51. It is interposed between the regions 56. Thus, since the buried conductor layer 62 can be electrically insulated from each of the p ⁻ type low concentration region 55 and the p type high concentration region 56 of the first impurity region 51, the buried conductor layer 62 and the first conductor region 62 Leakage current between the impurity regions 51 can be suppressed.

  In addition, the chip diode 1 according to the present embodiment includes the first external terminal 6 and the second external terminal 7 that can be externally connected via a conductive bonding material such as solder or metal paste. Therefore, when the chip diode 1 is mounted, it is not necessary to perform a die bonding process using a bonding wire. Thereby, since the connection failure resulting from bonding wire connection does not arise, a yield can be improved. Thereby, the reliability of the device incorporating the chip diode 1 can also be improved.

  In the chip diode 1 according to this embodiment, a thick first insulating layer 13 having a thickness of 5 μm or more and 100 μm or less is formed on the semiconductor layer 11. Thereby, in addition to protecting the semiconductor layer 11, a parasitic capacitance between the first connection wiring 101 and the semiconductor layer 11, a parasitic capacitance between the second connection wiring 102 and the semiconductor layer 11, and The parasitic capacitance between the third connection wiring 103 and the semiconductor layer 11 can be reduced. Thereby, the parasitic capacitance between the first external terminal 6 and the semiconductor layer 11 and the parasitic capacitance between the second external terminal 7 and the semiconductor layer 11 can be reduced. Therefore, it is possible to reduce the parasitic capacitance CP between the first external terminal 6 and the second external terminal 7 shown in the expressions (1) and (3).

In the chip diode 1 according to the present embodiment, the first insulating layer 13 has a single layer structure of the resin layer 97. The resin layer 97 is made of a photosensitive resin, in this embodiment, a negative type photoresist containing an epoxy resin, or a polyimide resin. Thereby, the 1st opening 98, the 2nd opening 99, and the 3rd opening 100 can be formed by exposure and development.
Therefore, when the first opening 98, the second opening 99, and the third opening 100 are formed, the first insulating layer 13 need not be etched. As a result, it is possible to prevent undesired damage caused by etching on the first contact electrode 94, the second contact electrode 95, and the third contact electrode 96 formed below the first insulating layer 13. Thereby, the fluctuation | variation of the resistance component of the 1st contact electrode 94, the 2nd contact electrode 95, and the 3rd contact electrode 96 resulting from damage and contact failure can be suppressed.

  Further, the chip diode 1 according to the present embodiment includes a first parallel circuit 111 and a second parallel circuit 112, and a circuit network having a structure in which the first parallel circuit 111 and the second parallel circuit 112 are connected in series. have. The first parallel circuit 111 and the second parallel circuit 112 include an anti-series circuit 113 of a first pn junction diode D1 and a Zener diode DZ, and a second pn junction diode D2 connected in parallel to the anti-series circuit 113, respectively.

Such a circuit network is formed in the first element formation region 41 and the second element formation region 42 formed in one semiconductor layer 11. Therefore, in forming the first parallel circuit 111 and the second parallel circuit 112, it is not necessary to use a plurality of chip diodes, and it is not necessary to use a plurality of semiconductor layers 11. Therefore, it is possible to provide a small chip diode 1 that is multifunctional and highly functional.
Second Embodiment
FIG. 8 is a longitudinal sectional view of a chip diode 121 according to the second embodiment of the present invention.

The chip diode 121 according to the present embodiment includes a second element formation region 42, a second portion 45 of the first element isolation structure 43, a fourth impurity region 54, a p ⁺ -type contact region 59, a second element isolation structure 71, The third contact hole 93, the third contact electrode 96, the third opening 100, the third connection wiring 103, and the like are not included, and are different from the chip diode 1 according to the first embodiment described above. In FIG. 8, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  In the chip diode 121 according to the present embodiment, the second connection wiring 102 formed immediately below the second external terminal 7 enters the second opening 99 from the surface of the first insulating layer 13, and in the second opening 99. The second contact electrode 95 is electrically connected. As a result, the second external terminal 7 is electrically connected to the second impurity region 52 via the second contact electrode 95.

Next, the electrical structure of the chip diode 121 will be described with reference to FIG. FIG. 9 is an electric circuit diagram showing an electrical structure of the chip diode 121 of FIG.
Referring to FIG. 9, the chip diode 121 includes an anti-series circuit 122 that is electrically connected to the first external terminal 6 and the second external terminal 7 between the first external terminal 6 and the second external terminal 7. including. The reverse series circuit 122 is formed by connecting the first pn junction diode D1 and the Zener diode DZ in reverse series.

  The reverse series circuit 122 includes an anode connection portion 123 in which the anode of the Zener diode DZ and the anode of the first pn junction diode D1 are electrically connected. The anode connection portion 123 of the inverse series circuit 122 is formed by the first impurity region 51 described above. In the reverse series circuit 122, the cathode of the Zener diode DZ is electrically connected to the first external terminal 6, and the cathode of the first pn junction diode D1 is electrically connected to the second external terminal 7.

When a voltage equal to or higher than a predetermined threshold voltage with the second external terminal 7 as a reference potential (for example, ground potential) is applied between the first external terminal 6 and the second external terminal 7, A current flows from the first external terminal 6 to the second external terminal 7.
When the absolute value of the voltage (potential difference) between the first external terminal 6 and the second external terminal 7 is less than a predetermined threshold voltage, the anti-series circuit 122 causes a current to flow between the first external terminal 6 and the second external terminal 7. It is blocked from flowing.

According to the chip diode 121 that realizes such an operation, a protection circuit that protects the electric circuit from an overvoltage, ESD (Electro Static Discharge) or the like can be provided by being incorporated in a part of the electric circuit, for example. .
Next, the capacitance between the first external terminal 6 and the second external terminal 7 will be described with reference to FIG. FIG. 10 is an electric circuit diagram showing the electrical structure of the chip diode 121 of FIG.

  In FIG. 10, the capacitance of the first pn junction diode D1 is indicated by C1. Further, the capacitance of the Zener diode DZ is indicated by CZ. When the parasitic capacitance between the first external terminal 6 and the second external terminal 7 is CP, the combined capacitance CE between the first external terminal 6 and the second external terminal 7 is given by the following equation (4).

  Similar to the first embodiment described above, the electrostatic capacitance CZ of the Zener diode DZ is formed to be extremely larger than the electrostatic capacitance C1 of the first pn junction diode D1 (C1 << CZ). Therefore, the combined capacitance CE of the above equation (4) is approximated by the following equation (5).

  As shown in the above equation (5), the combined capacitance CE between the first external terminal 6 and the second external terminal 7 is determined based on the capacitance C1 of the first pn junction diode D1 that is a relatively small value. be able to. Therefore, even if the planar view area of the Zener diode DZ is increased and the capacitance CZ of the Zener diode DZ is increased, the combined capacitance CE between the first external terminal 6 and the second external terminal 7 is reduced. Can do.

As described above, the chip diode 121 according to the present embodiment can also provide the same operational effects as those described in the first embodiment. The chip diode 121 according to the present embodiment has a structure including the support substrate 10 and the first element isolation structure 43, but the support substrate 10 and the first element isolation structure 43 may be omitted. Thereby, further miniaturization of the chip diode 121 can be achieved.
<Third Embodiment>
FIG. 11 is a longitudinal sectional view of a chip diode 131 according to a third embodiment of the present invention.

The chip diode 131 according to the present embodiment does not include the second element formation region 42, the second portion 45 of the first element isolation structure 43, the third connection wiring 103, and the like according to the above-described first embodiment. It is different from the diode 1. In FIG. 11, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.
In the chip diode 131 according to the present embodiment, the second connection wiring 102 formed immediately below the second external terminal 7 enters the second opening 99 and the third opening 100 from the surface of the first insulating layer 13. The second connection wiring 102 is electrically connected to the second contact electrode 95 in the second opening 99, and is electrically connected to the third contact electrode 96 in the third opening 100. As a result, the second external terminal 7 is electrically connected to the second impurity region 52 via the second contact electrode 95 and electrically connected to the p ⁺ -type contact region 59 via the third contact electrode 96. It is connected to the.

Next, the electrical structure of the chip diode 131 will be described with reference to FIG. FIG. 12 is an electric circuit diagram showing an electrical structure of the chip diode 131 of FIG.
Referring to FIG. 12, the chip diode 131 includes a parallel circuit 132 electrically connected to the first external terminal 6 and the second external terminal 7 between the first external terminal 6 and the second external terminal 7. Including. The parallel circuit 132 includes an anti-series circuit 133 including a first pn junction diode D1 and a Zener diode DZ, and a second pn junction diode D2 connected in parallel to the anti-series circuit 133.

  The parallel circuit 132 has an anode connection part 134 in which the anode of the first pn junction diode D1 and the anode of the Zener diode DZ are electrically connected, and the cathode of the Zener diode DZ and the cathode of the second pn junction diode D2 are electrically connected. A cathode connection portion 135, and an anode / cathode connection portion 136 in which the cathode of the first pn junction diode D1 and the anode of the second pn junction diode D2 are electrically connected. The cathode connection part 135 of the parallel circuit 132 is electrically connected to the first external terminal 6. The anode / cathode connection portion 136 of the parallel circuit 132 is electrically connected to the second external terminal 7.

The anode connection part 134 of the parallel circuit 132 is formed by the first impurity region 51 described above. The cathode connection portion 135 of the parallel circuit 132 is formed by the third impurity region 53 described above. The anode / cathode connection portion 136 of the parallel circuit 132 is formed by the second connection wiring 102 described above.
When a voltage equal to or higher than a predetermined threshold voltage with the second external terminal 7 as a reference potential (for example, ground potential) is applied between the first external terminal 6 and the second external terminal 7, A current flows from the first external terminal 6 to the second external terminal 7.

When a voltage equal to or higher than a predetermined threshold voltage having the first external terminal 6 as a reference potential (for example, ground potential) is applied between the first external terminal 6 and the second external terminal 7, the second pn junction diode D2 is used. A current flows from the second external terminal 7 to the first external terminal 6.
When the absolute value of the voltage (potential difference) between the first external terminal 6 and the second external terminal 7 is less than a predetermined threshold voltage, a current flows between the first external terminal 6 and the second external terminal 7 by the parallel circuit 132. Is prevented.

According to the chip diode 131 that realizes such an operation, for example, a protection circuit that protects the electric circuit from an overvoltage, ESD (Electro Static Discharge) or the like can be provided by being incorporated in a part of the electric circuit. .
Next, the capacitance between the first external terminal 6 and the second external terminal 7 will be described with reference to FIG. FIG. 13 is an electric circuit diagram showing the electrical structure of the chip diode 131 of FIG.

  In FIG. 13, the capacitance of the first pn junction diode D1 is indicated by C1. Further, the capacitance of the second pn junction diode D2 is indicated by C2. Further, the capacitance of the Zener diode DZ is indicated by CZ. If the parasitic capacitance between the first external terminal 6 and the second external terminal 7 is CP, the combined capacitance CE between the first external terminal 6 and the second external terminal 7 is given by the following equation (6).

  Similar to the first embodiment described above, the electrostatic capacitance CZ of the Zener diode DZ is formed to be extremely larger than the electrostatic capacitance C1 of the first pn junction diode D1 (C1 << CZ). Therefore, the combined capacitance CE of the above equation (6) is approximated by the following equation (7).

  As shown in the above equation (7), the combined capacitance CE between the first external terminal 6 and the second external terminal 7 is a relatively small value of the capacitance C1 of the first pn junction diode D1 and the comparison. It can be determined based on the capacitance C2 of the second pn junction diode D2, which is a relatively small value. Therefore, even if the planar view area of the Zener diode DZ is increased and the capacitance CZ of the Zener diode DZ is increased, the combined capacitance CE between the first external terminal 6 and the second external terminal 7 is reduced. Can do.

  As described above, even with the chip diode 131 according to the present embodiment, the same operational effects as those described in the first embodiment can be obtained. The chip diode 131 according to the present embodiment has a structure including the support substrate 10 and the first element isolation structure 43, but the support substrate 10 and the first element isolation structure 43 may be omitted. Thereby, the chip diode 131 can be further reduced in size.

As mentioned above, although embodiment of this invention was described, this invention can also be implemented with another form.
For example, in the first embodiment described above, the chip diode 1 having a structure in which the structure in the first element formation region 41 and the structure in the second element formation region 42 are substantially equal has been described. However, a chip diode having a structure in which the structure in the first element formation region 41 and the structure in the second element formation region 42 are different from each other may be employed. For example, a chip diode having a structure in which only the second pn junction diode D2 is formed in the second element formation region 42 may be employed. For example, a chip diode having a structure in which only the anti-series circuit 113 including the first pn junction diode D1 and the Zener diode DZ is formed in the second element formation region 42 may be employed.

Moreover, the electrode structure 61 according to the first embodiment described above may be changed to a form as shown in FIG. FIG. 14 is a schematic enlarged sectional view showing a modification of the electrode structure 61. In FIG. 14, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.
Referring to FIG. 14, the electrode structure 61 according to the present modification example includes the surface insulating layer 12 and the first impurity region 51 from the surface of the surface insulating layer 12 so as to be electrically connected to the third impurity region 53. And embedded conductor layer 62 embedded in surface insulating layer 12 and semiconductor layer 11, and insulating film 63 that electrically insulates embedded conductor layer 62 from first impurity region 51. More specifically, the electrode structure 61 according to this modification includes a deep trench 141 having the above-described trench 64 and a through-hole 140 formed in the surface insulating layer 12 so as to communicate with the trench 64. The deep trench 141 has a structure in which a buried conductor layer 62 is buried through an insulating film 63.

  The deep trench 141 includes a side wall and a bottom wall. The side wall of the deep trench 141 is formed by the side wall of the trench 64 and the side wall of the through hole 47. The bottom wall of the deep trench 141 is formed by the bottom wall of the trench 64. The deep trench 141 is formed in a tapered shape in which the width of the bottom wall is narrower than the opening width in the longitudinal direction and the short direction of the semiconductor layer 11. The first impurity region 51 and the third impurity region 53 are exposed from the side wall of the deep trench 141. The third impurity region 53 is exposed from the bottom wall of the deep trench 141.

  The insulating film 63 covers the sidewall of the deep trench 141 so that the third impurity region 53 is exposed from the deep trench 141. More specifically, the insulating film 63 covers the entire side wall of the deep trench 141 so that the third impurity region 53 is exposed from the bottom wall of the deep trench 141. The insulating film 63 includes one surface (the surface on the semiconductor layer 11 side) and the other surface on the opposite side, and the one surface and the other surface are formed along the side wall of the deep trench 141.

The buried conductor layer 62 fills the concave space defined by the insulating film 63 and the bottom wall of the deep trench 141. Between the side surface of the buried conductor layer 62 and the p ⁻ type low concentration region 55 of the first impurity region 51 and between the side surface of the buried conductor layer 62 and the p type high concentration region 56 of the first impurity region 51. The insulating film 63 is interposed, so that the buried conductor layer 62 is electrically insulated from the first impurity region 51. The buried conductor layer 62 is electrically connected to the third impurity region 53 by being joined to the third impurity region 53 exposed from the bottom wall of the deep trench 141.

The buried conductor layer 62 has a laminated structure including the first conductor layer 66 and the second conductor layer 67 described above. The upper surface of the buried conductor layer 62 is exposed from the surface of the surface insulating layer 12. The upper surface of the buried conductor layer 62 is formed substantially flush with the surface of the surface insulating layer 12.
According to the electrode structure 61 having such a structure, as shown in FIG. 14, the first contact electrode 94 that is flat with respect to the upper surface of the buried conductor layer 62 and the surface of the surface insulating layer 12 can be formed. . Thereby, the electrode structure 61 and the 1st contact electrode 94 can be connected favorably. Of course, the electrode structure 61 according to the present modification can also be applied to the second and third embodiments described above.

In each of the above-described embodiments, a structure in which the conductivity type of each semiconductor portion is reversed may be employed. That is, the p-type portion may be n-type and the n-type portion may be p-type.
In addition, various design changes can be made within the scope of matters described in the claims. For example, the diode element according to the present invention is not limited to a chip diode, and in a semiconductor device having a structure in which a semiconductor chip is sealed (packaged) with a lead terminal together with a lead terminal, in a partial region of the semiconductor chip, or The semiconductor chip can be applied. The diode element according to the present invention includes LSI (Large Scale Integration), SSI (Small Scale Integration), MSI (Medium Scale Integration), VLSI (Very Large Scale Integration), ULSI (Ultra-Very Large Scale Integration), etc. A semiconductor device including a semiconductor chip on which various integrated circuits are formed can be applied to a partial region of the semiconductor chip.

1 Chip diode (diode element)
6 first external terminal 7 second external terminal 11 semiconductor layer 25 buried insulating layer (insulating layer)
31 First main surface 32 of semiconductor layer 32 Second main surface 41 of semiconductor layer First element formation region 42 Second element formation region 43 First element isolation structure 47 Through hole 48 First inner wall insulating film 49 First material layer 51 First 1 impurity region 52 2nd impurity region 53 3rd impurity region 54 4th impurity region 55 p ^- type low concentration region (low concentration region)
56 p-type high concentration region (high concentration region)
61 Electrode structure 62 Embedded conductor layer 63 Insulating film 71 Second element isolation structure 73 Trench 74 Second inner wall insulating film 75 Second material layer 111 First parallel circuit 112 Second parallel circuit 113 Inverse series circuit 121 Chip diode 122 Inverse series Circuit 131 Chip diode 132 Parallel circuit 133 Inverse series circuit D1 First pn junction diode D2 Second pn junction diode DZ Zener diode

Claims (25)

A semiconductor layer having a first main surface and a second main surface;
A first impurity region of a first conductivity type formed in a surface layer portion on the first main surface side of the semiconductor layer;
A second impurity region of a second conductivity type formed in a surface layer portion of the first impurity region and electrically connected to the first impurity region;
A third impurity region of a second conductivity type formed on the second main surface side of the semiconductor layer with respect to the first impurity region and electrically connected to the first impurity region;
Embedded in the semiconductor layer through the first impurity region from the first main surface of the semiconductor layer so as to be electrically connected to the third impurity region, and more than the resistivity of the semiconductor layer And an electrode structure including a buried conductor layer having a low resistivity.   The diode element according to claim 1, wherein the electrode structure includes an insulating film that electrically isolates the buried conductor layer from the first impurity region.   3. The diode element according to claim 2, wherein the insulating film covers a side surface of the buried conductor layer between the buried conductor layer and the first impurity region. The first impurity region is formed on the first main surface side of the semiconductor layer and on the second main surface side of the semiconductor layer with respect to the low concentration region. A high concentration region having a first conductivity type impurity concentration higher than the first conductivity type impurity concentration of the region,
The second impurity region is electrically connected to the low concentration region of the first impurity region;
4. The diode element according to claim 1, wherein the third impurity region is electrically connected to the high concentration region of the first impurity region. 5. The second impurity region forms a pn junction diode with the low concentration region of the first impurity region,
5. The diode element according to claim 4, wherein the third impurity region forms a Zener diode with the high concentration region of the first impurity region.   6. The diode element according to claim 5, wherein the Zener diode is connected in anti-series with the pn junction diode. The first impurity region is formed on the first main surface side of the semiconductor layer and on the second main surface side of the semiconductor layer with respect to the low concentration region. A high concentration region having a first conductivity type impurity concentration higher than the first conductivity type impurity concentration of the region,
The second impurity region is electrically connected to the low concentration region of the first impurity region;
The third impurity region is electrically connected to the high concentration region of the first impurity region;
A second conductivity type second electrode formed on the second main surface side of the semiconductor layer with respect to the low concentration region of the first impurity region and electrically connected to the low concentration region of the first impurity region. The diode element according to any one of claims 1 to 3, further comprising four impurity regions.   The fourth impurity region is formed in a region between the low-concentration region of the first impurity region and the third impurity region, and in addition to the low-concentration region of the first impurity region, The diode element according to claim 7, wherein the diode element is electrically connected to the three impurity regions. The second impurity region forms a first pn junction diode with the low concentration region of the first impurity region,
The third impurity region forms a Zener diode with the high concentration region of the first impurity region,
9. The diode element according to claim 7, wherein the fourth impurity region forms a second pn junction diode with the low-concentration region of the first impurity region. The Zener diode is connected in anti-series with the first pn junction diode, thereby forming an anti-series circuit with the first pn junction diode,
The diode element according to claim 9, wherein the second pn junction diode is connected in parallel to the anti-series circuit.   The first impurity region is formed so as to penetrate from the first main surface of the semiconductor layer so as to reach the third impurity region, and the high concentration region and the fourth impurity region of the first impurity region are electrically connected to each other. The diode element according to any one of claims 7 to 10, further comprising an element isolation structure for isolating.   The element isolation structure includes an inner wall insulating film formed along an inner wall of a trench formed through the first impurity region from the first main surface of the semiconductor layer so as to reach the third impurity region. The diode element according to claim 11, having a DTI (Deep Trench Isolation) structure including a material layer embedded in the trench through the inner wall insulating film. A diode element including a semiconductor layer having a first main surface and a second main surface, wherein the first element formation region and the second element formation region are formed,
The first element formation region and the second element formation region are:
A first impurity region of a first conductivity type formed in a surface layer portion on the first main surface side of the semiconductor layer;
A second impurity region of a second conductivity type formed in a surface layer portion of the first impurity region and electrically connected to the first impurity region;
A third impurity region of a second conductivity type formed on the second main surface side of the semiconductor layer with respect to the first impurity region and electrically connected to the first impurity region;
Embedded in the semiconductor layer through the first impurity region from the first main surface of the semiconductor layer so as to be electrically connected to the third impurity region, and more than the resistivity of the semiconductor layer And an electrode structure including a buried conductor layer having a low resistivity.   The diode element according to claim 13, wherein the electrode structure includes an insulating film that electrically isolates the buried conductor layer from the first impurity region.   The diode element according to claim 14, wherein the insulating film covers a side surface of the buried conductor layer between the electrode structure and the first impurity region. The first impurity region is formed on the first main surface side of the semiconductor layer and on the second main surface side of the semiconductor layer with respect to the low concentration region. A high concentration region having a first conductivity type impurity concentration higher than the first conductivity type impurity concentration of the region,
The second impurity region is electrically connected to the low concentration region of the first impurity region;
The diode element according to any one of claims 13 to 15, wherein the third impurity region is electrically connected to the high concentration region of the first impurity region. The second impurity region forms a pn junction diode with the low concentration region of the first impurity region,
The diode element according to claim 16, wherein the third impurity region forms a Zener diode with the high concentration region of the first impurity region.   The diode element according to claim 17, wherein the Zener diode is connected in anti-series with the pn junction diode. The first impurity region is formed on the first main surface side of the semiconductor layer and on the second main surface side of the semiconductor layer with respect to the low concentration region. A high concentration region having a first conductivity type impurity concentration higher than the first conductivity type impurity concentration of the region,
The second impurity region is electrically connected to the low concentration region of the first impurity region;
The third impurity region is electrically connected to the high concentration region of the first impurity region;
The first element formation region and the second element formation region are:
A second conductivity type second electrode formed on the second main surface side of the semiconductor layer with respect to the low concentration region of the first impurity region and electrically connected to the low concentration region of the first impurity region. The diode element according to claim 13, further comprising four impurity regions.   The fourth impurity region is formed in a region between the low concentration region of the first impurity region and the third impurity region, and in addition to the low concentration region of the first impurity region, the third impurity region The diode element according to claim 19, which is electrically connected to the region. The second impurity region forms a first pn junction diode with the low concentration region of the first impurity region,
The third impurity region forms a Zener diode with the high concentration region of the first impurity region,
21. The diode element according to claim 19, wherein the fourth impurity region forms a second pn junction diode with the low-concentration region of the first impurity region. A first parallel circuit formed in the first element formation region, wherein the second pn junction diode is connected in parallel to an anti-series circuit of the first pn junction diode and the Zener diode;
A second parallel circuit formed in the second element formation region, wherein the second pn junction diode is connected in parallel to an anti-series circuit of the first pn junction diode and the Zener diode;
The diode element according to claim 21, wherein the first parallel circuit and the second parallel circuit are connected in series.   The diode element according to any one of claims 13 to 22, further comprising an element isolation structure formed in the semiconductor layer and electrically isolating the first element formation region and the second element formation region. An insulating layer covering the second main surface of the semiconductor layer;
The element isolation structure includes an inner wall insulating film formed along an inner wall of a through hole that penetrates the second main surface from the first main surface of the semiconductor layer to expose the insulating layer, and the inner wall insulating film 24. The diode element according to claim 23, wherein the diode element has a DTI (Deep Trench Isolation) structure including a material layer embedded in the through hole. A first external terminal electrically connected to the electrode structure in the first element formation region;
The diode element as described in any one of Claims 13-24 including the 2nd external terminal electrically connected with the said electrode structure of a said 2nd element formation area.

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