JPS63275136A - Semiconductor device provided with insulating isolation region - Google Patents

Abstract

PURPOSE:To realize a substrate potential taking-out structure of small area with low resistance, by taking out a substrate potential from a conductive region formed by burying conductive material such as metal in a groove having an insulating film on the side surface thereof. CONSTITUTION:The title device is provided with the following; grooves 20 penetrating through a first and a second conducting layers 12, 13 and reaching a substrate 11, an insulating layer 21 formed on both sides of groove, and a conductive region 22 buried in the groove 20 and being in contact with the substrate 11. The substrate 11 and a wiring 18 for elements are electrically connected by the conductive region 22. As the wiring 18 for elements is formed on a semiconductor surface matching with the conductive region 22, the substrate 11 and the wiring layer 18 are electrically connected via the conductive region 22, so that the electric potential of the substrate 11 is lead out. Thereby, the potential of a substrate having a small area, a low resistance and a small capacitance can be taken out.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device including an insulating isolation region.
In particular, the present invention relates to a semiconductor device facing an insulating isolation region suitable for bipolar integrated circuits.

[Prior Art] As integrated circuits become more highly integrated, there is a demand for miniaturization of insulation isolation regions between elements. For this reason, a groove insulation isolation technique in which the insulation isolation region is groove-shaped has been developed. When this trench insulation isolation technology is applied to bipolar integrated circuits, the isolation valve @mitsu can separate the highly concentrated buried layer that becomes the sub collector, allowing for high W! Even if this high-concentration buried layer is formed over the entire surface of the substrate without selectively forming the A-degree buried layer, it is possible to insulate and isolate the elements.

However, in bipolar integrated circuits, it is necessary to apply a power supply potential to the substrate, and it is necessary to connect the substrate and circuit wiring through a diffusion layer. For this reason,
A high-concentration buried layer that will serve as a sub-collector cannot be formed in a region where the substrate potential is taken out, that is, a region where the substrate and circuit wiring are connected. Therefore, similarly to the selective oxidation method, it is necessary to selectively form the buried layer of the sub collector in advance, excluding the substrate potential extraction region.

For example, as shown in FIG. 4, the n+ buried layer 2 is formed over the entire surface of the P-type silicon substrate 1 except for the substrate potential extraction region. A p+ buried layer 3 is formed in the substrate potential extraction region. Further, an n'' epitaxial layer 4 is formed on the buried layer 2, and a p1 diffusion layer 5 is formed on the buried layer 3 by diffusion from the surface of the epitaxial layer 4. 1 and the wiring 9 on the surface of the semiconductor device are electrically connected via the p1 buried layer 3 and the 7p+ diffusion layer 5, and the substrate potential is led to the wiring 9.
The buried layer 2 and the epitaxial layer 4 are insulated into small regions by an insulating isolation groove 10.

[Problems to be solved by the invention] However, in the above-mentioned conventional semiconductor device,
It is necessary to selectively form the N-type buried layer 2 which becomes the sub-collector, and it is also necessary to form the buried layer 3 and the diffusion layer 5 in the region from which the substrate potential is taken out. Therefore, the manufacturing process of the semiconductor device is complicated.

In fact, if the connection resistance of the diffusion layer 5 from which the substrate potential is derived is high, the substrate potential will rise and lag-up will occur, so it is necessary to increase the concentration of the diffusion layer 5 and to increase the area of the diffusion layer 5. be. As a result, the element area increases and
There is a problem in that the capacitance between the collector and the substrate increases, which slows down the operating speed of the semiconductor device.

This invention was made in view of such circumstances, and
It is an object of the present invention to provide a semiconductor device having an insulating isolation region, which has a small area and low resistance substrate potential extraction structure, has a high operating speed, and is simple to manufacture.

Means for Solving Problem U] A semiconductor device including an insulating isolation region according to the present invention includes a first conductive layer of a second S conductivity type formed on a semiconductor substrate of a first conductivity type; , a second conductive layer formed on this first conductive layer.
A semiconductor device comprising: a second conductive layer having a conductivity type of a groove penetrating the conductive layer to reach the substrate; an insulating layer formed on the side surface of the groove; and a conductive region immediately disposed within the groove and in contact with the substrate; is characterized in that it electrically connects the substrate and the element wiring.

[Operation] In the present invention, the potential of the substrate is led to the surface of the semiconductor device by the conductive region buried in the groove that penetrates the first and second conductive layers and reaches the substrate, and the potential of the substrate is drawn out to the surface of the semiconductor device. The wiring on the surface is electrically connected. In addition, since an insulating layer is formed on the side surface of the plate, this conductive region is
and is electrically isolated from the second conductive layer. With such a conductive region, it is possible to obtain a substrate potential extraction structure with a small area, low resistance, and low capacitance.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a sectional view showing a semiconductor device including an insulating isolation region according to an embodiment of the present invention.

An n+ buried layer 12 that acts as a sub-collector is formed on a P-type silicon substrate 11.
An n--bitaxial layer 13 is epitaxially grown on the substrate. Insulating isolation trenches 14 are provided at appropriate locations in this semiconductor device, and the buried layer 12 and (1) pitaxial layer 13 are partitioned into minute regions by the insulating isolation trenches 14, and are electrically connected to other regions. will be cut off. In this isolation groove 14, a p1 channel stopper layer 15 is formed at the bottom thereof, and then a silicon oxide film (insulating film) 17 is formed to cover the bottom and side surfaces of the groove. Polycrystalline silicon is immediately placed inside the groove to form a polycrystalline silicon region 16. The surfaces of the nz pitaxial layer 13 and the polycrystalline silicon region 16 are covered with an insulating silicon oxide film 17.

A derivation region 19 for extracting the potential of the substrate 11 is provided in a region partitioned by the insulating isolation trench 14 .

In this lead-out region 19, a vortex 20 is formed that penetrates the buried layer 12 and epitaxial layer 13 and reaches the substrate 11, and an insulating silicon oxide film 21 is formed on the side surface of this vortex 20. There is.

Then, a suitable metal (for example, tungsten or aluminum) is buried in the groove 20 to form the conductive region 2.
2 is formed. A wiring layer 18 for the element is formed on the surface of the semiconductor device aligned with the conductive region 22. Thereby, the substrate 11 and the wiring layer 18 are electrically connected via the conductive region 22, and the potential of the substrate 11 is derived.

In the semiconductor device configured in this manner, the isolation trench 14 electrically isolates the region partitioned by the trench 14 from other regions, thereby insulating and isolating each element.

On the other hand, the potential of the substrate 11 is taken out by the conductive region 22. This conductive region 22 includes an n+ buried layer 12 and an n- epitaxial layer 13 formed over the entire surface of the substrate 11.
It penetrates through and is in contact with the silicon substrate 11, and is insulated from the n+ buried layer 12 and the n- epitaxial layer 13 by a silicon oxide film 21. Moreover, this conductive region 22
is electrically connected to at least a portion of the wiring layer 18 that interconnects the elements. Therefore, as shown in Figure 4,
Compared to conventional semiconductor devices in which the substrate potential is taken out through the p+ immediate implant 3 and the p+ diffusion layer 5, the substrate potential take-out structure of the present invention requires a smaller occupied area, and has low resistance and low resistance. It is capacity. In addition, this structure is similar to the substrate 11
The n + buried layer 12 can be formed even if it exists over the entire surface of the substrate, and the manufacturing process of an integrated circuit having groove insulation isolation can be simplified.

Next, the manufacturing process of this semiconductor device is shown in FIG. 2(a).
This will be explained with reference to (d). First, an n+ buried layer 12 and an n- epitaxial 1 full layer 13 are laminated over the entire surface of a P-type silicon substrate 11, and an insulating isolation trench 14 having a polycrystalline silicon region 16 and a silicon oxide film 17 therein is formed. Form and cover [Figure 2(a)]. Next, a silicon nitride film 30 is grown, and the silicon nitride film 30 and silicon oxide film 1 are selectively grown using the photoresist 31 as a mask.
Remove 7. Furthermore, does silicon etching reach the silicon substrate 11? 1i20 is formed [FIG. 2(b)]. Next, an oxide film 21 is formed on the side wall surface of the trench 20, and only the oxide film formed at the bottom of the trench 20 is removed by dry etching [FIG. 2(C)]. Thereafter, the metal film 32 is grown by a method such as CVD which has an excellent step coverage rate until the trench 20 is completely buried [FIG. 2(d)]. Next, by selectively removing the metal Wi 32 using the photoresist 33 as a mask, the semiconductor device according to the embodiment of the invention shown in FIG. 1 is manufactured.

Next, with reference to FIGS. 3(a) and 3(b), another method of manufacturing a semiconductor device having an insulating isolation region according to an embodiment of the present invention will be described. In this manufacturing method, a metal such as tungsten (W) or aluminum (A1) is selectively grown only inside the groove 20 from the state shown in FIG. Figure (a)]
. Thereafter, a metal film 35 is grown on the entire surface, and the metal film 35 is selectively removed using a photoresist 36 mask.
3(b)], the semiconductor device according to the embodiment of the present invention shown in FIG. 1 is manufactured.

[Effects of the Invention] As explained above, the present invention forms a conductive region by burying a conductive material such as a metal in a trench having an insulating film on its side surface, and extracts a substrate potential from the conductive region. Therefore, the substrate potential extraction structure can be covered with a small area and low resistance.

Therefore, the capacitance between the collector and the substrate does not increase, and the operating speed is high. Furthermore, even if a buried layer serving as a sub-collector is formed over the entire surface, this substrate potential extraction structure can be formed, so that the manufacturing process can be extremely simplified.

Therefore, according to the present invention, a highly reliable and high performance semiconductor device can be obtained.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention, FIGS. 2(a) to (d) are cross-sectional views showing a manufacturing method thereof, and FIGS. 3(a) and (b) are FIG. 4 is a cross-sectional view showing a conventional semiconductor device.

Claims (1)

[Claims] a first conductive layer of a second conductive type formed on a semiconductor substrate of a first conductive type; a second conductive layer of a second conductive type formed on the first conductive layer; In a semiconductor device including an insulating isolation region that insulates and isolates a first and a second conductive layer for each predetermined region, the first and second conductive layers are penetrated to reach the substrate. an insulating layer formed on the side surface of the groove, and a conductive region buried in the groove and in contact with the substrate, and the conductive region electrically connects the substrate and the element wiring. A semiconductor device comprising an insulating isolation region.